1/*
2 * NOTE: Autogenerated file by gen_board_pinctrl.py
3 * for MK82FN256VLL15/signal_configuration.xml
4 *
5 * Copyright (c) 2022, NXP
6 * SPDX-License-Identifier: Apache-2.0
7 */
8
9
10#include <nxp/kinetis/MK82FN256VLL15-pinctrl.h>
11
12&pinctrl {
13	adc0_default: adc0_default {
14		group0 {
15			pinmux = <ADC0_SE15_PTC1>;
16			drive-strength = "low";
17			slew-rate = "fast";
18		};
19	};
20
21	ftm3_default: ftm3_default {
22		group0 {
23			pinmux = <FTM3_CH4_PTC8>,
24				<FTM3_CH5_PTC9>,
25				<FTM3_CH6_PTC10>;
26			drive-strength = "low";
27			slew-rate = "fast";
28		};
29	};
30
31	i2c0_default: i2c0_default {
32		group0 {
33			pinmux = <I2C0_SCL_PTB2>,
34				<I2C0_SDA_PTB3>;
35			drive-strength = "low";
36			drive-open-drain;
37			slew-rate = "fast";
38		};
39	};
40
41	i2c3_default: i2c3_default {
42		group0 {
43			pinmux = <I2C3_SCL_PTA2>,
44				<I2C3_SDA_PTA1>;
45			drive-strength = "low";
46			drive-open-drain;
47			bias-pull-up;
48			slew-rate = "fast";
49		};
50	};
51
52	lpuart0_default: lpuart0_default {
53		group0 {
54			pinmux = <LPUART0_RX_PTB16>,
55				<LPUART0_TX_PTB17>;
56			drive-strength = "low";
57			slew-rate = "fast";
58		};
59	};
60
61	lpuart4_default: lpuart4_default {
62		group0 {
63			pinmux = <LPUART4_RX_PTC14>,
64				<LPUART4_TX_PTC15>;
65			drive-strength = "low";
66			slew-rate = "fast";
67		};
68	};
69
70	spi0_default: spi0_default {
71		group0 {
72			pinmux = <SPI0_SCK_PTD1>,
73				<SPI0_SOUT_PTD2>,
74				<SPI0_SIN_PTD3>,
75				<SPI0_PCS1_PTD4>;
76			drive-strength = "low";
77			slew-rate = "fast";
78		};
79	};
80
81	spi1_default: spi1_default {
82		group0 {
83			pinmux = <SPI1_SCK_PTE1>,
84				<SPI1_SOUT_PTE2>,
85				<SPI1_SIN_PTE4>,
86				<SPI1_PCS0_PTE5>;
87			drive-strength = "low";
88			slew-rate = "fast";
89		};
90	};
91
92};
93