1 /*
2 * Copyright (c) 2019 Linaro Limited
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 /**
8 * @file
9 * @brief System/hardware module for STM32H7 CM7 processor
10 */
11
12 #include <zephyr/kernel.h>
13 #include <zephyr/device.h>
14 #include <zephyr/init.h>
15 #include <soc.h>
16 #include <stm32_ll_bus.h>
17 #include <stm32_ll_pwr.h>
18 #include <stm32_ll_rcc.h>
19 #include <stm32_ll_system.h>
20 #include "stm32_hsem.h"
21
22 #include <cmsis_core.h>
23
24 #if defined(CONFIG_STM32H7_DUAL_CORE)
stm32h7_m4_wakeup(void)25 static int stm32h7_m4_wakeup(void)
26 {
27
28 /* HW semaphore and SysCfg Clock enable */
29 LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_HSEM);
30 LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_SYSCFG);
31
32 if (READ_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4)) {
33 /* Cortex-M4 is waiting for end of system initialization made by
34 * Cortex-M7. This initialization is now finished,
35 * then Cortex-M7 takes HSEM so that CM4 can continue running.
36 */
37 LL_HSEM_1StepLock(HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID);
38 } else if (IS_ENABLED(CONFIG_STM32H7_BOOT_M4_AT_INIT)) {
39 /* CM4 is not started at boot, start it now */
40 LL_RCC_ForceCM4Boot();
41 }
42
43 return 0;
44 }
45 #endif /* CONFIG_STM32H7_DUAL_CORE */
46
47 /**
48 * @brief Perform basic hardware initialization at boot.
49 *
50 * This needs to be run from the very beginning.
51 * So the init priority has to be 0 (zero).
52 *
53 * @return 0
54 */
stm32h7_init(void)55 static int stm32h7_init(void)
56 {
57 SCB_EnableICache();
58
59 if (IS_ENABLED(CONFIG_DCACHE)) {
60 if (!(SCB->CCR & SCB_CCR_DC_Msk)) {
61 SCB_EnableDCache();
62 }
63 }
64
65 /* Update CMSIS SystemCoreClock variable (HCLK) */
66 /* At reset, system core clock is set to 64 MHz from HSI */
67 SystemCoreClock = 64000000;
68
69 /* Power Configuration */
70 #if !defined(SMPS) && \
71 (defined(CONFIG_POWER_SUPPLY_DIRECT_SMPS) || \
72 defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_LDO) || \
73 defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_LDO) || \
74 defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT_AND_LDO) || \
75 defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT_AND_LDO) || \
76 defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT) || \
77 defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT))
78 #error Unsupported configuration: Selected SoC do not support SMPS
79 #endif
80 #if defined(CONFIG_POWER_SUPPLY_DIRECT_SMPS)
81 LL_PWR_ConfigSupply(LL_PWR_DIRECT_SMPS_SUPPLY);
82 #elif defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_LDO)
83 LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_LDO);
84 #elif defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_LDO)
85 LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_LDO);
86 #elif defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT_AND_LDO)
87 LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO);
88 #elif defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT_AND_LDO)
89 LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO);
90 #elif defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT)
91 LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_EXT);
92 #elif defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT)
93 LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_EXT);
94 #elif defined(CONFIG_POWER_SUPPLY_EXTERNAL_SOURCE)
95 LL_PWR_ConfigSupply(LL_PWR_EXTERNAL_SOURCE_SUPPLY);
96 #else
97 LL_PWR_ConfigSupply(LL_PWR_LDO_SUPPLY);
98 #endif
99 LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
100 while (LL_PWR_IsActiveFlag_VOS() == 0) {
101 }
102
103 /* Errata ES0392 Rev 8:
104 * 2.2.9: Reading from AXI SRAM may lead to data read corruption
105 * Workaround: Set the READ_ISS_OVERRIDE bit in the AXI_TARG7_FN_MOD
106 * register.
107 * Applicable only to RevY (REV_ID 0x1003)
108 */
109 if (LL_DBGMCU_GetRevisionID() == 0x1003) {
110 MODIFY_REG(GPV->AXI_TARG7_FN_MOD, 0x1, 0x1);
111 }
112
113 return 0;
114 }
115
116 SYS_INIT(stm32h7_init, PRE_KERNEL_1, 0);
117
118
119 #if defined(CONFIG_STM32H7_DUAL_CORE)
120 /* Unlock M4 once system configuration has been done */
121 SYS_INIT(stm32h7_m4_wakeup, POST_KERNEL, CONFIG_APPLICATION_INIT_PRIORITY);
122 #endif /* CONFIG_STM32H7_DUAL_CORE */
123
