/* * Copyright (c) 2019 Linaro Limited * * SPDX-License-Identifier: Apache-2.0 */ /** * @file * @brief System/hardware module for STM32H7 CM7 processor */ #include #include #include #include #include #include #include #include #include "stm32_hsem.h" #include #if defined(CONFIG_STM32H7_DUAL_CORE) static int stm32h7_m4_wakeup(void) { /* HW semaphore and SysCfg Clock enable */ LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_HSEM); LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_SYSCFG); if (READ_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4)) { /* Cortex-M4 is waiting for end of system initialization made by * Cortex-M7. This initialization is now finished, * then Cortex-M7 takes HSEM so that CM4 can continue running. */ LL_HSEM_1StepLock(HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID); } else if (IS_ENABLED(CONFIG_STM32H7_BOOT_M4_AT_INIT)) { /* CM4 is not started at boot, start it now */ LL_RCC_ForceCM4Boot(); } return 0; } #endif /* CONFIG_STM32H7_DUAL_CORE */ /** * @brief Perform basic hardware initialization at boot. * * This needs to be run from the very beginning. * So the init priority has to be 0 (zero). * * @return 0 */ static int stm32h7_init(void) { SCB_EnableICache(); if (IS_ENABLED(CONFIG_DCACHE)) { if (!(SCB->CCR & SCB_CCR_DC_Msk)) { SCB_EnableDCache(); } } /* Update CMSIS SystemCoreClock variable (HCLK) */ /* At reset, system core clock is set to 64 MHz from HSI */ SystemCoreClock = 64000000; /* Power Configuration */ #if !defined(SMPS) && \ (defined(CONFIG_POWER_SUPPLY_DIRECT_SMPS) || \ defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_LDO) || \ defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_LDO) || \ defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT_AND_LDO) || \ defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT_AND_LDO) || \ defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT) || \ defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT)) #error Unsupported configuration: Selected SoC do not support SMPS #endif #if defined(CONFIG_POWER_SUPPLY_DIRECT_SMPS) LL_PWR_ConfigSupply(LL_PWR_DIRECT_SMPS_SUPPLY); #elif defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_LDO) LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_LDO); #elif defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_LDO) LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_LDO); #elif defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT_AND_LDO) LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO); #elif defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT_AND_LDO) LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO); #elif defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT) LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_EXT); #elif defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT) LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_EXT); #elif defined(CONFIG_POWER_SUPPLY_EXTERNAL_SOURCE) LL_PWR_ConfigSupply(LL_PWR_EXTERNAL_SOURCE_SUPPLY); #else LL_PWR_ConfigSupply(LL_PWR_LDO_SUPPLY); #endif LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1); while (LL_PWR_IsActiveFlag_VOS() == 0) { } /* Errata ES0392 Rev 8: * 2.2.9: Reading from AXI SRAM may lead to data read corruption * Workaround: Set the READ_ISS_OVERRIDE bit in the AXI_TARG7_FN_MOD * register. * Applicable only to RevY (REV_ID 0x1003) */ if (LL_DBGMCU_GetRevisionID() == 0x1003) { MODIFY_REG(GPV->AXI_TARG7_FN_MOD, 0x1, 0x1); } return 0; } SYS_INIT(stm32h7_init, PRE_KERNEL_1, 0); #if defined(CONFIG_STM32H7_DUAL_CORE) /* Unlock M4 once system configuration has been done */ SYS_INIT(stm32h7_m4_wakeup, POST_KERNEL, CONFIG_APPLICATION_INIT_PRIORITY); #endif /* CONFIG_STM32H7_DUAL_CORE */