1 /* 2 * Copyright 2022-2023 NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_SOC_ARM_NXP_S32_COMMON_PINCTRL_SOC_H_ 8 #define ZEPHYR_SOC_ARM_NXP_S32_COMMON_PINCTRL_SOC_H_ 9 10 #include <zephyr/devicetree.h> 11 #include <zephyr/dt-bindings/pinctrl/nxp-s32-pinctrl.h> 12 #include <zephyr/sys/util_macro.h> 13 #include <zephyr/types.h> 14 15 #include <Siul2_Port_Ip.h> 16 17 /** @cond INTERNAL_HIDDEN */ 18 19 /** @brief Type for NXP S32 pin configuration. */ 20 typedef Siul2_Port_Ip_PinSettingsConfig pinctrl_soc_pin_t; 21 22 #if defined(SIUL2_PORT_IP_MULTIPLE_SIUL2_INSTANCES) 23 #define NXP_S32_SIUL2_IDX(n) \ 24 n == 0 ? IP_SIUL2_0 : (n == 1 ? IP_SIUL2_1 : ( \ 25 n == 3 ? IP_SIUL2_3 : (n == 4 ? IP_SIUL2_4 : ( \ 26 n == 5 ? IP_SIUL2_5 : (NULL))))) 27 #else 28 #define NXP_S32_SIUL2_IDX(n) (n == 0 ? IP_SIUL2 : NULL) 29 #endif 30 31 #define NXP_S32_INPUT_BUFFER(group) \ 32 COND_CODE_1(DT_PROP(group, input_enable), (PORT_INPUT_BUFFER_ENABLED), \ 33 (PORT_INPUT_BUFFER_DISABLED)) 34 35 #define NXP_S32_OUTPUT_BUFFER(group) \ 36 COND_CODE_1(DT_PROP(group, output_enable), (PORT_OUTPUT_BUFFER_ENABLED), \ 37 (PORT_OUTPUT_BUFFER_DISABLED)) 38 39 #define NXP_S32_INPUT_MUX_REG(group, val) \ 40 COND_CODE_1(DT_PROP(group, input_enable), (NXP_S32_PINMUX_GET_IMCR_IDX(val)), \ 41 (0U)) 42 43 #define NXP_S32_INPUT_MUX(group, val) \ 44 COND_CODE_1(DT_PROP(group, input_enable), \ 45 ((Siul2_Port_Ip_PortInputMux)NXP_S32_PINMUX_GET_IMCR_SSS(val)), \ 46 (PORT_INPUT_MUX_NO_INIT)) 47 48 #define NXP_S32_PULL_SEL(group) \ 49 COND_CODE_1(DT_PROP(group, bias_pull_up), (PORT_INTERNAL_PULL_UP_ENABLED), \ 50 (COND_CODE_1(DT_PROP(group, bias_pull_down), \ 51 (PORT_INTERNAL_PULL_DOWN_ENABLED), (PORT_INTERNAL_PULL_NOT_ENABLED)))) 52 53 #if defined(SIUL2_PORT_IP_HAS_ONEBIT_SLEWRATE) 54 #define NXP_S32_SLEW_RATE(group) \ 55 COND_CODE_1(DT_NODE_HAS_PROP(group, slew_rate), \ 56 (UTIL_CAT(PORT_SLEW_RATE_, DT_STRING_UPPER_TOKEN(group, slew_rate))), \ 57 (PORT_SLEW_RATE_FASTEST)) 58 #else 59 #define NXP_S32_SLEW_RATE(group) \ 60 COND_CODE_1(DT_NODE_HAS_PROP(group, slew_rate), \ 61 (UTIL_CAT(PORT_SLEW_RATE_CONTROL, DT_PROP(group, slew_rate))), \ 62 (PORT_SLEW_RATE_CONTROL0)) 63 #endif 64 65 #define NXP_S32_DRIVE_STRENGTH(group) \ 66 COND_CODE_1(DT_PROP(group, nxp_drive_strength), \ 67 (PORT_DRIVE_STRENTGTH_ENABLED), (PORT_DRIVE_STRENTGTH_DISABLED)) 68 69 #define NXP_S32_INVERT(group) \ 70 COND_CODE_1(DT_PROP(group, nxp_invert), \ 71 (PORT_INVERT_ENABLED), (PORT_INVERT_DISABLED)) 72 73 /* To enable open drain both OBE and ODE bits need to be set */ 74 #define NXP_S32_OPEN_DRAIN(group) \ 75 (DT_PROP(group, drive_open_drain) && DT_PROP(group, output_enable) ? \ 76 (PORT_OPEN_DRAIN_ENABLED) : (PORT_OPEN_DRAIN_DISABLED)) 77 78 /* Only a single input mux is configured, the rest is not used */ 79 #define NXP_S32_INPUT_MUX_NO_INIT \ 80 [1 ... (FEATURE_SIUL2_MAX_NUMBER_OF_INPUT-1)] = PORT_INPUT_MUX_NO_INIT 81 82 #define NXP_S32_PINMUX_INIT(group, val) \ 83 .base = NXP_S32_SIUL2_IDX(NXP_S32_PINMUX_GET_SIUL2_IDX(val)), \ 84 .pinPortIdx = NXP_S32_PINMUX_GET_MSCR_IDX(val), \ 85 .mux = (Siul2_Port_Ip_PortMux)NXP_S32_PINMUX_GET_MSCR_SSS(val), \ 86 .inputMux = { \ 87 NXP_S32_INPUT_MUX(group, val), \ 88 NXP_S32_INPUT_MUX_NO_INIT \ 89 }, \ 90 .inputMuxReg = { \ 91 NXP_S32_INPUT_MUX_REG(group, val) \ 92 }, \ 93 .inputBuffer = NXP_S32_INPUT_BUFFER(group), \ 94 .outputBuffer = NXP_S32_OUTPUT_BUFFER(group), \ 95 .pullConfig = NXP_S32_PULL_SEL(group), \ 96 .safeMode = PORT_SAFE_MODE_DISABLED, \ 97 .slewRateCtrlSel = NXP_S32_SLEW_RATE(group), \ 98 .initValue = PORT_PIN_LEVEL_NOTCHANGED_U8, \ 99 IF_ENABLED(__DEBRACKET FEATURE_SIUL2_PORT_IP_HAS_DRIVE_STRENGTH, \ 100 (.driveStrength = NXP_S32_DRIVE_STRENGTH(group),)) \ 101 IF_ENABLED(__DEBRACKET FEATURE_SIUL2_PORT_IP_HAS_INVERT_DATA, \ 102 (.invert = NXP_S32_INVERT(group),)) \ 103 IF_ENABLED(__DEBRACKET FEATURE_SIUL2_PORT_IP_HAS_OPEN_DRAIN, \ 104 (.openDrain = NXP_S32_OPEN_DRAIN(group),)) \ 105 IF_ENABLED(__DEBRACKET FEATURE_SIUL2_PORT_IP_HAS_INPUT_FILTER, \ 106 (.inputFilter = PORT_INPUT_FILTER_DISABLED,)) \ 107 IF_ENABLED(__DEBRACKET FEATURE_SIUL2_PORT_IP_HAS_RECEIVER_SELECT, \ 108 (.receiverSel = PORT_RECEIVER_ENABLE_SINGLE_ENDED,)) \ 109 IF_ENABLED(__DEBRACKET FEATURE_SIUL2_PORT_IP_HAS_HYSTERESIS, \ 110 (.hysteresis = PORT_HYSTERESIS_DISABLED,)) \ 111 IF_ENABLED(__DEBRACKET FEATURE_SIUL2_PORT_IP_HAS_ANALOG_PAD_CONTROL, \ 112 (.analogPadControl = PORT_ANALOG_PAD_CONTROL_DISABLED,)) \ 113 IF_ENABLED(__DEBRACKET FEATURE_SIUL2_PORT_IP_HAS_TERMINATION_RESISTOR, \ 114 (.terminationResistor = PORT_TERMINATION_RESISTOR_DISABLED,)) \ 115 IF_ENABLED(__DEBRACKET FEATURE_SIUL2_PORT_IP_HAS_CURRENT_REFERENCE_CONTROL, \ 116 (.currentReferenceControl = PORT_CURRENT_REFERENCE_CONTROL_DISABLED,)) \ 117 IF_ENABLED(__DEBRACKET FEATURE_SIUL2_PORT_IP_HAS_RX_CURRENT_BOOST, \ 118 (.rxCurrentBoost = PORT_RX_CURRENT_BOOST_DISABLED,)) \ 119 IF_ENABLED(__DEBRACKET FEATURE_SIUL2_PORT_IP_HAS_PULL_KEEPER, \ 120 (.pullKeep = PORT_PULL_KEEP_DISABLED,)) 121 122 /** 123 * @brief Utility macro to initialize each pin. 124 * 125 * 126 * @param group Group node identifier. 127 * @param prop Property name. 128 * @param idx Property entry index. 129 */ 130 #define Z_PINCTRL_STATE_PIN_INIT(group, prop, idx) \ 131 { \ 132 NXP_S32_PINMUX_INIT(group, DT_PROP_BY_IDX(group, prop, idx)) \ 133 }, 134 135 /** 136 * @brief Utility macro to initialize state pins contained in a given property. 137 * 138 * @param node_id Node identifier. 139 * @param prop Property name describing state pins. 140 */ 141 #define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ 142 {DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \ 143 DT_FOREACH_PROP_ELEM, pinmux, \ 144 Z_PINCTRL_STATE_PIN_INIT)} 145 146 /** @endcond */ 147 148 #endif /* ZEPHYR_SOC_ARM_NXP_S32_COMMON_PINCTRL_SOC_H_ */ 149
