1 /*
2 * Copyright (c) 2017, I-SENSE group of ICCS
3 * Copyright (c) 2017 Linaro Ltd
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 *
7 * I2C Driver for: STM32F1, STM32F2, STM32F4 and STM32L1
8 *
9 */
10
11 #include <drivers/clock_control/stm32_clock_control.h>
12 #include <drivers/clock_control.h>
13 #include <sys/util.h>
14 #include <kernel.h>
15 #include <soc.h>
16 #include <stm32_ll_i2c.h>
17 #include <errno.h>
18 #include <drivers/i2c.h>
19 #include "i2c_ll_stm32.h"
20
21 #define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
22 #include <logging/log.h>
23 LOG_MODULE_REGISTER(i2c_ll_stm32_v1);
24
25 #include "i2c-priv.h"
26
27 #define STM32_I2C_TRANSFER_TIMEOUT_MSEC 500
28
29 #define STM32_I2C_TIMEOUT_USEC 1000
30 #define I2C_REQUEST_WRITE 0x00
31 #define I2C_REQUEST_READ 0x01
32 #define HEADER 0xF0
33
stm32_i2c_generate_start_condition(I2C_TypeDef * i2c)34 static void stm32_i2c_generate_start_condition(I2C_TypeDef *i2c)
35 {
36 uint16_t cr1 = LL_I2C_ReadReg(i2c, CR1);
37
38 if (cr1 & I2C_CR1_STOP) {
39 LOG_DBG("%s: START while STOP active!", __func__);
40 LL_I2C_WriteReg(i2c, CR1, cr1 & ~I2C_CR1_STOP);
41 }
42
43 LL_I2C_GenerateStartCondition(i2c);
44 }
45
46 #ifdef CONFIG_I2C_STM32_INTERRUPT
47
stm32_i2c_disable_transfer_interrupts(const struct device * dev)48 static void stm32_i2c_disable_transfer_interrupts(const struct device *dev)
49 {
50 const struct i2c_stm32_config *cfg = DEV_CFG(dev);
51 I2C_TypeDef *i2c = cfg->i2c;
52
53 LL_I2C_DisableIT_TX(i2c);
54 LL_I2C_DisableIT_RX(i2c);
55 LL_I2C_DisableIT_EVT(i2c);
56 LL_I2C_DisableIT_BUF(i2c);
57 LL_I2C_DisableIT_ERR(i2c);
58 }
59
stm32_i2c_enable_transfer_interrupts(const struct device * dev)60 static void stm32_i2c_enable_transfer_interrupts(const struct device *dev)
61 {
62 const struct i2c_stm32_config *cfg = DEV_CFG(dev);
63 I2C_TypeDef *i2c = cfg->i2c;
64
65 LL_I2C_EnableIT_ERR(i2c);
66 LL_I2C_EnableIT_EVT(i2c);
67 LL_I2C_EnableIT_BUF(i2c);
68 }
69
70 #endif /* CONFIG_I2C_STM32_INTERRUPT */
71
stm32_i2c_reset(const struct device * dev)72 static void stm32_i2c_reset(const struct device *dev)
73 {
74 const struct i2c_stm32_config *cfg = DEV_CFG(dev);
75 I2C_TypeDef *i2c = cfg->i2c;
76 uint16_t cr1, cr2, oar1, oar2, trise, ccr;
77 #if defined(I2C_FLTR_ANOFF) && defined(I2C_FLTR_DNF)
78 uint16_t fltr;
79 #endif
80
81 /* disable i2c and disable IRQ's */
82 LL_I2C_Disable(i2c);
83 #ifdef CONFIG_I2C_STM32_INTERRUPT
84 stm32_i2c_disable_transfer_interrupts(dev);
85 #endif
86
87 /* save all important registers before reset */
88 cr1 = LL_I2C_ReadReg(i2c, CR1);
89 cr2 = LL_I2C_ReadReg(i2c, CR2);
90 oar1 = LL_I2C_ReadReg(i2c, OAR1);
91 oar2 = LL_I2C_ReadReg(i2c, OAR2);
92 ccr = LL_I2C_ReadReg(i2c, CCR);
93 trise = LL_I2C_ReadReg(i2c, TRISE);
94 #if defined(I2C_FLTR_ANOFF) && defined(I2C_FLTR_DNF)
95 fltr = LL_I2C_ReadReg(i2c, FLTR);
96 #endif
97
98 /* reset i2c hardware */
99 LL_I2C_EnableReset(i2c);
100 LL_I2C_DisableReset(i2c);
101
102 /* restore all important registers after reset */
103 LL_I2C_WriteReg(i2c, CR1, cr1);
104 LL_I2C_WriteReg(i2c, CR2, cr2);
105
106 /* bit 14 of OAR1 must always be 1 */
107 oar1 |= (1 << 14);
108 LL_I2C_WriteReg(i2c, OAR1, oar1);
109 LL_I2C_WriteReg(i2c, OAR2, oar2);
110 LL_I2C_WriteReg(i2c, CCR, ccr);
111 LL_I2C_WriteReg(i2c, TRISE, trise);
112 #if defined(I2C_FLTR_ANOFF) && defined(I2C_FLTR_DNF)
113 LL_I2C_WriteReg(i2c, FLTR, fltr);
114 #endif
115 }
116
117
stm32_i2c_master_finish(const struct device * dev)118 static void stm32_i2c_master_finish(const struct device *dev)
119 {
120 const struct i2c_stm32_config *cfg = DEV_CFG(dev);
121 I2C_TypeDef *i2c = cfg->i2c;
122
123 #ifdef CONFIG_I2C_STM32_INTERRUPT
124 stm32_i2c_disable_transfer_interrupts(dev);
125 #endif
126
127 #if defined(CONFIG_I2C_SLAVE)
128 struct i2c_stm32_data *data = DEV_DATA(dev);
129 data->master_active = false;
130 if (!data->slave_attached) {
131 LL_I2C_Disable(i2c);
132 } else {
133 stm32_i2c_enable_transfer_interrupts(dev);
134 LL_I2C_AcknowledgeNextData(i2c, LL_I2C_ACK);
135 }
136 #else
137 LL_I2C_Disable(i2c);
138 #endif
139 }
140
msg_init(const struct device * dev,struct i2c_msg * msg,uint8_t * next_msg_flags,uint16_t slave,uint32_t transfer)141 static inline void msg_init(const struct device *dev, struct i2c_msg *msg,
142 uint8_t *next_msg_flags, uint16_t slave,
143 uint32_t transfer)
144 {
145 const struct i2c_stm32_config *cfg = DEV_CFG(dev);
146 struct i2c_stm32_data *data = DEV_DATA(dev);
147 I2C_TypeDef *i2c = cfg->i2c;
148
149 ARG_UNUSED(next_msg_flags);
150
151 #ifdef CONFIG_I2C_STM32_INTERRUPT
152 k_sem_reset(&data->device_sync_sem);
153 #endif
154
155 data->current.len = msg->len;
156 data->current.buf = msg->buf;
157 data->current.flags = msg->flags;
158 data->current.is_restart = 0U;
159 data->current.is_write = (transfer == I2C_REQUEST_WRITE);
160 data->current.is_arlo = 0U;
161 data->current.is_err = 0U;
162 data->current.is_nack = 0U;
163 data->current.msg = msg;
164 #if defined(CONFIG_I2C_SLAVE)
165 data->master_active = true;
166 #endif
167 data->slave_address = slave;
168
169 LL_I2C_Enable(i2c);
170
171 LL_I2C_DisableBitPOS(i2c);
172 LL_I2C_AcknowledgeNextData(i2c, LL_I2C_ACK);
173 if (msg->flags & I2C_MSG_RESTART) {
174 stm32_i2c_generate_start_condition(i2c);
175 }
176 }
177
msg_end(const struct device * dev,uint8_t * next_msg_flags,const char * funcname)178 static int32_t msg_end(const struct device *dev, uint8_t *next_msg_flags,
179 const char *funcname)
180 {
181 struct i2c_stm32_data *data = DEV_DATA(dev);
182
183 if (data->current.is_nack || data->current.is_err ||
184 data->current.is_arlo) {
185 goto error;
186 }
187
188 if (!next_msg_flags) {
189 stm32_i2c_master_finish(dev);
190 }
191
192 return 0;
193
194 error:
195 if (data->current.is_arlo) {
196 LOG_DBG("%s: ARLO %d", funcname,
197 data->current.is_arlo);
198 data->current.is_arlo = 0U;
199 }
200
201 if (data->current.is_nack) {
202 LOG_DBG("%s: NACK", funcname);
203 data->current.is_nack = 0U;
204 }
205
206 if (data->current.is_err) {
207 LOG_DBG("%s: ERR %d", funcname,
208 data->current.is_err);
209 data->current.is_err = 0U;
210 }
211 stm32_i2c_master_finish(dev);
212
213 return -EIO;
214 }
215
216 #ifdef CONFIG_I2C_STM32_INTERRUPT
217
stm32_i2c_master_mode_end(const struct device * dev)218 static void stm32_i2c_master_mode_end(const struct device *dev)
219 {
220 struct i2c_stm32_data *data = DEV_DATA(dev);
221
222 k_sem_give(&data->device_sync_sem);
223 }
224
handle_sb(const struct device * dev)225 static inline void handle_sb(const struct device *dev)
226 {
227 const struct i2c_stm32_config *cfg = DEV_CFG(dev);
228 struct i2c_stm32_data *data = DEV_DATA(dev);
229 I2C_TypeDef *i2c = cfg->i2c;
230
231 uint16_t saddr = data->slave_address;
232 uint8_t slave;
233
234 if (I2C_ADDR_10_BITS & data->dev_config) {
235 slave = (((saddr & 0x0300) >> 7) & 0xFF);
236 uint8_t header = slave | HEADER;
237
238 if (data->current.is_restart == 0U) {
239 data->current.is_restart = 1U;
240 } else {
241 header |= I2C_REQUEST_READ;
242 data->current.is_restart = 0U;
243 }
244 LL_I2C_TransmitData8(i2c, header);
245
246 return;
247 }
248 slave = (saddr << 1) & 0xFF;
249 if (data->current.is_write) {
250 LL_I2C_TransmitData8(i2c, slave | I2C_REQUEST_WRITE);
251 } else {
252 LL_I2C_TransmitData8(i2c, slave | I2C_REQUEST_READ);
253 if (data->current.len == 2) {
254 LL_I2C_EnableBitPOS(i2c);
255 }
256 }
257 }
258
handle_addr(const struct device * dev)259 static inline void handle_addr(const struct device *dev)
260 {
261 const struct i2c_stm32_config *cfg = DEV_CFG(dev);
262 struct i2c_stm32_data *data = DEV_DATA(dev);
263 I2C_TypeDef *i2c = cfg->i2c;
264
265 if (I2C_ADDR_10_BITS & data->dev_config) {
266 if (!data->current.is_write && data->current.is_restart) {
267 data->current.is_restart = 0U;
268 LL_I2C_ClearFlag_ADDR(i2c);
269 stm32_i2c_generate_start_condition(i2c);
270
271 return;
272 }
273 }
274
275 if (data->current.is_write) {
276 LL_I2C_ClearFlag_ADDR(i2c);
277 return;
278 }
279 /* according to STM32F1 errata we need to handle these corner cases in
280 * specific way.
281 * Please ref to STM32F10xxC/D/E I2C peripheral Errata sheet 2.14.1
282 */
283 if (data->current.len == 0U && IS_ENABLED(CONFIG_SOC_SERIES_STM32F1X)) {
284 LL_I2C_GenerateStopCondition(i2c);
285 } else if (data->current.len == 1U) {
286 /* Single byte reception: enable NACK and clear POS */
287 LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
288 #ifdef CONFIG_SOC_SERIES_STM32F1X
289 LL_I2C_ClearFlag_ADDR(i2c);
290 LL_I2C_GenerateStopCondition(i2c);
291 #endif
292 } else if (data->current.len == 2U) {
293 #ifdef CONFIG_SOC_SERIES_STM32F1X
294 LL_I2C_ClearFlag_ADDR(i2c);
295 #endif
296 /* 2-byte reception: enable NACK and set POS */
297 LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
298 LL_I2C_EnableBitPOS(i2c);
299 }
300 LL_I2C_ClearFlag_ADDR(i2c);
301 }
302
handle_txe(const struct device * dev)303 static inline void handle_txe(const struct device *dev)
304 {
305 const struct i2c_stm32_config *cfg = DEV_CFG(dev);
306 struct i2c_stm32_data *data = DEV_DATA(dev);
307 I2C_TypeDef *i2c = cfg->i2c;
308
309 if (data->current.len) {
310 data->current.len--;
311 if (data->current.len == 0U) {
312 /*
313 * This is the last byte to transmit disable Buffer
314 * interrupt and wait for a BTF interrupt
315 */
316 LL_I2C_DisableIT_BUF(i2c);
317 }
318 LL_I2C_TransmitData8(i2c, *data->current.buf);
319 data->current.buf++;
320 } else {
321 if (data->current.flags & I2C_MSG_STOP) {
322 LL_I2C_GenerateStopCondition(i2c);
323 }
324 if (LL_I2C_IsActiveFlag_BTF(i2c)) {
325 /* Read DR to clear BTF flag */
326 LL_I2C_ReceiveData8(i2c);
327 }
328
329 k_sem_give(&data->device_sync_sem);
330 }
331 }
332
handle_rxne(const struct device * dev)333 static inline void handle_rxne(const struct device *dev)
334 {
335 const struct i2c_stm32_config *cfg = DEV_CFG(dev);
336 struct i2c_stm32_data *data = DEV_DATA(dev);
337 I2C_TypeDef *i2c = cfg->i2c;
338
339 if (data->current.len > 0) {
340 switch (data->current.len) {
341 case 1:
342 LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
343 LL_I2C_DisableBitPOS(i2c);
344 /* Single byte reception */
345 if (data->current.flags & I2C_MSG_STOP) {
346 LL_I2C_GenerateStopCondition(i2c);
347 }
348 LL_I2C_DisableIT_BUF(i2c);
349 data->current.len--;
350 *data->current.buf = LL_I2C_ReceiveData8(i2c);
351 data->current.buf++;
352
353 k_sem_give(&data->device_sync_sem);
354 break;
355 case 2:
356 LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
357 LL_I2C_EnableBitPOS(i2c);
358 __fallthrough;
359 case 3:
360 /*
361 * 2-byte, 3-byte reception and for N-2, N-1,
362 * N when N > 3
363 */
364 LL_I2C_DisableIT_BUF(i2c);
365 break;
366 default:
367 /* N byte reception when N > 3 */
368 data->current.len--;
369 *data->current.buf = LL_I2C_ReceiveData8(i2c);
370 data->current.buf++;
371 }
372 } else {
373
374 if (data->current.flags & I2C_MSG_STOP) {
375 LL_I2C_GenerateStopCondition(i2c);
376 }
377 k_sem_give(&data->device_sync_sem);
378 }
379 }
380
handle_btf(const struct device * dev)381 static inline void handle_btf(const struct device *dev)
382 {
383 const struct i2c_stm32_config *cfg = DEV_CFG(dev);
384 struct i2c_stm32_data *data = DEV_DATA(dev);
385 I2C_TypeDef *i2c = cfg->i2c;
386
387 if (data->current.is_write) {
388 handle_txe(dev);
389 } else {
390 uint32_t counter = 0U;
391
392 switch (data->current.len) {
393 case 2:
394 /*
395 * Stop condition must be generated before reading the
396 * last two bytes.
397 */
398 if (data->current.flags & I2C_MSG_STOP) {
399 LL_I2C_GenerateStopCondition(i2c);
400 }
401
402 for (counter = 2U; counter > 0; counter--) {
403 data->current.len--;
404 *data->current.buf = LL_I2C_ReceiveData8(i2c);
405 data->current.buf++;
406 }
407 k_sem_give(&data->device_sync_sem);
408 break;
409 case 3:
410 /* Set NACK before reading N-2 byte*/
411 LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
412 data->current.len--;
413 *data->current.buf = LL_I2C_ReceiveData8(i2c);
414 data->current.buf++;
415 break;
416 default:
417 handle_rxne(dev);
418 }
419 }
420 }
421
422
423 #if defined(CONFIG_I2C_SLAVE)
stm32_i2c_slave_event(const struct device * dev)424 static void stm32_i2c_slave_event(const struct device *dev)
425 {
426 const struct i2c_stm32_config *cfg = DEV_CFG(dev);
427 struct i2c_stm32_data *data = DEV_DATA(dev);
428 I2C_TypeDef *i2c = cfg->i2c;
429 const struct i2c_slave_callbacks *slave_cb =
430 data->slave_cfg->callbacks;
431
432 if (LL_I2C_IsActiveFlag_TXE(i2c) && LL_I2C_IsActiveFlag_BTF(i2c)) {
433 uint8_t val;
434 slave_cb->read_processed(data->slave_cfg, &val);
435 LL_I2C_TransmitData8(i2c, val);
436 return;
437 }
438
439 if (LL_I2C_IsActiveFlag_RXNE(i2c)) {
440 uint8_t val = LL_I2C_ReceiveData8(i2c);
441 if (slave_cb->write_received(data->slave_cfg, val)) {
442 LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
443 }
444 return;
445 }
446
447 if (LL_I2C_IsActiveFlag_AF(i2c)) {
448 LL_I2C_ClearFlag_AF(i2c);
449 }
450
451 if (LL_I2C_IsActiveFlag_STOP(i2c)) {
452 LL_I2C_ClearFlag_STOP(i2c);
453 slave_cb->stop(data->slave_cfg);
454 /* Prepare to ACK next transmissions address byte */
455 LL_I2C_AcknowledgeNextData(i2c, LL_I2C_ACK);
456 }
457
458 if (LL_I2C_IsActiveFlag_ADDR(i2c)) {
459 uint32_t dir = LL_I2C_GetTransferDirection(i2c);
460 if (dir == LL_I2C_DIRECTION_READ) {
461 slave_cb->write_requested(data->slave_cfg);
462 LL_I2C_EnableIT_RX(i2c);
463 } else {
464 uint8_t val;
465 slave_cb->read_requested(data->slave_cfg, &val);
466 LL_I2C_TransmitData8(i2c, val);
467 LL_I2C_EnableIT_TX(i2c);
468 }
469
470 stm32_i2c_enable_transfer_interrupts(dev);
471 }
472 }
473
474 /* Attach and start I2C as slave */
i2c_stm32_slave_register(const struct device * dev,struct i2c_slave_config * config)475 int i2c_stm32_slave_register(const struct device *dev,
476 struct i2c_slave_config *config)
477 {
478 const struct i2c_stm32_config *cfg = DEV_CFG(dev);
479 struct i2c_stm32_data *data = DEV_DATA(dev);
480 I2C_TypeDef *i2c = cfg->i2c;
481 uint32_t bitrate_cfg;
482 int ret;
483
484 if (!config) {
485 return -EINVAL;
486 }
487
488 if (data->slave_attached) {
489 return -EBUSY;
490 }
491
492 if (data->master_active) {
493 return -EBUSY;
494 }
495
496 bitrate_cfg = i2c_map_dt_bitrate(cfg->bitrate);
497
498 ret = i2c_stm32_runtime_configure(dev, bitrate_cfg);
499 if (ret < 0) {
500 LOG_ERR("i2c: failure initializing");
501 return ret;
502 }
503
504 data->slave_cfg = config;
505
506 LL_I2C_Enable(i2c);
507
508 LL_I2C_SetOwnAddress1(i2c, config->address << 1,
509 LL_I2C_OWNADDRESS1_7BIT);
510
511 data->slave_attached = true;
512
513 LOG_DBG("i2c: slave registered");
514
515 stm32_i2c_enable_transfer_interrupts(dev);
516 LL_I2C_AcknowledgeNextData(i2c, LL_I2C_ACK);
517
518 return 0;
519 }
520
i2c_stm32_slave_unregister(const struct device * dev,struct i2c_slave_config * config)521 int i2c_stm32_slave_unregister(const struct device *dev,
522 struct i2c_slave_config *config)
523 {
524 const struct i2c_stm32_config *cfg = DEV_CFG(dev);
525 struct i2c_stm32_data *data = DEV_DATA(dev);
526 I2C_TypeDef *i2c = cfg->i2c;
527
528 if (!data->slave_attached) {
529 return -EINVAL;
530 }
531
532 if (data->master_active) {
533 return -EBUSY;
534 }
535
536 stm32_i2c_disable_transfer_interrupts(dev);
537
538 LL_I2C_ClearFlag_AF(i2c);
539 LL_I2C_ClearFlag_STOP(i2c);
540 LL_I2C_ClearFlag_ADDR(i2c);
541
542 LL_I2C_Disable(i2c);
543
544 data->slave_attached = false;
545
546 LOG_DBG("i2c: slave unregistered");
547
548 return 0;
549 }
550 #endif /* defined(CONFIG_I2C_SLAVE) */
551
stm32_i2c_event_isr(void * arg)552 void stm32_i2c_event_isr(void *arg)
553 {
554 const struct device *dev = (const struct device *)arg;
555 const struct i2c_stm32_config *cfg = DEV_CFG(dev);
556 struct i2c_stm32_data *data = DEV_DATA(dev);
557 I2C_TypeDef *i2c = cfg->i2c;
558
559 #if defined(CONFIG_I2C_SLAVE)
560 if (data->slave_attached && !data->master_active) {
561 stm32_i2c_slave_event(dev);
562 return;
563 }
564 #endif
565
566 if (LL_I2C_IsActiveFlag_SB(i2c)) {
567 handle_sb(dev);
568 } else if (LL_I2C_IsActiveFlag_ADD10(i2c)) {
569 LL_I2C_TransmitData8(i2c, data->slave_address);
570 } else if (LL_I2C_IsActiveFlag_ADDR(i2c)) {
571 handle_addr(dev);
572 } else if (LL_I2C_IsActiveFlag_BTF(i2c)) {
573 handle_btf(dev);
574 } else if (LL_I2C_IsActiveFlag_TXE(i2c) && data->current.is_write) {
575 handle_txe(dev);
576 } else if (LL_I2C_IsActiveFlag_RXNE(i2c) && !data->current.is_write) {
577 handle_rxne(dev);
578 }
579 }
580
stm32_i2c_error_isr(void * arg)581 void stm32_i2c_error_isr(void *arg)
582 {
583 const struct device *dev = (const struct device *)arg;
584 const struct i2c_stm32_config *cfg = DEV_CFG(dev);
585 struct i2c_stm32_data *data = DEV_DATA(dev);
586 I2C_TypeDef *i2c = cfg->i2c;
587
588 #if defined(CONFIG_I2C_SLAVE)
589 if (data->slave_attached && !data->master_active) {
590 /* No need for a slave error function right now. */
591 return;
592 }
593 #endif
594
595 if (LL_I2C_IsActiveFlag_AF(i2c)) {
596 LL_I2C_ClearFlag_AF(i2c);
597 LL_I2C_GenerateStopCondition(i2c);
598 data->current.is_nack = 1U;
599 goto end;
600 }
601 if (LL_I2C_IsActiveFlag_ARLO(i2c)) {
602 LL_I2C_ClearFlag_ARLO(i2c);
603 data->current.is_arlo = 1U;
604 goto end;
605 }
606
607 if (LL_I2C_IsActiveFlag_BERR(i2c)) {
608 LL_I2C_ClearFlag_BERR(i2c);
609 data->current.is_err = 1U;
610 goto end;
611 }
612 return;
613 end:
614 stm32_i2c_master_mode_end(dev);
615 }
616
stm32_i2c_msg_write(const struct device * dev,struct i2c_msg * msg,uint8_t * next_msg_flags,uint16_t saddr)617 int32_t stm32_i2c_msg_write(const struct device *dev, struct i2c_msg *msg,
618 uint8_t *next_msg_flags, uint16_t saddr)
619 {
620 struct i2c_stm32_data *data = DEV_DATA(dev);
621
622 msg_init(dev, msg, next_msg_flags, saddr, I2C_REQUEST_WRITE);
623
624 stm32_i2c_enable_transfer_interrupts(dev);
625
626 if (k_sem_take(&data->device_sync_sem,
627 K_MSEC(STM32_I2C_TRANSFER_TIMEOUT_MSEC)) != 0) {
628 LOG_DBG("%s: WRITE timeout", __func__);
629 stm32_i2c_reset(dev);
630 return -EIO;
631 }
632
633 return msg_end(dev, next_msg_flags, __func__);
634 }
635
stm32_i2c_msg_read(const struct device * dev,struct i2c_msg * msg,uint8_t * next_msg_flags,uint16_t saddr)636 int32_t stm32_i2c_msg_read(const struct device *dev, struct i2c_msg *msg,
637 uint8_t *next_msg_flags, uint16_t saddr)
638 {
639 const struct i2c_stm32_config *cfg = DEV_CFG(dev);
640 struct i2c_stm32_data *data = DEV_DATA(dev);
641 I2C_TypeDef *i2c = cfg->i2c;
642
643 msg_init(dev, msg, next_msg_flags, saddr, I2C_REQUEST_READ);
644
645 stm32_i2c_enable_transfer_interrupts(dev);
646 LL_I2C_EnableIT_RX(i2c);
647
648 if (k_sem_take(&data->device_sync_sem,
649 K_MSEC(STM32_I2C_TRANSFER_TIMEOUT_MSEC)) != 0) {
650 LOG_DBG("%s: READ timeout", __func__);
651 stm32_i2c_reset(dev);
652 return -EIO;
653 }
654
655 return msg_end(dev, next_msg_flags, __func__);
656 }
657
658 #else /* CONFIG_I2C_STM32_INTERRUPT */
659
check_errors(const struct device * dev,const char * funcname)660 static inline int check_errors(const struct device *dev, const char *funcname)
661 {
662 const struct i2c_stm32_config *cfg = DEV_CFG(dev);
663 struct i2c_stm32_data *data = DEV_DATA(dev);
664 I2C_TypeDef *i2c = cfg->i2c;
665
666 if (LL_I2C_IsActiveFlag_AF(i2c)) {
667 LL_I2C_ClearFlag_AF(i2c);
668 LOG_DBG("%s: NACK", funcname);
669 data->current.is_nack = 1U;
670 goto error;
671 }
672
673 if (LL_I2C_IsActiveFlag_ARLO(i2c)) {
674 LL_I2C_ClearFlag_ARLO(i2c);
675 LOG_DBG("%s: ARLO", funcname);
676 data->current.is_arlo = 1U;
677 goto error;
678 }
679
680 if (LL_I2C_IsActiveFlag_OVR(i2c)) {
681 LL_I2C_ClearFlag_OVR(i2c);
682 LOG_DBG("%s: OVR", funcname);
683 data->current.is_err = 1U;
684 goto error;
685 }
686
687 if (LL_I2C_IsActiveFlag_BERR(i2c)) {
688 LL_I2C_ClearFlag_BERR(i2c);
689 LOG_DBG("%s: BERR", funcname);
690 data->current.is_err = 1U;
691 goto error;
692 }
693
694 return 0;
695 error:
696 return -EIO;
697 }
698
stm32_i2c_wait_timeout(uint16_t * timeout)699 static int stm32_i2c_wait_timeout(uint16_t *timeout)
700 {
701 if (*timeout == 0) {
702 return 1;
703 } else {
704 k_busy_wait(1);
705 (*timeout)--;
706 return 0;
707 }
708 }
709
stm32_i2c_msg_write(const struct device * dev,struct i2c_msg * msg,uint8_t * next_msg_flags,uint16_t saddr)710 int32_t stm32_i2c_msg_write(const struct device *dev, struct i2c_msg *msg,
711 uint8_t *next_msg_flags, uint16_t saddr)
712 {
713 const struct i2c_stm32_config *cfg = DEV_CFG(dev);
714 struct i2c_stm32_data *data = DEV_DATA(dev);
715 I2C_TypeDef *i2c = cfg->i2c;
716 uint32_t len = msg->len;
717 uint16_t timeout;
718 uint8_t *buf = msg->buf;
719 int32_t res;
720
721 msg_init(dev, msg, next_msg_flags, saddr, I2C_REQUEST_WRITE);
722
723 if (msg->flags & I2C_MSG_RESTART) {
724 timeout = STM32_I2C_TIMEOUT_USEC;
725 while (!LL_I2C_IsActiveFlag_SB(i2c)) {
726 if (stm32_i2c_wait_timeout(&timeout)) {
727 LL_I2C_GenerateStopCondition(i2c);
728 data->current.is_err = 1U;
729 goto end;
730 }
731 }
732
733 if (I2C_ADDR_10_BITS & data->dev_config) {
734 uint8_t slave = (((saddr & 0x0300) >> 7) & 0xFF);
735 uint8_t header = slave | HEADER;
736
737 LL_I2C_TransmitData8(i2c, header);
738 timeout = STM32_I2C_TIMEOUT_USEC;
739 while (!LL_I2C_IsActiveFlag_ADD10(i2c)) {
740 if (stm32_i2c_wait_timeout(&timeout)) {
741 LL_I2C_GenerateStopCondition(i2c);
742 data->current.is_err = 1U;
743 goto end;
744 }
745 }
746
747 slave = data->slave_address & 0xFF;
748 LL_I2C_TransmitData8(i2c, slave);
749 } else {
750 uint8_t slave = (saddr << 1) & 0xFF;
751
752 LL_I2C_TransmitData8(i2c, slave | I2C_REQUEST_WRITE);
753 }
754
755 timeout = STM32_I2C_TIMEOUT_USEC;
756 while (!LL_I2C_IsActiveFlag_ADDR(i2c)) {
757 if (LL_I2C_IsActiveFlag_AF(i2c) || stm32_i2c_wait_timeout(&timeout)) {
758 LL_I2C_ClearFlag_AF(i2c);
759 LL_I2C_GenerateStopCondition(i2c);
760 data->current.is_nack = 1U;
761 goto end;
762 }
763 }
764 LL_I2C_ClearFlag_ADDR(i2c);
765 }
766
767 while (len) {
768 timeout = STM32_I2C_TIMEOUT_USEC;
769 while (1) {
770 if (LL_I2C_IsActiveFlag_TXE(i2c)) {
771 break;
772 }
773 if (LL_I2C_IsActiveFlag_AF(i2c) || stm32_i2c_wait_timeout(&timeout)) {
774 LL_I2C_ClearFlag_AF(i2c);
775 LL_I2C_GenerateStopCondition(i2c);
776 data->current.is_nack = 1U;
777 goto end;
778 }
779 }
780 LL_I2C_TransmitData8(i2c, *buf);
781 buf++;
782 len--;
783 }
784
785 timeout = STM32_I2C_TIMEOUT_USEC;
786 while (!LL_I2C_IsActiveFlag_BTF(i2c)) {
787 if (stm32_i2c_wait_timeout(&timeout)) {
788 LL_I2C_GenerateStopCondition(i2c);
789 data->current.is_err = 1U;
790 goto end;
791 }
792 }
793
794 if (msg->flags & I2C_MSG_STOP) {
795 LL_I2C_GenerateStopCondition(i2c);
796 }
797
798 end:
799 check_errors(dev, __func__);
800 res = msg_end(dev, next_msg_flags, __func__);
801 if (res < 0) {
802 stm32_i2c_reset(dev);
803 }
804
805 return res;
806 }
807
stm32_i2c_msg_read(const struct device * dev,struct i2c_msg * msg,uint8_t * next_msg_flags,uint16_t saddr)808 int32_t stm32_i2c_msg_read(const struct device *dev, struct i2c_msg *msg,
809 uint8_t *next_msg_flags, uint16_t saddr)
810 {
811 const struct i2c_stm32_config *cfg = DEV_CFG(dev);
812 struct i2c_stm32_data *data = DEV_DATA(dev);
813 I2C_TypeDef *i2c = cfg->i2c;
814 uint32_t len = msg->len;
815 uint16_t timeout;
816 uint8_t *buf = msg->buf;
817 int32_t res;
818
819 msg_init(dev, msg, next_msg_flags, saddr, I2C_REQUEST_READ);
820
821 if (msg->flags & I2C_MSG_RESTART) {
822 timeout = STM32_I2C_TIMEOUT_USEC;
823 while (!LL_I2C_IsActiveFlag_SB(i2c)) {
824 if (stm32_i2c_wait_timeout(&timeout)) {
825 LL_I2C_GenerateStopCondition(i2c);
826 data->current.is_err = 1U;
827 goto end;
828 }
829 }
830
831 if (I2C_ADDR_10_BITS & data->dev_config) {
832 uint8_t slave = (((saddr & 0x0300) >> 7) & 0xFF);
833 uint8_t header = slave | HEADER;
834
835 LL_I2C_TransmitData8(i2c, header);
836 timeout = STM32_I2C_TIMEOUT_USEC;
837 while (!LL_I2C_IsActiveFlag_ADD10(i2c)) {
838 if (stm32_i2c_wait_timeout(&timeout)) {
839 LL_I2C_GenerateStopCondition(i2c);
840 data->current.is_err = 1U;
841 goto end;
842 }
843 }
844
845 slave = saddr & 0xFF;
846 LL_I2C_TransmitData8(i2c, slave);
847 timeout = STM32_I2C_TIMEOUT_USEC;
848 while (!LL_I2C_IsActiveFlag_ADDR(i2c)) {
849 if (stm32_i2c_wait_timeout(&timeout)) {
850 LL_I2C_GenerateStopCondition(i2c);
851 data->current.is_err = 1U;
852 goto end;
853 }
854 }
855
856 LL_I2C_ClearFlag_ADDR(i2c);
857 stm32_i2c_generate_start_condition(i2c);
858 timeout = STM32_I2C_TIMEOUT_USEC;
859 while (!LL_I2C_IsActiveFlag_SB(i2c)) {
860 if (stm32_i2c_wait_timeout(&timeout)) {
861 LL_I2C_GenerateStopCondition(i2c);
862 data->current.is_err = 1U;
863 goto end;
864 }
865 }
866
867 header |= I2C_REQUEST_READ;
868 LL_I2C_TransmitData8(i2c, header);
869 } else {
870 uint8_t slave = ((saddr) << 1) & 0xFF;
871
872 LL_I2C_TransmitData8(i2c, slave | I2C_REQUEST_READ);
873 }
874
875 timeout = STM32_I2C_TIMEOUT_USEC;
876 while (!LL_I2C_IsActiveFlag_ADDR(i2c)) {
877 if (LL_I2C_IsActiveFlag_AF(i2c) || stm32_i2c_wait_timeout(&timeout)) {
878 LL_I2C_ClearFlag_AF(i2c);
879 LL_I2C_GenerateStopCondition(i2c);
880 data->current.is_nack = 1U;
881 goto end;
882 }
883 }
884 /* ADDR must be cleared before NACK generation. Either in 2 byte reception
885 * byte 1 will be NACK'ed and slave wont sent the last byte
886 */
887 LL_I2C_ClearFlag_ADDR(i2c);
888 if (len == 1U) {
889 /* Single byte reception: enable NACK and set STOP */
890 LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
891 } else if (len == 2U) {
892 /* 2-byte reception: enable NACK and set POS */
893 LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
894 LL_I2C_EnableBitPOS(i2c);
895 }
896 }
897
898 while (len) {
899 timeout = STM32_I2C_TIMEOUT_USEC;
900 while (!LL_I2C_IsActiveFlag_RXNE(i2c)) {
901 if (stm32_i2c_wait_timeout(&timeout)) {
902 LL_I2C_GenerateStopCondition(i2c);
903 data->current.is_err = 1U;
904 goto end;
905 }
906 }
907
908 timeout = STM32_I2C_TIMEOUT_USEC;
909 switch (len) {
910 case 1:
911 if (msg->flags & I2C_MSG_STOP) {
912 LL_I2C_GenerateStopCondition(i2c);
913 }
914 len--;
915 *buf = LL_I2C_ReceiveData8(i2c);
916 buf++;
917 break;
918 case 2:
919 while (!LL_I2C_IsActiveFlag_BTF(i2c)) {
920 if (stm32_i2c_wait_timeout(&timeout)) {
921 LL_I2C_GenerateStopCondition(i2c);
922 data->current.is_err = 1U;
923 goto end;
924 }
925 }
926
927 /*
928 * Stop condition must be generated before reading the
929 * last two bytes.
930 */
931 if (msg->flags & I2C_MSG_STOP) {
932 LL_I2C_GenerateStopCondition(i2c);
933 }
934
935 for (uint32_t counter = 2; counter > 0; counter--) {
936 len--;
937 *buf = LL_I2C_ReceiveData8(i2c);
938 buf++;
939 }
940
941 break;
942 case 3:
943 while (!LL_I2C_IsActiveFlag_BTF(i2c)) {
944 if (stm32_i2c_wait_timeout(&timeout)) {
945 LL_I2C_GenerateStopCondition(i2c);
946 data->current.is_err = 1U;
947 goto end;
948 }
949 }
950
951 /* Set NACK before reading N-2 byte*/
952 LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
953 __fallthrough;
954 default:
955 len--;
956 *buf = LL_I2C_ReceiveData8(i2c);
957 buf++;
958 }
959 }
960 end:
961 check_errors(dev, __func__);
962 res = msg_end(dev, next_msg_flags, __func__);
963 if (res < 0) {
964 stm32_i2c_reset(dev);
965 }
966
967 return res;
968 }
969 #endif /* CONFIG_I2C_STM32_INTERRUPT */
970
stm32_i2c_configure_timing(const struct device * dev,uint32_t clock)971 int32_t stm32_i2c_configure_timing(const struct device *dev, uint32_t clock)
972 {
973 const struct i2c_stm32_config *cfg = DEV_CFG(dev);
974 struct i2c_stm32_data *data = DEV_DATA(dev);
975 I2C_TypeDef *i2c = cfg->i2c;
976
977 switch (I2C_SPEED_GET(data->dev_config)) {
978 case I2C_SPEED_STANDARD:
979 LL_I2C_ConfigSpeed(i2c, clock, 100000, LL_I2C_DUTYCYCLE_2);
980 break;
981 case I2C_SPEED_FAST:
982 LL_I2C_ConfigSpeed(i2c, clock, 400000, LL_I2C_DUTYCYCLE_2);
983 break;
984 default:
985 return -EINVAL;
986 }
987
988 return 0;
989 }
990
