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Searched refs:phases (Results 1 – 16 of 16) sorted by relevance

/Zephyr-latest/tests/subsys/sd/sdio/
DREADME.txt8 The test has the following phases:
/Zephyr-latest/tests/drivers/disk/disk_performance/
DREADME.txt6 The test has the following phases:
/Zephyr-latest/tests/drivers/sdhc/
DREADME.txt6 to pass. The test has the following phases:
/Zephyr-latest/tests/subsys/sd/sdmmc/
DREADME.txt10 the following phases:
/Zephyr-latest/tests/subsys/sd/mmc/
DREADME.txt10 the following phases:
/Zephyr-latest/tests/drivers/disk/disk_access/
DREADME.txt6 disk devices as well. The test has the following phases:
/Zephyr-latest/tests/drivers/i2c/i2c_target_api/
DREADME.txt21 In slightly more detail the test has these phases:
/Zephyr-latest/boards/phytec/reel_board/
Dreel_board_nrf52840_2.overlay60 * 4 phases x = {A,B,C,D}.
/Zephyr-latest/doc/hardware/peripherals/
Dmspi.rst8 address and data phases, and multiple signal lines during these phases.
/Zephyr-latest/soc/microchip/mec/
DKconfig200 input/output data phases. Bits[0:2] are CPOL:CPHA_MOSI:CPHA_MISO. Refer
/Zephyr-latest/doc/build/cmake/
Dindex.rst53 The Zephyr build process can be divided into two main phases: a configuration
/Zephyr-latest/boards/native/doc/
Darch_soc.rst23 target hardware in the early phases of development.
/Zephyr-latest/doc/kernel/services/
Dinterrupts.rst509 Zephyr is built in two phases; the first phase of the build produces
/Zephyr-latest/doc/hardware/porting/
Dboard_porting.rst990 useful in development phases, when the board skeleton lives upstream, but other
/Zephyr-latest/doc/connectivity/bluetooth/api/mesh/
Dshell.rst883 * ``Phase``: New Key Refresh Phase. Valid phases are:
/Zephyr-latest/doc/releases/
Drelease-notes-3.7.rst1021 phases as well as variable latency for a transfer. The API now supports from single wire