Searched refs:mie (Results 1 – 10 of 10) sorted by relevance
/Zephyr-latest/soc/common/riscv-privileged/ |
D | soc_common_irq.c | 53 uint32_t mie; in arch_irq_enable() local 68 mie = csr_read_set(mie, 1 << irq); in arch_irq_enable() 73 uint32_t mie; in arch_irq_disable() local 88 mie = csr_read_clear(mie, 1 << irq); in arch_irq_disable() 93 uint32_t mie; in arch_irq_is_enabled() local 103 mie = csr_read(mie); in arch_irq_is_enabled() 105 return !!(mie & (1 << irq)); in arch_irq_is_enabled() 126 csr_write(mie, 0); in soc_interrupt_init()
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/Zephyr-latest/drivers/interrupt_controller/ |
D | intc_swerv_pic.c | 194 uint32_t mie; in arch_irq_enable() local 206 : "=r" (mie) in arch_irq_enable() 212 uint32_t mie; in arch_irq_disable() local 224 : "=r" (mie) in arch_irq_disable() 230 uint32_t mie; in arch_irq_is_enabled() local 236 __asm__ volatile ("csrr %0, mie" : "=r" (mie)); in arch_irq_is_enabled() 238 return !!(mie & (1 << irq)); in arch_irq_is_enabled()
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D | intc_ite_it8xxx2_v2.c | 241 csr_set(mie, MIP_MEIP); in soc_interrupt_init()
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D | intc_ite_it8xxx2.c | 283 csr_set(mie, MIP_MEIP); in soc_interrupt_init()
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/Zephyr-latest/soc/neorv32/ |
D | soc_irq.S | 23 csrrc t2, mie, t0 25 csrrs t2, mie, t1
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D | soc.c | 15 csr_write(mie, 0); in soc_interrupt_init()
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D | reset.S | 21 csrw mie, x0
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/Zephyr-latest/soc/ite/ec/common/ |
D | soc_common_irq.c | 37 return ((csr_read(mie) & BIT(IRQ_M_EXT)) && in arch_irq_is_enabled()
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D | vector.S | 60 csrwi mie, 0
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/Zephyr-latest/soc/ite/ec/it8xxx2/ |
D | soc.c | 301 csr_clear(mie, MIP_MEIP); in riscv_idle() 344 csr_set(mie, MIP_MEIP); in riscv_idle()
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