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Searched refs:gate (Results 1 – 12 of 12) sorted by relevance

/Zephyr-latest/boards/shields/waveshare_epaper/
Dwaveshare_epaper_gdeh029a1.overlay36 gate-line-width = <0x08>;
49 gate-line-width = <0x08>;
Dwaveshare_epaper_gdeh0213b72.overlay36 gate-line-width = <0x0a>;
59 gate-line-width = <0x0a>;
Dwaveshare_epaper_gdeh0213b1.overlay36 gate-line-width = <0x08>;
51 gate-line-width = <0x08>;
/Zephyr-latest/boards/phytec/reel_board/
Dreel_board.dts72 gate-line-width = <0x08>;
87 gate-line-width = <0x08>;
Dreel_board_nrf52840_2.overlay53 gate-line-width = <0x0a>;
97 gate-line-width = <0x0a>;
/Zephyr-latest/boards/particle/boron/
Dparticle_boron.dts21 * single inverter gate -- requires a definition below,
/Zephyr-latest/dts/riscv/ite/
Dit81xx2.dtsi366 clock-gate-offset = <CGC_OFFSET_SMBA>;
383 clock-gate-offset = <CGC_OFFSET_SMBB>;
400 clock-gate-offset = <CGC_OFFSET_SMBC>;
416 clock-gate-offset = <CGC_OFFSET_SMBD>;
431 clock-gate-offset = <CGC_OFFSET_SMBE>;
446 clock-gate-offset = <CGC_OFFSET_SMBF>;
Dit82xx2.dtsi915 clock-gate-offset = <CGC_OFFSET_SMBA>;
930 clock-gate-offset = <CGC_OFFSET_SMBB>;
945 clock-gate-offset = <CGC_OFFSET_SMBC>;
960 clock-gate-offset = <CGC_OFFSET_SMBD>;
975 clock-gate-offset = <CGC_OFFSET_SMBE>;
990 clock-gate-offset = <CGC_OFFSET_SMBF>;
/Zephyr-latest/samples/basic/custom_dts_binding/
DREADME.rst25 :zephyr_file:`samples/basic/custom_dts_binding/dts/bindings/power-switch.yaml`. The gate driver for
/Zephyr-latest/doc/kernel/services/synchronization/
Dsemaphores.rst44 to create a gate through which no waiting thread may pass until the semaphore
/Zephyr-latest/doc/connectivity/networking/conn_mgr/
Dimplementation.rst242 …* It is acceptable to gate this behind a small timeout (separate from the connection timeout) for …
/Zephyr-latest/doc/releases/
Drelease-notes-3.2.rst1326 ``gate-line-width`` properties. The ``gdv``, ``sdv``, ``vcom``, and