1/* 2 * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6#include <mem.h> 7#include <freq.h> 8#include <xtensa/xtensa.dtsi> 9#include <zephyr/dt-bindings/adc/adc.h> 10#include <zephyr/dt-bindings/gpio/gpio.h> 11#include <zephyr/dt-bindings/i2c/i2c.h> 12#include <zephyr/dt-bindings/clock/esp32s3_clock.h> 13#include <zephyr/dt-bindings/interrupt-controller/esp32s3-xtensa-intmux.h> 14#include <dt-bindings/pinctrl/esp32s3-pinctrl.h> 15 16/ { 17 18 aliases { 19 die-temp0 = &coretemp; 20 }; 21 22 chosen { 23 zephyr,canbus = &twai; 24 zephyr,entropy = &trng0; 25 zephyr,flash-controller = &flash; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 cpu0: cpu@0 { 33 device_type = "cpu"; 34 compatible = "espressif,xtensa-lx7"; 35 reg = <0>; 36 cpu-power-states = <&light_sleep &deep_sleep>; 37 clock-source = <ESP32_CPU_CLK_SRC_PLL>; 38 clock-frequency = <DT_FREQ_M(240)>; 39 xtal-freq = <DT_FREQ_M(40)>; 40 }; 41 42 cpu1: cpu@1 { 43 device_type = "cpu"; 44 compatible = "espressif,xtensa-lx7"; 45 reg = <1>; 46 clock-source = <ESP32_CPU_CLK_SRC_PLL>; 47 clock-frequency = <DT_FREQ_M(240)>; 48 xtal-freq = <DT_FREQ_M(40)>; 49 }; 50 51 power-states { 52 light_sleep: light_sleep { 53 compatible = "zephyr,power-state"; 54 power-state-name = "standby"; 55 min-residency-us = <200>; 56 exit-latency-us = <133>; 57 }; 58 59 deep_sleep: deep_sleep { 60 compatible = "zephyr,power-state"; 61 power-state-name = "soft-off"; 62 min-residency-us = <2000>; 63 exit-latency-us = <382>; 64 }; 65 }; 66 }; 67 68 wifi: wifi { 69 compatible = "espressif,esp32-wifi"; 70 status = "disabled"; 71 }; 72 73 esp32_bt_hci: esp32_bt_hci { 74 compatible = "espressif,esp32-bt-hci"; 75 status = "disabled"; 76 }; 77 78 pinctrl: pin-controller { 79 compatible = "espressif,esp32-pinctrl"; 80 status = "okay"; 81 }; 82 83 soc { 84 #address-cells = <1>; 85 #size-cells = <1>; 86 compatible = "simple-bus"; 87 ranges; 88 89 icache0: memory@42000000 { 90 compatible = "zephyr,memory-region"; 91 reg = <0x42000000 DT_SIZE_M(32)>; 92 zephyr,memory-region = "ICACHE0"; 93 }; 94 95 dcache0: memory@3c000000 { 96 compatible = "zephyr,memory-region"; 97 reg = <0x3c000000 DT_SIZE_M(32)>; 98 zephyr,memory-region = "DCACHE0"; 99 100 psram0: psram0 { 101 compatible = "espressif,esp32-psram"; 102 size = <0x0>; 103 }; 104 }; 105 106 sram0: memory@40370000 { 107 compatible = "zephyr,memory-region", "mmio-sram"; 108 reg = <0x40370000 DT_SIZE_K(32)>; 109 zephyr,memory-region = "SRAM0"; 110 }; 111 112 sram1: memory@3fc88000 { 113 compatible = "zephyr,memory-region", "mmio-sram"; 114 reg = <0x3fc88000 DT_SIZE_K(416)>; 115 zephyr,memory-region = "SRAM1"; 116 }; 117 118 sram2: memory@3fcf0000 { 119 compatible = "zephyr,memory-region", "mmio-sram"; 120 reg = <0x3fcf0000 DT_SIZE_K(64)>; 121 zephyr,memory-region = "SRAM2"; 122 }; 123 124 ipmmem0: memory@3fce5000 { 125 compatible = "mmio-sram"; 126 reg = <0x3fce5000 0x400>; 127 }; 128 129 shm0: memory@3fce5400 { 130 compatible = "mmio-sram"; 131 reg = <0x3fce5400 0x4000>; 132 }; 133 134 ipm0: ipm@3fce9400 { 135 compatible = "espressif,esp32-ipm"; 136 reg = <0x3fce9400 0x8>; 137 status = "disabled"; 138 shared-memory = <&ipmmem0>; 139 shared-memory-size = <0x400>; 140 interrupts = 141 <FROM_CPU_INTR0_SOURCE IRQ_DEFAULT_PRIORITY 0>, 142 <FROM_CPU_INTR1_SOURCE IRQ_DEFAULT_PRIORITY 0>; 143 interrupt-parent = <&intc>; 144 }; 145 146 mbox0: mbox@3fce9408 { 147 compatible = "espressif,mbox-esp32"; 148 reg = <0x3fce9408 0x8>; 149 status = "disabled"; 150 shared-memory = <&ipmmem0>; 151 shared-memory-size = <0x400>; 152 interrupts = 153 <FROM_CPU_INTR0_SOURCE IRQ_DEFAULT_PRIORITY 0>, 154 <FROM_CPU_INTR1_SOURCE IRQ_DEFAULT_PRIORITY 0>; 155 interrupt-parent = <&intc>; 156 #mbox-cells = <1>; 157 }; 158 159 intc: interrupt-controller@600c2000 { 160 #interrupt-cells = <3>; 161 #address-cells = <0>; 162 compatible = "espressif,esp32-intc"; 163 interrupt-controller; 164 reg = <0x600c2000 0x1000>; 165 status = "okay"; 166 }; 167 168 rtc: rtc@60021000 { 169 compatible = "espressif,esp32-rtc"; 170 reg = <0x60021000 0x2000>; 171 fast-clk-src = <ESP32_RTC_FAST_CLK_SRC_RC_FAST>; 172 slow-clk-src = <ESP32_RTC_SLOW_CLK_SRC_RC_SLOW>; 173 #clock-cells = <1>; 174 status = "okay"; 175 }; 176 177 xt_wdt: xt_wdt@60021004 { 178 compatible = "espressif,esp32-xt-wdt"; 179 reg = <0x60021004 0x4>; 180 clocks = <&rtc ESP32_MODULE_MAX>; 181 interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 182 interrupt-parent = <&intc>; 183 status = "disabled"; 184 }; 185 186 rtc_timer: rtc_timer@60008004 { 187 reg = <0x60008004 0xC>; 188 compatible = "espressif,esp32-rtc-timer"; 189 clocks = <&rtc ESP32_MODULE_MAX>; 190 interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 191 interrupt-parent = <&intc>; 192 status = "disabled"; 193 }; 194 195 flash: flash-controller@60002000 { 196 compatible = "espressif,esp32-flash-controller"; 197 reg = <0x60002000 0x1000>; 198 #address-cells = <1>; 199 #size-cells = <1>; 200 201 flash0: flash@0 { 202 compatible = "soc-nv-flash"; 203 erase-block-size = <4096>; 204 write-block-size = <4>; 205 /* Flash size is specified in SOC/SIP dtsi */ 206 }; 207 }; 208 209 uart0: uart@60000000 { 210 compatible = "espressif,esp32-uart"; 211 reg = <0x60000000 0x1000>; 212 interrupts = <UART0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 213 interrupt-parent = <&intc>; 214 clocks = <&rtc ESP32_UART0_MODULE>; 215 status = "disabled"; 216 }; 217 218 uart1: uart@60010000 { 219 compatible = "espressif,esp32-uart"; 220 reg = <0x60010000 0x1000>; 221 interrupts = <UART1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 222 interrupt-parent = <&intc>; 223 clocks = <&rtc ESP32_UART1_MODULE>; 224 status = "disabled"; 225 }; 226 227 uart2: uart@6002e000 { 228 compatible = "espressif,esp32-uart"; 229 reg = <0x6002e000 0x1000>; 230 interrupts = <UART2_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 231 interrupt-parent = <&intc>; 232 clocks = <&rtc ESP32_UART2_MODULE>; 233 status = "disabled"; 234 }; 235 236 gpio: gpio { 237 compatible = "simple-bus"; 238 gpio-map-mask = <0xffffffe0 0xffffffc0>; 239 gpio-map-pass-thru = <0x1f 0x3f>; 240 gpio-map = < 241 0x00 0x0 &gpio0 0x0 0x0 242 0x20 0x0 &gpio1 0x0 0x0 243 >; 244 #gpio-cells = <2>; 245 #address-cells = <1>; 246 #size-cells = <1>; 247 ranges; 248 249 gpio0: gpio@60004000 { 250 compatible = "espressif,esp32-gpio"; 251 gpio-controller; 252 #gpio-cells = <2>; 253 reg = <0x60004000 0x800>; 254 interrupts = <GPIO_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 255 interrupt-parent = <&intc>; 256 /* Maximum available pins (per port) 257 * Actual occupied pins are specified 258 * on part number dtsi level, using 259 * the `gpio-reserved-ranges` property. 260 */ 261 ngpios = <32>; /* 0..31 */ 262 }; 263 264 gpio1: gpio@60004800 { 265 compatible = "espressif,esp32-gpio"; 266 gpio-controller; 267 #gpio-cells = <2>; 268 reg = <0x60004800 0x800>; 269 interrupts = <GPIO_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 270 interrupt-parent = <&intc>; 271 ngpios = <22>; /* 32..53 */ 272 }; 273 }; 274 275 touch: touch@6000885c { 276 compatible = "espressif,esp32-touch"; 277 reg = <0x6000885c 0x88 0x60008908 0x18>; 278 interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 279 interrupt-parent = <&intc>; 280 status = "disabled"; 281 }; 282 283 i2c0: i2c@60013000 { 284 compatible = "espressif,esp32-i2c"; 285 #address-cells = <1>; 286 #size-cells = <0>; 287 reg = <0x60013000 DT_SIZE_K(4)>; 288 interrupts = <I2C_EXT0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 289 interrupt-parent = <&intc>; 290 clocks = <&rtc ESP32_I2C0_MODULE>; 291 status = "disabled"; 292 }; 293 294 i2c1: i2c@60027000 { 295 compatible = "espressif,esp32-i2c"; 296 #address-cells = <1>; 297 #size-cells = <0>; 298 reg = <0x60027000 DT_SIZE_K(4)>; 299 interrupts = <I2C_EXT1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 300 interrupt-parent = <&intc>; 301 clocks = <&rtc ESP32_I2C1_MODULE>; 302 status = "disabled"; 303 }; 304 305 i2s0: i2s@6000f000 { 306 compatible = "espressif,esp32-i2s"; 307 #address-cells = <1>; 308 #size-cells = <0>; 309 reg = <0x6000f000 0x1000>; 310 interrupts = <I2S0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 311 interrupt-parent = <&intc>; 312 clocks = <&rtc ESP32_I2S0_MODULE>; 313 dmas = <&dma 2>, <&dma 3>; 314 dma-names = "rx", "tx"; 315 unit = <0>; 316 status = "disabled"; 317 }; 318 319 i2s1: i2s@6002d000 { 320 compatible = "espressif,esp32-i2s"; 321 #address-cells = <1>; 322 #size-cells = <0>; 323 reg = <0x6002d000 0x1000>; 324 interrupts = <I2S1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 325 interrupt-parent = <&intc>; 326 clocks = <&rtc ESP32_I2S1_MODULE>; 327 dmas = <&dma 4>, <&dma 5>; 328 dma-names = "rx", "tx"; 329 unit = <1>; 330 status = "disabled"; 331 }; 332 333 spi2: spi@60024000 { 334 compatible = "espressif,esp32-spi"; 335 reg = <0x60024000 DT_SIZE_K(4)>; 336 interrupts = <SPI2_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 337 interrupt-parent = <&intc>; 338 clocks = <&rtc ESP32_SPI2_MODULE>; 339 dma-clk = <ESP32_GDMA_MODULE>; 340 dma-host = <0>; 341 status = "disabled"; 342 }; 343 344 spi3: spi@60025000 { 345 compatible = "espressif,esp32-spi"; 346 reg = <0x60025000 DT_SIZE_K(4)>; 347 interrupts = <SPI3_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 348 interrupt-parent = <&intc>; 349 clocks = <&rtc ESP32_SPI3_MODULE>; 350 dma-clk = <ESP32_GDMA_MODULE>; 351 dma-host = <1>; 352 status = "disabled"; 353 }; 354 355 coretemp: coretemp@60008800 { 356 compatible = "espressif,esp32-temp"; 357 friendly-name = "coretemp"; 358 reg = <0x60008800 0x4>; 359 status = "disabled"; 360 }; 361 362 adc0: adc@60040000 { 363 compatible = "espressif,esp32-adc"; 364 reg = <0x60040000 4>; 365 clocks = <&rtc ESP32_SARADC_MODULE>; 366 unit = <1>; 367 channel-count = <10>; 368 #io-channel-cells = <1>; 369 status = "disabled"; 370 }; 371 372 adc1: adc@60040004 { 373 compatible = "espressif,esp32-adc"; 374 reg = <0x60040004 4>; 375 clocks = <&rtc ESP32_SARADC_MODULE>; 376 unit = <2>; 377 channel-count = <10>; 378 #io-channel-cells = <1>; 379 status = "disabled"; 380 }; 381 382 twai: can@6002b000 { 383 compatible = "espressif,esp32-twai"; 384 reg = <0x6002b000 DT_SIZE_K(4)>; 385 interrupts = <TWAI_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 386 interrupt-parent = <&intc>; 387 clocks = <&rtc ESP32_TWAI_MODULE>; 388 status = "disabled"; 389 }; 390 391 lcd_cam: lcd_cam@60041000 { 392 compatible = "espressif,esp32-lcd-cam"; 393 reg = <0x60041000 DT_SIZE_K(4)>; 394 clocks = <&rtc ESP32_LCD_CAM_MODULE>; 395 interrupts = <LCD_CAM_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 396 interrupt-parent = <&intc>; 397 status = "disabled"; 398 }; 399 400 usb_serial: uart@60038000 { 401 compatible = "espressif,esp32-usb-serial"; 402 reg = <0x60038000 DT_SIZE_K(4)>; 403 status = "disabled"; 404 interrupts = <USB_SERIAL_JTAG_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 405 interrupt-parent = <&intc>; 406 clocks = <&rtc ESP32_USB_MODULE>; 407 }; 408 409 timer0: counter@6001f000 { 410 compatible = "espressif,esp32-timer"; 411 reg = <0x6001f000 DT_SIZE_K(4)>; 412 clocks = <&rtc ESP32_TIMG0_MODULE>; 413 group = <0>; 414 index = <0>; 415 interrupts = <TG0_T0_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 416 interrupt-parent = <&intc>; 417 status = "disabled"; 418 }; 419 420 timer1: counter@6001f024 { 421 compatible = "espressif,esp32-timer"; 422 reg = <0x6001f024 DT_SIZE_K(4)>; 423 clocks = <&rtc ESP32_TIMG0_MODULE>; 424 group = <0>; 425 index = <1>; 426 interrupts = <TG0_T1_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 427 interrupt-parent = <&intc>; 428 status = "disabled"; 429 }; 430 431 timer2: counter@60020000 { 432 compatible = "espressif,esp32-timer"; 433 reg = <0x60020000 DT_SIZE_K(4)>; 434 clocks = <&rtc ESP32_TIMG1_MODULE>; 435 group = <1>; 436 index = <0>; 437 interrupts = <TG1_T0_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 438 interrupt-parent = <&intc>; 439 status = "disabled"; 440 }; 441 442 timer3: counter@60020024 { 443 compatible = "espressif,esp32-timer"; 444 reg = <0x60020024 DT_SIZE_K(4)>; 445 clocks = <&rtc ESP32_TIMG1_MODULE>; 446 group = <1>; 447 index = <1>; 448 interrupts = <TG1_T1_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 449 interrupt-parent = <&intc>; 450 }; 451 452 wdt0: watchdog@6001f048 { 453 compatible = "espressif,esp32-watchdog"; 454 reg = <0x6001f048 0x20>; 455 interrupts = <TG0_WDT_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 456 interrupt-parent = <&intc>; 457 clocks = <&rtc ESP32_TIMG0_MODULE>; 458 status = "disabled"; 459 }; 460 461 wdt1: watchdog@60020048 { 462 compatible = "espressif,esp32-watchdog"; 463 reg = <0x60020048 0x20>; 464 interrupts = <TG1_WDT_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 465 interrupt-parent = <&intc>; 466 clocks = <&rtc ESP32_TIMG1_MODULE>; 467 status = "disabled"; 468 }; 469 470 trng0: trng@6003507c { 471 compatible = "espressif,esp32-trng"; 472 reg = <0x6003507c 0x4>; 473 status = "disabled"; 474 }; 475 476 ledc0: ledc@60019000 { 477 compatible = "espressif,esp32-ledc"; 478 #pwm-cells = <3>; 479 reg = <0x60019000 DT_SIZE_K(4)>; 480 clocks = <&rtc ESP32_LEDC_MODULE>; 481 status = "disabled"; 482 }; 483 484 mcpwm0: mcpwm@6001e000 { 485 compatible = "espressif,esp32-mcpwm"; 486 reg = <0x6001e000 DT_SIZE_K(4)>; 487 interrupts = <PWM0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 488 interrupt-parent = <&intc>; 489 clocks = <&rtc ESP32_PWM0_MODULE>; 490 #pwm-cells = <3>; 491 status = "disabled"; 492 }; 493 494 mcpwm1: mcpwm@6002c000 { 495 compatible = "espressif,esp32-mcpwm"; 496 reg = <0x6002c000 DT_SIZE_K(4)>; 497 interrupts = <PWM1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 498 interrupt-parent = <&intc>; 499 clocks = <&rtc ESP32_PWM1_MODULE>; 500 #pwm-cells = <3>; 501 status = "disabled"; 502 }; 503 504 pcnt: pcnt@60017000 { 505 compatible = "espressif,esp32-pcnt"; 506 reg = <0x60017000 DT_SIZE_K(4)>; 507 interrupts = <PCNT_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 508 interrupt-parent = <&intc>; 509 clocks = <&rtc ESP32_PCNT_MODULE>; 510 status = "disabled"; 511 }; 512 513 dma: dma@6003f000 { 514 compatible = "espressif,esp32-gdma"; 515 reg = <0x6003f000 DT_SIZE_K(4)>; 516 #dma-cells = <1>; 517 interrupts = 518 <DMA_IN_CH0_INTR_SOURCE IRQ_DEFAULT_PRIORITY ESP_INTR_FLAG_SHARED>, 519 <DMA_OUT_CH0_INTR_SOURCE IRQ_DEFAULT_PRIORITY ESP_INTR_FLAG_SHARED>, 520 <DMA_IN_CH1_INTR_SOURCE IRQ_DEFAULT_PRIORITY ESP_INTR_FLAG_SHARED>, 521 <DMA_OUT_CH1_INTR_SOURCE IRQ_DEFAULT_PRIORITY ESP_INTR_FLAG_SHARED>, 522 <DMA_IN_CH2_INTR_SOURCE IRQ_DEFAULT_PRIORITY ESP_INTR_FLAG_SHARED>, 523 <DMA_OUT_CH2_INTR_SOURCE IRQ_DEFAULT_PRIORITY ESP_INTR_FLAG_SHARED>, 524 <DMA_IN_CH3_INTR_SOURCE IRQ_DEFAULT_PRIORITY ESP_INTR_FLAG_SHARED>, 525 <DMA_OUT_CH3_INTR_SOURCE IRQ_DEFAULT_PRIORITY ESP_INTR_FLAG_SHARED>, 526 <DMA_IN_CH4_INTR_SOURCE IRQ_DEFAULT_PRIORITY ESP_INTR_FLAG_SHARED>, 527 <DMA_OUT_CH4_INTR_SOURCE IRQ_DEFAULT_PRIORITY ESP_INTR_FLAG_SHARED>; 528 interrupt-parent = <&intc>; 529 clocks = <&rtc ESP32_GDMA_MODULE>; 530 dma-channels = <10>; 531 dma-buf-addr-alignment = <4>; 532 status = "disabled"; 533 }; 534 535 sdhc: sdhc@60028000 { 536 compatible = "espressif,esp32-sdhc"; 537 reg = <0x60028000 0x1000>; 538 interrupts = <SDIO_HOST_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 539 interrupt-parent = <&intc>; 540 clocks = <&rtc ESP32_SDMMC_MODULE>; 541 #address-cells = <1>; 542 #size-cells = <0>; 543 544 sdhc0: sdhc@0 { 545 compatible = "espressif,esp32-sdhc-slot"; 546 reg = <0>; 547 status = "disabled"; 548 }; 549 550 sdhc1: sdhc@1 { 551 compatible = "espressif,esp32-sdhc-slot"; 552 reg = <1>; 553 status = "disabled"; 554 }; 555 }; 556 }; 557}; 558
