| /trusted-firmware-a-3.4.0/drivers/nxp/ddr/phy-gen1/ |
| D | phy.c | 25 debug("clk_cntl = 0x%x\n", regs->clk_cntl); in cal_ddr_sdram_clk_cntl()
33 debug("cdr[0] = 0x%x\n", regs->cdr[0]); in cal_ddr_cdr()
34 debug("cdr[1] = 0x%x\n", regs->cdr[1]); in cal_ddr_cdr()
58 debug("wrlvl_cntl[0] = 0x%x\n", regs->wrlvl_cntl[0]); in cal_ddr_wrlvl_cntl()
59 debug("wrlvl_cntl[1] = 0x%x\n", regs->wrlvl_cntl[1]); in cal_ddr_wrlvl_cntl()
60 debug("wrlvl_cntl[2] = 0x%x\n", regs->wrlvl_cntl[2]); in cal_ddr_wrlvl_cntl()
68 regs->debug[18] = popts->cswl_override; in cal_ddr_dbg()
73 regs->debug[2] = U(0x00000400); in cal_ddr_dbg()
74 regs->debug[4] = U(0xff800800); in cal_ddr_dbg()
75 regs->debug[5] = U(0x08000800); in cal_ddr_dbg()
[all …]
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| /trusted-firmware-a-3.4.0/drivers/nxp/ddr/nxp-ddr/ |
| D | dimm.c | 167 debug("n_ranks %d\n", pdimm->n_ranks); in cal_dimm_params()
173 debug("rank_density 0x%llx\n", pdimm->rank_density); in cal_dimm_params()
175 debug("capacity 0x%llx\n", pdimm->capacity); in cal_dimm_params()
177 debug("die density 0x%x\n", pdimm->die_density); in cal_dimm_params()
179 debug("primary_sdram_width %d\n", pdimm->primary_sdram_width); in cal_dimm_params()
185 debug("ec_sdram_width %d\n", pdimm->ec_sdram_width); in cal_dimm_params()
187 debug("device_width %d\n", pdimm->device_width); in cal_dimm_params()
190 debug("package_3ds %d\n", pdimm->package_3ds); in cal_dimm_params()
251 debug("rdimm %d\n", pdimm->rdimm); in cal_dimm_params()
252 debug("mirrored_dimm %d\n", pdimm->mirrored_dimm); in cal_dimm_params()
[all …]
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| D | ddr.c | 302 debug("cs %d\n", i); in cal_odt()
304 debug(" odt_rd_cfg 0x%x\n", in cal_odt()
307 debug(" odt_wr_cfg 0x%x\n", in cal_odt()
310 debug(" odt_rtt_norm 0x%x\n", in cal_odt()
313 debug(" odt_rtt_wr 0x%x\n", in cal_odt()
316 debug(" auto_precharge %d\n", in cal_odt()
336 debug("ctlr_init_ecc %d\n", popts->ctlr_init_ecc); in cal_opts()
359 debug("x4_en %d\n", popts->x4_en); in cal_opts()
372 debug("ap_en %d\n", popts->ap_en); in cal_opts()
392 debug("ctlr_intlv %d\n", popts->ctlr_intlv); in cal_intlv()
[all …]
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| D | ddrc.c | 90 debug("\nFound highest position %d, mapping to %d, ", in bist()
94 debug("in dec[%d], bit %d (0x%x)\n", in bist()
100 debug("Increase wait time to %d ms\n", timeout * 10); in bist()
116 debug("Timer remains %d\n", timeout); in bist()
156 debug("*0x%lx = 0x%lx\n", (unsigned long)ddr, val); in dump_ddrc()
317 ddr_out32(&ddr->debug[3], 0x124a02c0); in ddrc_set_regs()
326 if (regs->debug[i] != 0) { in ddrc_set_regs()
332 ddr_out32(&ddr->debug[i], regs->debug[i]); in ddrc_set_regs()
341 debug("Disable address decoding\n"); in ddrc_set_regs()
353 ddr_out32(&ddr->debug[37], (U(1) << 31)); in ddrc_set_regs()
[all …]
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| D | regs.c | 69 debug("cs%d\n", i); in cal_csn_config()
70 debug(" _config = 0x%x\n", regs->cs[i].config); in cal_csn_config()
236 debug("timing_cfg[0] = 0x%x\n", regs->timing_cfg[0]); in cal_timing_cfg()
261 debug("timing_cfg[1] = 0x%x\n", regs->timing_cfg[1]); in cal_timing_cfg()
278 debug("timing_cfg[2] = 0x%x\n", regs->timing_cfg[2]); in cal_timing_cfg()
288 debug("timing_cfg[3] = 0x%x\n", regs->timing_cfg[3]); in cal_timing_cfg()
299 debug("timing_cfg[4] = 0x%x\n", regs->timing_cfg[4]); in cal_timing_cfg()
310 debug("timing_cfg[5] = 0x%x\n", regs->timing_cfg[5]); in cal_timing_cfg()
317 debug("timing_cfg[6] = 0x%x\n", regs->timing_cfg[6]); in cal_timing_cfg()
321 debug("PAR_LAT = 0x%x\n", par_lat); in cal_timing_cfg()
[all …]
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| D | utility.c | 120 debug("%s: nothing to do.\n", __func__); in disable_unused_ddrc()
138 debug("valid_spd_mask = 0x%x\n", valid_spd_mask); in disable_unused_ddrc()
149 debug("Disable first DDR controller\n"); in disable_unused_ddrc()
155 debug("Disable second DDR controller\n"); in disable_unused_ddrc()
165 debug("Both controllers in use.\n"); in disable_unused_ddrc()
187 debug("Setting HN-F node %d\n", i); in disable_unused_ddrc()
188 debug("nodeid = 0x%x\n", nodeid); in disable_unused_ddrc()
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| /trusted-firmware-a-3.4.0/drivers/marvell/comphy/ |
| D | phy-comphy-common.h | 15 #define debug(format...) printf(format) macro
17 #define debug(format, arg...) macro
147 debug("<atf>: WR to addr = 0x%lx, data = 0x%x (mask = 0x%x) - ", in reg_set()
149 debug("old value = 0x%x ==> ", mmio_read_32(addr)); in reg_set()
152 debug("new val 0x%x\n", mmio_read_32(addr)); in reg_set()
159 debug("<atf>: WR to addr = 0x%lx, data = 0x%x (mask = 0x%x) - ", in reg_set16()
161 debug("old value = 0x%x ==> ", mmio_read_16(addr)); in reg_set16()
164 debug("new val 0x%x\n", mmio_read_16(addr)); in reg_set16()
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| D | phy-comphy-cp110.c | 107 debug("cp_base 0x%" PRIx64 ", ap_io_base 0x%lx, cp_offset 0x%lx\n", in mvebu_cp110_get_ap_and_cp_nr()
342 debug("%s: inverting TX polarity\n", __func__); in mvebu_cp110_polarity_invert()
348 debug("%s: inverting RX polarity\n", __func__); in mvebu_cp110_polarity_invert()
381 debug(" add hpipe 0x%lx, sd 0x%lx, comphy 0x%lx\n", in mvebu_cp110_comphy_sata_power_on()
383 debug("stage: RFU configurations - hard reset comphy\n"); in mvebu_cp110_comphy_sata_power_on()
410 debug("stage: Comphy configuration\n"); in mvebu_cp110_comphy_sata_power_on()
431 debug("stage: Analog parameters from ETP(HW)\n"); in mvebu_cp110_comphy_sata_power_on()
699 debug("stage: RFU configurations - hard reset comphy\n"); in mvebu_cp110_comphy_sgmii_power_on()
762 debug("stage: Comphy configuration\n"); in mvebu_cp110_comphy_sgmii_power_on()
789 debug("stage: Analog parameters from ETP(HW)\n"); in mvebu_cp110_comphy_sgmii_power_on()
[all …]
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| /trusted-firmware-a-3.4.0/docs/security_advisories/ |
| D | security-advisory-tfv-2.rst | 5 | Title | Enabled secure self-hosted invasive debug interface can |
25 The ``MDCR_EL3.SDD`` bit controls AArch64 secure self-hosted invasive debug
28 entrypoint code, which enables debug exceptions from the secure world. This can
31 by saving and restoring the appropriate debug registers), this may allow a
34 The ``MDCR_EL3.SDD`` bit should be assigned to ``1`` to disable debug exceptions
42 secure self-hosted invasive debug enablement. TF assigns these bits to ``00``
43 meaning that debug exceptions from Secure EL1 are enabled by the authentication
45 secure privileged invasive debug is enabled by the authentication interface, at
48 However, given that TF contains no support for handling debug exceptions, the
49 ``MDCR_EL3.SPD32`` bits should be assigned to ``10`` to disable debug exceptions
|
| /trusted-firmware-a-3.4.0/plat/nxp/soc-ls1046a/ls1046aqds/ |
| D | ddr_init.c | 33 debug("RDIMM parameters not set.\n"); in ddr_board_options()
68 debug("platform clock %lu\n", sys.freq_platform); in init_ddr()
69 debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0); in init_ddr()
70 debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1); in init_ddr()
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| /trusted-firmware-a-3.4.0/drivers/nxp/ddr/phy-gen2/ |
| D | phy.c | 372 debug("CDD rrmax %x wwmax %x rwmax %x wrmax %x\n", in get_cdd_val()
427 debug("Saving 1D Training reg val at: %d\n", phy_store); in save_phy_training_values()
431 debug("%d. Reg: %x, value: %x PHY: %p\n", i, in save_phy_training_values()
444 debug("Saving 2D Training reg val at:%d\n", phy_store); in save_phy_training_values()
450 debug("%d.2D addr:0x%x,val:0x%x,PHY:0x%p\n", in save_phy_training_values()
481 debug("Restoring Training register values\n"); in restore_phy_training_values()
507 debug("Restoring 1D Training reg val at:%08x\n", phy_store); in restore_phy_training_values()
512 debug("%d. Reg: %x, value: %x PHY: %p\n", i, in restore_phy_training_values()
526 debug("Restoring 2D Training reg val at:%08x\n", in restore_phy_training_values()
532 debug("%d. Reg: %x, value: %x PHY: %p\n", i, in restore_phy_training_values()
[all …]
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| /trusted-firmware-a-3.4.0/plat/nxp/soc-ls1088a/ls1088aqds/ |
| D | ddr_init.c | 37 debug("RDIMM parameters not set.\n"); in ddr_board_options()
66 debug("platform clock %lu\n", sys.freq_platform); in init_ddr()
67 debug("DDR PLL %lu\n", sys.freq_ddr_pll0); in init_ddr()
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| /trusted-firmware-a-3.4.0/plat/nxp/soc-ls1088a/ls1088ardb/ |
| D | ddr_init.c | 38 debug("RDIMM parameters not set.\n"); in ddr_board_options()
67 debug("platform clock %lu\n", sys.freq_platform); in init_ddr()
68 debug("DDR PLL %lu\n", sys.freq_ddr_pll0); in init_ddr()
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| /trusted-firmware-a-3.4.0/drivers/marvell/secure_dfx_access/ |
| D | misc_dfx.c | 17 #define debug(format...) NOTICE(format) macro
19 #define debug(format, arg...) macro
108 debug("func %ld, addr 0x%lx, val 0x%lx\n", func, addr, val); in mvebu_dfx_misc_handle()
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| D | armada_thermal.c | 17 #define debug(format...) NOTICE(format) macro
19 #define debug(format, arg...) macro
212 debug("thermal: Initialization done\n"); in armada_ap806_thermal_init()
|
| /trusted-firmware-a-3.4.0/plat/nxp/soc-ls1043a/ls1043ardb/ |
| D | ddr_init.c | 50 .debug[28] = U(0x00700046),
139 debug("platform clock %lu\n", sys.freq_platform);
140 debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0);
141 debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1);
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| /trusted-firmware-a-3.4.0/include/drivers/nxp/ddr/ |
| D | ddr.h | 36 #define debug(...) INFO(__VA_ARGS__) macro
38 #define debug(...) VERBOSE(__VA_ARGS__) macro
75 unsigned int debug[64]; member
|
| /trusted-firmware-a-3.4.0/plat/marvell/armada/common/ |
| D | mrvl_sip_svc.c | 25 #define debug(format...) NOTICE(format) macro
27 #define debug(format, arg...) macro
85 debug("%s: got SMC (0x%x) x1 0x%lx, x2 0x%lx, x3 0x%lx\n", in mrvl_sip_smc_handler()
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| /trusted-firmware-a-3.4.0/plat/nxp/soc-ls1046a/ls1046afrwy/ |
| D | ddr_init.c | 156 debug("platform clock %lu\n", sys.freq_platform); in init_ddr()
157 debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0); in init_ddr()
158 debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1); in init_ddr()
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| /trusted-firmware-a-3.4.0/plat/nxp/soc-ls1028a/ls1028ardb/ |
| D | ddr_init.c | 53 .debug[28] = U(0x00700046),
169 debug("platform clock %lu\n", sys.freq_platform); in init_ddr()
170 debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0); in init_ddr()
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| /trusted-firmware-a-3.4.0/plat/nvidia/tegra/common/ |
| D | tegra_common.mk | 42 ${TEGRA_LIBS}/debug/profiler.c \
44 ${TEGRA_LIBS}/debug/profiler.c \
|
| /trusted-firmware-a-3.4.0/plat/nxp/soc-lx2160a/lx2160ardb/ |
| D | ddr_init.c | 177 debug("platform clock %lu\n", sys.freq_platform); in init_ddr()
178 debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0); in init_ddr()
179 debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1); in init_ddr()
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| /trusted-firmware-a-3.4.0/plat/nxp/soc-ls1046a/ls1046ardb/ |
| D | ddr_init.c | 210 debug("RDIMM parameters not set.\n"); in ddr_board_options()
245 debug("platform clock %lu\n", sys.freq_platform); in init_ddr()
246 debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0); in init_ddr()
247 debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1); in init_ddr()
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| /trusted-firmware-a-3.4.0/plat/mediatek/build_helpers/ |
| D | conditional_eval_options.mk | 22 ifeq ($(BUILD_TYPE),debug)
|
| /trusted-firmware-a-3.4.0/docs/plat/ |
| D | warp7.rst | 80 …ot/u-boot.cfgout -T imximage -e 0x9df00000 -d ./build/warp7/debug/bl2.bin ./build/warp7/debug/bl2.…
90 tools/cert_create/cert_create -n --rot-key "build/warp7/debug/rot_key.pem" \
94 --tb-fw=build/warp7/debug/bl2.bin \
176 …oot.cfgout.warp7 -T imximage -e 0x9df00000 -d ./build/warp7/debug/bl2.bin ./build/warp7/debug/bl2.…
179 cp build/warp7/debug/bl2.bin.imx ${TEMP}
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