372 	debug("CDD rrmax %x wwmax %x rwmax %x wrmax %x\n",  in get_cdd_val()
427 		debug("Saving 1D Training reg val at: %d\n", phy_store);  in save_phy_training_values()
431 			debug("%d. Reg: %x, value: %x PHY: %p\n", i,  in save_phy_training_values()
444 			debug("Saving 2D Training reg val at:%d\n", phy_store);  in save_phy_training_values()
450 				debug("%d.2D addr:0x%x,val:0x%x,PHY:0x%p\n",  in save_phy_training_values()
481 	debug("Restoring Training register values\n");  in restore_phy_training_values()
507 		debug("Restoring 1D Training reg val at:%08x\n", phy_store);  in restore_phy_training_values()
512 			debug("%d. Reg: %x, value: %x PHY: %p\n", i,  in restore_phy_training_values()
526 			debug("Restoring 2D Training reg val at:%08x\n",  in restore_phy_training_values()
532 				debug("%d. Reg: %x, value: %x PHY: %p\n", i,  in restore_phy_training_values()
692 	debug("seq0bdly0 = 0x%x\n", phy_io_read16(phy, addr));  in prog_seq0bdly0()
697 	debug("seq0bdly1 = 0x%x\n", phy_io_read16(phy, addr));  in prog_seq0bdly0()
702 	debug("seq0bdly2 = 0x%x\n", phy_io_read16(phy, addr));  in prog_seq0bdly0()
707 	debug("seq0bdly3 = 0x%x\n", phy_io_read16(phy, addr));  in prog_seq0bdly0()
784 		debug("mr[%d] = 0x%x\n", i, input->mr[i]);  in phy_gen2_init_input()
787 	debug("input->cs_d0 = 0x%x\n", input->cs_d0);  in phy_gen2_init_input()
788 	debug("input->cs_d1 = 0x%x\n", input->cs_d1);  in phy_gen2_init_input()
789 	debug("input->mirror = 0x%x\n", input->mirror);  in phy_gen2_init_input()
790 	debug("PHY ODT impedance = %d ohm\n", input->adv.odtimpedance);  in phy_gen2_init_input()
791 	debug("PHY DQ driver impedance = %d ohm\n", input->adv.tx_impedance);  in phy_gen2_init_input()
792 	debug("PHY Addr driver impedance = %d ohm\n", input->adv.atx_impedance);  in phy_gen2_init_input()
795 		debug("odt[%d] = 0x%x\n", i, input->odt[i]);  in phy_gen2_init_input()
800 			debug("input->rcw[%d] = 0x%x\n", i, input->rcw[i]);  in phy_gen2_init_input()
802 		debug("input->rcw3x = 0x%x\n", input->rcw3x);  in phy_gen2_init_input()
910 	debug("msg_blk->dram_type = 0x%x\n", msg_blk->dram_type);  in phy_gen2_msg_init()
911 	debug("msg_blk->sequence_ctrl = 0x%x\n", msg_blk->sequence_ctrl);  in phy_gen2_msg_init()
912 	debug("msg_blk->phy_cfg = 0x%x\n", msg_blk->phy_cfg);  in phy_gen2_msg_init()
913 	debug("msg_blk->x16present = 0x%x\n", msg_blk->x16present);  in phy_gen2_msg_init()
914 	debug("msg_blk->dramfreq = 0x%x\n", msg_blk->dramfreq);  in phy_gen2_msg_init()
915 	debug("msg_blk->pll_bypass_en = 0x%x\n", msg_blk->pll_bypass_en);  in phy_gen2_msg_init()
916 	debug("msg_blk->dfi_freq_ratio = 0x%x\n", msg_blk->dfi_freq_ratio);  in phy_gen2_msg_init()
917 	debug("msg_blk->phy_odt_impedance = 0x%x\n",  in phy_gen2_msg_init()
919 	debug("msg_blk->phy_drv_impedance = 0x%x\n",  in phy_gen2_msg_init()
921 	debug("msg_blk->bpznres_val = 0x%x\n", msg_blk->bpznres_val);  in phy_gen2_msg_init()
922 	debug("msg_blk->enabled_dqs = 0x%x\n", msg_blk->enabled_dqs);  in phy_gen2_msg_init()
923 	debug("msg_blk->acsm_odt_ctrl0 = 0x%x\n", msg_blk->acsm_odt_ctrl0);  in phy_gen2_msg_init()
924 	debug("msg_blk->acsm_odt_ctrl1 = 0x%x\n", msg_blk->acsm_odt_ctrl1);  in phy_gen2_msg_init()
925 	debug("msg_blk->acsm_odt_ctrl2 = 0x%x\n", msg_blk->acsm_odt_ctrl2);  in phy_gen2_msg_init()
926 	debug("msg_blk->acsm_odt_ctrl3 = 0x%x\n", msg_blk->acsm_odt_ctrl3);  in phy_gen2_msg_init()
990 		debug("rx2d_train_opt %d, tx2d_train_opt %d\n",  in phy_gen2_msg_init()
1161 	debug("pll_ctrl1 = 0x%x\n", phy_io_read16(phy, addr));  in prog_pll_ctrl()
1166 	debug("pll_test_mode = 0x%x\n", phy_io_read16(phy, addr));  in prog_pll_ctrl()
1171 	debug("pll_ctrl4 = 0x%x\n", phy_io_read16(phy, addr));  in prog_pll_ctrl()
1198 	debug("pll_ctrl2 = 0x%x\n", phy_io_read16(phy, addr));  in prog_pll_ctrl2()
1206 	debug("dll_lck_param = 0x%x\n", phy_io_read16(phy, addr));  in prog_dll_lck_param()
1214 	debug("dll_gain_ctl = 0x%x\n", phy_io_read16(phy, addr));  in prog_dll_gain_ctl()
1225 	debug("pll_pwrdn = 0x%x\n", phy_io_read16(phy, addr));  in prog_pll_pwr_dn()
1583 	debug("%s 0x%x\n", __func__, phy_io_read16(phy, addr));  in prog_acx4_anib_dis()
1887 		debug("Initialize PHY %d config\n", i);  in c_init_phy_config()
1897 		debug("SOC_SI_REV = %x\n", soc_info->svr_reg.bf.maj_ver);  in c_init_phy_config()
2041 			debug("%s Training completed\n", train2d ? "2D" : "1D");  in wait_fw_done()
2044 			debug("%s Training failure\n", train2d ? "2D" : "1D");  in wait_fw_done()
2047 			debug("End of initialization\n");  in wait_fw_done()
2051 			debug("End of fine write leveling\n");  in wait_fw_done()
2055 			debug("End of read enable training\n");  in wait_fw_done()
2059 			debug("End of read delay center optimization\n");  in wait_fw_done()
2063 			debug("End of write delay center optimization\n");  in wait_fw_done()
2067 			debug("End of 2D read delay/voltage center optimztn\n");  in wait_fw_done()
2071 			debug("End of 2D write delay/voltage center optmztn\n");  in wait_fw_done()
2079 			debug("End of max read latency training\n");  in wait_fw_done()
2083 			debug("End of read dq deskew training\n");  in wait_fw_done()
2087 			debug("End of LRDIMM Specific training, including:\n");  in wait_fw_done()
2088 			debug("/tDWL, MREP, MRD and MWD\n");  in wait_fw_done()
2092 			debug("End of CA training\n");  in wait_fw_done()
2096 			debug("End of MPR read delay center optimization\n");  in wait_fw_done()
2100 			debug("End of Write leveling coarse delay\n");  in wait_fw_done()
2104 			debug("Timed out\n");  in wait_fw_done()
2120 	debug("PHY_GEN2 FW: Unxpected mail = 0x%x\n", mail);  in wait_fw_done()
2136 		debug("Applying PLL optimal settings\n");  in g_exec_fw()
2224 	debug("Loaded Imaged id %d of size %x at address %lx\n",  in load_fw()
2257 	debug("Loaded Imaged id %d of size %x at address %lx\n",  in load_fw()
2501 	debug("frequency = %dMHz\n", input.basic.frequency);  in compute_ddr_phy()
2515 	debug("Vref_phy = %d percent\n", (input.vref * 100U) >> 7U);  in compute_ddr_phy()
2557 	debug("Initializing input adv data structure\n");  in compute_ddr_phy()
2560 	debug("Initializing message block\n");  in compute_ddr_phy()
2573 	debug("Warm boot flag value %0x\n", priv->warm_boot_flag);  in compute_ddr_phy()
2575 		debug("Restoring the Phy training data\n");  in compute_ddr_phy()
2597 		debug("Load 1D firmware\n");  in compute_ddr_phy()
2606 		debug("Execute firmware\n");  in compute_ddr_phy()
2627 			debug("Load 2D firmware\n");  in compute_ddr_phy()
2636 				debug("Execute 2D firmware\n");  in compute_ddr_phy()
2647 			debug("save the phy training data\n");  in compute_ddr_phy()
2662 		debug("Load PIE\n");  in compute_ddr_phy()