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Searched refs:Gclk (Results 1 – 13 of 13) sorted by relevance

/loramac-node-3.4.0/src/boards/mcu/saml21/hri/
Dhri_gclk_l21.h69 while (((Gclk *)hw)->SYNCBUSY.reg & reg) { in hri_gclk_wait_for_sync()
75 return ((Gclk *)hw)->SYNCBUSY.reg & reg; in hri_gclk_is_syncing()
82 ((Gclk *)hw)->CTRLA.reg |= GCLK_CTRLA_SWRST; in hri_gclk_set_CTRLA_SWRST_bit()
90 tmp = ((Gclk *)hw)->CTRLA.reg; in hri_gclk_get_CTRLA_SWRST_bit()
98 ((Gclk *)hw)->CTRLA.reg |= mask; in hri_gclk_set_CTRLA_reg()
105 tmp = ((Gclk *)hw)->CTRLA.reg; in hri_gclk_get_CTRLA_reg()
113 ((Gclk *)hw)->CTRLA.reg = data; in hri_gclk_write_CTRLA_reg()
120 ((Gclk *)hw)->CTRLA.reg &= ~mask; in hri_gclk_clear_CTRLA_reg()
127 ((Gclk *)hw)->CTRLA.reg ^= mask; in hri_gclk_toggle_CTRLA_reg()
133 return ((Gclk *)hw)->CTRLA.reg; in hri_gclk_read_CTRLA_reg()
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/loramac-node-3.4.0/src/boards/mcu/saml21/saml21b/include/component/
Dgclk.h243 } Gclk; typedef
/loramac-node-3.4.0/src/boards/mcu/saml21/saml21b/include/
Dsaml21e15b.h469 #define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */
Dsaml21e16b.h469 #define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */
Dsaml21e17b.h469 #define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */
Dsaml21e18b.h469 #define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */
Dsaml21g16b.h469 #define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */
Dsaml21g17b.h469 #define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */
Dsaml21g18b.h469 #define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */
Dsaml21j16b.h479 #define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */
Dsaml21j17b.h479 #define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */
Dsaml21j18b.h479 #define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */
Dsaml21j18bu.h479 #define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */