1 /** 2 * \file 3 * 4 * \brief Header file for SAML21J18BU 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAML21J18BU_ 30 #define _SAML21J18BU_ 31 32 /** 33 * \ingroup SAML21_definitions 34 * \addtogroup SAML21J18BU_definitions SAML21J18BU definitions 35 * This file defines all structures and symbols for SAML21J18BU: 36 * - registers and bitfields 37 * - peripheral base address 38 * - peripheral ID 39 * - PIO definitions 40 */ 41 /*@{*/ 42 43 #ifdef __cplusplus 44 extern "C" { 45 #endif 46 47 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 48 #include <stdint.h> 49 #ifndef __cplusplus 50 typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ 51 typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ 52 typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ 53 #else 54 typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ 55 typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ 56 typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ 57 #endif 58 typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ 59 typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ 60 typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ 61 typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ 62 typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ 63 typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ 64 #if !defined(_UL) 65 #define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ 66 #define _L(x) x ## L /**< C code: Long integer literal constant value */ 67 #define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ 68 #endif 69 #else 70 #if !defined(_UL) 71 #define _U(x) x /**< Assembler: Unsigned integer literal constant value */ 72 #define _L(x) x /**< Assembler: Long integer literal constant value */ 73 #define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ 74 #endif 75 #endif 76 77 /* ************************************************************************** */ 78 /** CMSIS DEFINITIONS FOR SAML21J18BU */ 79 /* ************************************************************************** */ 80 /** \defgroup SAML21J18BU_cmsis CMSIS Definitions */ 81 /*@{*/ 82 83 /** Interrupt Number Definition */ 84 typedef enum IRQn 85 { 86 /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ 87 NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ 88 HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ 89 SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ 90 PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ 91 SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ 92 /****** SAML21J18BU-specific Interrupt Numbers ***********************/ 93 SYSTEM_IRQn = 0, /**< 0 SAML21J18BU System Interrupts */ 94 WDT_IRQn = 1, /**< 1 SAML21J18BU Watchdog Timer (WDT) */ 95 RTC_IRQn = 2, /**< 2 SAML21J18BU Real-Time Counter (RTC) */ 96 EIC_IRQn = 3, /**< 3 SAML21J18BU External Interrupt Controller (EIC) */ 97 NVMCTRL_IRQn = 4, /**< 4 SAML21J18BU Non-Volatile Memory Controller (NVMCTRL) */ 98 DMAC_IRQn = 5, /**< 5 SAML21J18BU Direct Memory Access Controller (DMAC) */ 99 USB_IRQn = 6, /**< 6 SAML21J18BU Universal Serial Bus (USB) */ 100 EVSYS_IRQn = 7, /**< 7 SAML21J18BU Event System Interface (EVSYS) */ 101 SERCOM0_IRQn = 8, /**< 8 SAML21J18BU Serial Communication Interface 0 (SERCOM0) */ 102 SERCOM1_IRQn = 9, /**< 9 SAML21J18BU Serial Communication Interface 1 (SERCOM1) */ 103 SERCOM2_IRQn = 10, /**< 10 SAML21J18BU Serial Communication Interface 2 (SERCOM2) */ 104 SERCOM3_IRQn = 11, /**< 11 SAML21J18BU Serial Communication Interface 3 (SERCOM3) */ 105 SERCOM4_IRQn = 12, /**< 12 SAML21J18BU Serial Communication Interface 4 (SERCOM4) */ 106 SERCOM5_IRQn = 13, /**< 13 SAML21J18BU Serial Communication Interface 5 (SERCOM5) */ 107 TCC0_IRQn = 14, /**< 14 SAML21J18BU Timer Counter Control 0 (TCC0) */ 108 TCC1_IRQn = 15, /**< 15 SAML21J18BU Timer Counter Control 1 (TCC1) */ 109 TCC2_IRQn = 16, /**< 16 SAML21J18BU Timer Counter Control 2 (TCC2) */ 110 TC0_IRQn = 17, /**< 17 SAML21J18BU Basic Timer Counter 0 (TC0) */ 111 TC1_IRQn = 18, /**< 18 SAML21J18BU Basic Timer Counter 1 (TC1) */ 112 TC2_IRQn = 19, /**< 19 SAML21J18BU Basic Timer Counter 2 (TC2) */ 113 TC3_IRQn = 20, /**< 20 SAML21J18BU Basic Timer Counter 3 (TC3) */ 114 TC4_IRQn = 21, /**< 21 SAML21J18BU Basic Timer Counter 4 (TC4) */ 115 ADC_IRQn = 22, /**< 22 SAML21J18BU Analog Digital Converter (ADC) */ 116 AC_IRQn = 23, /**< 23 SAML21J18BU Analog Comparators (AC) */ 117 DAC_IRQn = 24, /**< 24 SAML21J18BU Digital-to-Analog Converter (DAC) */ 118 PTC_IRQn = 25, /**< 25 SAML21J18BU Peripheral Touch Controller (PTC) */ 119 AES_IRQn = 26, /**< 26 SAML21J18BU Advanced Encryption Standard (AES) */ 120 TRNG_IRQn = 27, /**< 27 SAML21J18BU True Random Generator (TRNG) */ 121 122 PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ 123 } IRQn_Type; 124 125 typedef struct _DeviceVectors 126 { 127 /* Stack pointer */ 128 void* pvStack; 129 130 /* Cortex-M handlers */ 131 void* pfnReset_Handler; 132 void* pfnNMI_Handler; 133 void* pfnHardFault_Handler; 134 void* pvReservedM12; 135 void* pvReservedM11; 136 void* pvReservedM10; 137 void* pvReservedM9; 138 void* pvReservedM8; 139 void* pvReservedM7; 140 void* pvReservedM6; 141 void* pfnSVC_Handler; 142 void* pvReservedM4; 143 void* pvReservedM3; 144 void* pfnPendSV_Handler; 145 void* pfnSysTick_Handler; 146 147 /* Peripheral handlers */ 148 void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ 149 void* pfnWDT_Handler; /* 1 Watchdog Timer */ 150 void* pfnRTC_Handler; /* 2 Real-Time Counter */ 151 void* pfnEIC_Handler; /* 3 External Interrupt Controller */ 152 void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ 153 void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ 154 void* pfnUSB_Handler; /* 6 Universal Serial Bus */ 155 void* pfnEVSYS_Handler; /* 7 Event System Interface */ 156 void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ 157 void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ 158 void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ 159 void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ 160 void* pfnSERCOM4_Handler; /* 12 Serial Communication Interface 4 */ 161 void* pfnSERCOM5_Handler; /* 13 Serial Communication Interface 5 */ 162 void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ 163 void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ 164 void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ 165 void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ 166 void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ 167 void* pfnTC2_Handler; /* 19 Basic Timer Counter 2 */ 168 void* pfnTC3_Handler; /* 20 Basic Timer Counter 3 */ 169 void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ 170 void* pfnADC_Handler; /* 22 Analog Digital Converter */ 171 void* pfnAC_Handler; /* 23 Analog Comparators */ 172 void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ 173 void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ 174 void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ 175 void* pfnTRNG_Handler; /* 27 True Random Generator */ 176 void* pvReserved28; 177 } DeviceVectors; 178 179 /* Cortex-M0+ processor handlers */ 180 void Reset_Handler ( void ); 181 void NMI_Handler ( void ); 182 void HardFault_Handler ( void ); 183 void SVC_Handler ( void ); 184 void PendSV_Handler ( void ); 185 void SysTick_Handler ( void ); 186 187 /* Peripherals handlers */ 188 void SYSTEM_Handler ( void ); 189 void WDT_Handler ( void ); 190 void RTC_Handler ( void ); 191 void EIC_Handler ( void ); 192 void NVMCTRL_Handler ( void ); 193 void DMAC_Handler ( void ); 194 void USB_Handler ( void ); 195 void EVSYS_Handler ( void ); 196 void SERCOM0_Handler ( void ); 197 void SERCOM1_Handler ( void ); 198 void SERCOM2_Handler ( void ); 199 void SERCOM3_Handler ( void ); 200 void SERCOM4_Handler ( void ); 201 void SERCOM5_Handler ( void ); 202 void TCC0_Handler ( void ); 203 void TCC1_Handler ( void ); 204 void TCC2_Handler ( void ); 205 void TC0_Handler ( void ); 206 void TC1_Handler ( void ); 207 void TC2_Handler ( void ); 208 void TC3_Handler ( void ); 209 void TC4_Handler ( void ); 210 void ADC_Handler ( void ); 211 void AC_Handler ( void ); 212 void DAC_Handler ( void ); 213 void PTC_Handler ( void ); 214 void AES_Handler ( void ); 215 void TRNG_Handler ( void ); 216 217 /* 218 * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals 219 */ 220 221 #define LITTLE_ENDIAN 1 222 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ 223 #define __MPU_PRESENT 0 /*!< MPU present or not */ 224 #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ 225 #define __VTOR_PRESENT 1 /*!< VTOR present or not */ 226 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 227 228 /** 229 * \brief CMSIS includes 230 */ 231 232 #include <core_cm0plus.h> 233 #if !defined DONT_USE_CMSIS_INIT 234 #include "system_saml21.h" 235 #endif /* DONT_USE_CMSIS_INIT */ 236 237 /*@}*/ 238 239 /* ************************************************************************** */ 240 /** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21J18BU */ 241 /* ************************************************************************** */ 242 /** \defgroup SAML21J18BU_api Peripheral Software API */ 243 /*@{*/ 244 245 #include "component/ac.h" 246 #include "component/adc.h" 247 #include "component/aes.h" 248 #include "component/ccl.h" 249 #include "component/dac.h" 250 #include "component/dmac.h" 251 #include "component/dsu.h" 252 #include "component/eic.h" 253 #include "component/evsys.h" 254 #include "component/gclk.h" 255 #include "component/mclk.h" 256 #include "component/mtb.h" 257 #include "component/nvmctrl.h" 258 #include "component/opamp.h" 259 #include "component/oscctrl.h" 260 #include "component/osc32kctrl.h" 261 #include "component/pac.h" 262 #include "component/pm.h" 263 #include "component/port.h" 264 #include "component/rstc.h" 265 #include "component/rtc.h" 266 #include "component/sercom.h" 267 #include "component/supc.h" 268 #include "component/tal.h" 269 #include "component/tc.h" 270 #include "component/tcc.h" 271 #include "component/trng.h" 272 #include "component/usb.h" 273 #include "component/wdt.h" 274 /*@}*/ 275 276 /* ************************************************************************** */ 277 /** REGISTERS ACCESS DEFINITIONS FOR SAML21J18BU */ 278 /* ************************************************************************** */ 279 /** \defgroup SAML21J18BU_reg Registers Access Definitions */ 280 /*@{*/ 281 282 #include "instance/ac.h" 283 #include "instance/adc.h" 284 #include "instance/aes.h" 285 #include "instance/ccl.h" 286 #include "instance/dac.h" 287 #include "instance/dmac.h" 288 #include "instance/dsu.h" 289 #include "instance/eic.h" 290 #include "instance/evsys.h" 291 #include "instance/gclk.h" 292 #include "instance/mclk.h" 293 #include "instance/mtb.h" 294 #include "instance/nvmctrl.h" 295 #include "instance/opamp.h" 296 #include "instance/oscctrl.h" 297 #include "instance/osc32kctrl.h" 298 #include "instance/pac.h" 299 #include "instance/pm.h" 300 #include "instance/port.h" 301 #include "instance/rstc.h" 302 #include "instance/rtc.h" 303 #include "instance/sercom0.h" 304 #include "instance/sercom1.h" 305 #include "instance/sercom2.h" 306 #include "instance/sercom3.h" 307 #include "instance/sercom4.h" 308 #include "instance/sercom5.h" 309 #include "instance/supc.h" 310 #include "instance/tal.h" 311 #include "instance/tc0.h" 312 #include "instance/tc1.h" 313 #include "instance/tc2.h" 314 #include "instance/tc3.h" 315 #include "instance/tc4.h" 316 #include "instance/tcc0.h" 317 #include "instance/tcc1.h" 318 #include "instance/tcc2.h" 319 #include "instance/trng.h" 320 #include "instance/usb.h" 321 #include "instance/wdt.h" 322 /*@}*/ 323 324 /* ************************************************************************** */ 325 /** PERIPHERAL ID DEFINITIONS FOR SAML21J18BU */ 326 /* ************************************************************************** */ 327 /** \defgroup SAML21J18BU_id Peripheral Ids Definitions */ 328 /*@{*/ 329 330 // Peripheral instances on HPB0 bridge 331 #define ID_PM 0 /**< \brief Power Manager (PM) */ 332 #define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ 333 #define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ 334 #define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ 335 #define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ 336 #define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ 337 #define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ 338 #define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ 339 #define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ 340 #define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ 341 #define ID_PORT 10 /**< \brief Port Module (PORT) */ 342 #define ID_TAL 11 /**< \brief Trigger Allocator (TAL) */ 343 344 // Peripheral instances on HPB1 bridge 345 #define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ 346 #define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ 347 #define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ 348 #define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ 349 350 // Peripheral instances on HPB2 bridge 351 #define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ 352 #define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ 353 #define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ 354 #define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ 355 #define ID_SERCOM4 68 /**< \brief Serial Communication Interface 4 (SERCOM4) */ 356 #define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ 357 #define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ 358 #define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ 359 #define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ 360 #define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ 361 #define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ 362 #define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ 363 #define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ 364 #define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ 365 #define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ 366 367 // Peripheral instances on HPB3 bridge 368 #define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ 369 #define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ 370 #define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ 371 #define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ 372 #define ID_AC 100 /**< \brief Analog Comparators (AC) */ 373 #define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ 374 #define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ 375 #define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ 376 377 // Peripheral instances on HPB4 bridge 378 #define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ 379 #define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ 380 381 #define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ 382 /*@}*/ 383 384 /* ************************************************************************** */ 385 /** BASE ADDRESS DEFINITIONS FOR SAML21J18BU */ 386 /* ************************************************************************** */ 387 /** \defgroup SAML21J18BU_base Peripheral Base Address Definitions */ 388 /*@{*/ 389 390 #if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) 391 #define AC (0x43001000) /**< \brief (AC) APB Base Address */ 392 #define ADC (0x43000C00) /**< \brief (ADC) APB Base Address */ 393 #define AES (0x42003400) /**< \brief (AES) APB Base Address */ 394 #define CCL (0x43001C00) /**< \brief (CCL) APB Base Address */ 395 #define DAC (0x42003000) /**< \brief (DAC) APB Base Address */ 396 #define DMAC (0x44000400) /**< \brief (DMAC) APB Base Address */ 397 #define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ 398 #define EIC (0x40002400) /**< \brief (EIC) APB Base Address */ 399 #define EVSYS (0x43000000) /**< \brief (EVSYS) APB Base Address */ 400 #define GCLK (0x40001800) /**< \brief (GCLK) APB Base Address */ 401 #define MCLK (0x40000400) /**< \brief (MCLK) APB Base Address */ 402 #define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ 403 #define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ 404 #define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ 405 #define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ 406 #define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ 407 #define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ 408 #define NVMCTRL_OTP3 (0x00806010) /**< \brief (NVMCTRL) OTP3 Base Address */ 409 #define NVMCTRL_OTP4 (0x00806018) /**< \brief (NVMCTRL) OTP4 Base Address */ 410 #define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ 411 #define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ 412 #define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ 413 #define OPAMP (0x43001800) /**< \brief (OPAMP) APB Base Address */ 414 #define OSCCTRL (0x40000C00) /**< \brief (OSCCTRL) APB Base Address */ 415 #define OSC32KCTRL (0x40001000) /**< \brief (OSC32KCTRL) APB Base Address */ 416 #define PAC (0x44000000) /**< \brief (PAC) APB Base Address */ 417 #define PM (0x40000000) /**< \brief (PM) APB Base Address */ 418 #define PORT (0x40002800) /**< \brief (PORT) APB Base Address */ 419 #define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ 420 #define PTC (0x43001400) /**< \brief (PTC) APB Base Address */ 421 #define RSTC (0x40000800) /**< \brief (RSTC) APB Base Address */ 422 #define RTC (0x40002000) /**< \brief (RTC) APB Base Address */ 423 #define SERCOM0 (0x42000000) /**< \brief (SERCOM0) APB Base Address */ 424 #define SERCOM1 (0x42000400) /**< \brief (SERCOM1) APB Base Address */ 425 #define SERCOM2 (0x42000800) /**< \brief (SERCOM2) APB Base Address */ 426 #define SERCOM3 (0x42000C00) /**< \brief (SERCOM3) APB Base Address */ 427 #define SERCOM4 (0x42001000) /**< \brief (SERCOM4) APB Base Address */ 428 #define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ 429 #define SUPC (0x40001400) /**< \brief (SUPC) APB Base Address */ 430 #define TAL (0x40002C00) /**< \brief (TAL) APB Base Address */ 431 #define TC0 (0x42002000) /**< \brief (TC0) APB Base Address */ 432 #define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ 433 #define TC2 (0x42002800) /**< \brief (TC2) APB Base Address */ 434 #define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ 435 #define TC4 (0x43000800) /**< \brief (TC4) APB Base Address */ 436 #define TCC0 (0x42001400) /**< \brief (TCC0) APB Base Address */ 437 #define TCC1 (0x42001800) /**< \brief (TCC1) APB Base Address */ 438 #define TCC2 (0x42001C00) /**< \brief (TCC2) APB Base Address */ 439 #define TRNG (0x42003800) /**< \brief (TRNG) APB Base Address */ 440 #define USB (0x41000000) /**< \brief (USB) APB Base Address */ 441 #define WDT (0x40001C00) /**< \brief (WDT) APB Base Address */ 442 #else 443 #define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ 444 #define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ 445 #define AC_INSTS { AC } /**< \brief (AC) Instances List */ 446 447 #define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ 448 #define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ 449 #define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ 450 451 #define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ 452 #define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ 453 #define AES_INSTS { AES } /**< \brief (AES) Instances List */ 454 455 #define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ 456 #define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ 457 #define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ 458 459 #define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ 460 #define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ 461 #define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ 462 463 #define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ 464 #define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ 465 #define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ 466 467 #define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ 468 #define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ 469 #define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ 470 471 #define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ 472 #define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ 473 #define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ 474 475 #define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ 476 #define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ 477 #define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ 478 479 #define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ 480 #define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ 481 #define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ 482 483 #define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ 484 #define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ 485 #define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ 486 487 #define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ 488 #define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ 489 #define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ 490 491 #define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ 492 #define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ 493 #define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ 494 #define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ 495 #define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ 496 #define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ 497 #define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ 498 #define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ 499 #define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ 500 #define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ 501 #define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ 502 #define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ 503 504 #define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ 505 #define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ 506 #define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ 507 508 #define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ 509 #define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ 510 #define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ 511 512 #define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ 513 #define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ 514 #define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ 515 516 #define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ 517 #define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ 518 #define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ 519 520 #define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ 521 #define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ 522 #define PM_INSTS { PM } /**< \brief (PM) Instances List */ 523 524 #define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ 525 #define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ 526 #define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ 527 #define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ 528 #define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ 529 #define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ 530 531 #define PTC ((void *)0x43001400UL) /**< \brief (PTC) APB Base Address */ 532 #define PTC_GCLK_ID 33 533 #define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ 534 #define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ 535 536 #define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ 537 #define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ 538 #define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ 539 540 #define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ 541 #define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ 542 #define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ 543 544 #define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ 545 #define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ 546 #define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ 547 #define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ 548 #define SERCOM4 ((Sercom *)0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ 549 #define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ 550 #define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ 551 #define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ 552 553 #define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ 554 #define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ 555 #define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ 556 557 #define TAL ((Tal *)0x40002C00UL) /**< \brief (TAL) APB Base Address */ 558 #define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ 559 #define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ 560 561 #define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ 562 #define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ 563 #define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ 564 #define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ 565 #define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ 566 #define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ 567 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */ 568 569 #define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ 570 #define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ 571 #define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ 572 #define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ 573 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ 574 575 #define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ 576 #define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ 577 #define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ 578 579 #define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ 580 #define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ 581 #define USB_INSTS { USB } /**< \brief (USB) Instances List */ 582 583 #define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ 584 #define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ 585 #define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ 586 587 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 588 /*@}*/ 589 590 /* ************************************************************************** */ 591 /** PORT DEFINITIONS FOR SAML21J18BU */ 592 /* ************************************************************************** */ 593 /** \defgroup SAML21J18BU_port PORT Definitions */ 594 /*@{*/ 595 596 #include "pio/saml21j18bu.h" 597 /*@}*/ 598 599 /* ************************************************************************** */ 600 /** MEMORY MAPPING DEFINITIONS FOR SAML21J18BU */ 601 /* ************************************************************************** */ 602 603 #define FLASH_SIZE _UL(0x00040000) /* 256 kB */ 604 #define FLASH_PAGE_SIZE 64 605 #define FLASH_NB_OF_PAGES 4096 606 #define FLASH_USER_PAGE_SIZE 64 607 #define HSRAM_SIZE _UL(0x00008000) /* 32 kB */ 608 #define LPRAM_SIZE _UL(0x00002000) /* 8 kB */ 609 610 #define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ 611 #define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ 612 #define HSRAM_ADDR _UL(0x20000000) /**< HSRAM base address */ 613 #define LPRAM_ADDR _UL(0x30000000) /**< LPRAM base address */ 614 #define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ 615 #define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ 616 #define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ 617 #define HPB3_ADDR _UL(0x43000000) /**< HPB3 base address */ 618 #define HPB4_ADDR _UL(0x44000000) /**< HPB4 base address */ 619 #define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ 620 621 #define DSU_DID_RESETVALUE _UL(0x1081020F) 622 #define NVMCTRL_RWW_EEPROM_SIZE _UL(0x00002000) /* 8 kB */ 623 #define PORT_GROUPS 2 624 #define USB_HOST_IMPLEMENTED 1 625 626 /* ************************************************************************** */ 627 /** ELECTRICAL DEFINITIONS FOR SAML21J18BU */ 628 /* ************************************************************************** */ 629 630 631 #ifdef __cplusplus 632 } 633 #endif 634 635 /*@}*/ 636 637 #endif /* SAML21J18BU_H */ 638
