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Searched refs:XSHAL_RAM_AVAIL_VADDR (Results 1 – 11 of 11) sorted by relevance

/hal_xtensa-3.5.0/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dsystem.h92 #define XSHAL_RAM_AVAIL_VADDR 0x20000000 macro
/hal_xtensa-3.5.0/zephyr/soc/mt8195_adsp/xtensa/config/
Dsystem.h92 #define XSHAL_RAM_AVAIL_VADDR 0x40000920 macro
/hal_xtensa-3.5.0/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dsystem.h98 #define XSHAL_RAM_AVAIL_VADDR 0xA0000000 macro
/hal_xtensa-3.5.0/zephyr/soc/dc233c/xtensa/config/
Dsystem.h101 #define XSHAL_RAM_AVAIL_VADDR 0x00002500 macro
/hal_xtensa-3.5.0/zephyr/soc/nxp_imx8/xtensa/config/
Dsystem.h108 #define XSHAL_RAM_AVAIL_VADDR 0x80700000 macro
/hal_xtensa-3.5.0/zephyr/soc/sample_controller/xtensa/config/
Dsystem.h108 #define XSHAL_RAM_AVAIL_VADDR 0x60000000 macro
/hal_xtensa-3.5.0/zephyr/soc/mimx8ml8/xtensa/config/
Dsystem.h108 #define XSHAL_RAM_AVAIL_VADDR 0x3B700000 macro
/hal_xtensa-3.5.0/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dsystem.h112 #define XSHAL_RAM_AVAIL_VADDR 0x80000000 macro
/hal_xtensa-3.5.0/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dsystem.h112 #define XSHAL_RAM_AVAIL_VADDR 0x80000000 macro
/hal_xtensa-3.5.0/zephyr/soc/intel_icl_adsp/xtensa/config/
Dsystem.h112 #define XSHAL_RAM_AVAIL_VADDR 0x80000000 macro
/hal_xtensa-3.5.0/zephyr/soc/intel_apl_adsp/xtensa/config/
Dsystem.h112 #define XSHAL_RAM_AVAIL_VADDR 0x80000000 macro