1 /* 2 * xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration 3 * 4 * NOTE: The location and contents of this file are highly subject to change. 5 * 6 * Source for configuration-independent binaries (which link in a 7 * configuration-specific HAL library) must NEVER include this file. 8 * The HAL itself has historically included this file in some instances, 9 * but this is not appropriate either, because the HAL is meant to be 10 * core-specific but system independent. 11 */ 12 13 /* Copyright (c) 2000-2007 Tensilica Inc. 14 15 Permission is hereby granted, free of charge, to any person obtaining 16 a copy of this software and associated documentation files (the 17 "Software"), to deal in the Software without restriction, including 18 without limitation the rights to use, copy, modify, merge, publish, 19 distribute, sublicense, and/or sell copies of the Software, and to 20 permit persons to whom the Software is furnished to do so, subject to 21 the following conditions: 22 23 The above copyright notice and this permission notice shall be included 24 in all copies or substantial portions of the Software. 25 26 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 27 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 28 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 29 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 30 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 31 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 32 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 33 34 35 #ifndef XTENSA_CONFIG_SYSTEM_H 36 #define XTENSA_CONFIG_SYSTEM_H 37 38 /*#include <xtensa/hal.h>*/ 39 40 41 42 /*---------------------------------------------------------------------- 43 CONFIGURED SOFTWARE OPTIONS 44 ----------------------------------------------------------------------*/ 45 46 #define XSHAL_USE_ABSOLUTE_LITERALS 0 /* (sw-only option, whether software uses absolute literals) */ 47 48 #define XSHAL_ABI XTHAL_ABI_WINDOWED /* (sw-only option, selected ABI) */ 49 /* The above maps to one of the following constants: */ 50 #define XTHAL_ABI_WINDOWED 0 51 #define XTHAL_ABI_CALL0 1 52 /* Alternatives: */ 53 /*#define XSHAL_WINDOWED_ABI 1*/ /* set if windowed ABI selected */ 54 /*#define XSHAL_CALL0_ABI 0*/ /* set if call0 ABI selected */ 55 56 #define XSHAL_CLIB XTHAL_CLIB_NEWLIB /* (sw-only option, selected C library) */ 57 /* The above maps to one of the following constants: */ 58 #define XTHAL_CLIB_NEWLIB 0 59 #define XTHAL_CLIB_UCLIBC 1 60 /* Alternatives: */ 61 /*#define XSHAL_NEWLIB 1*/ /* set if newlib C library selected */ 62 /*#define XSHAL_UCLIBC 0*/ /* set if uCLibC C library selected */ 63 64 #define XSHAL_USE_FLOATING_POINT 1 65 66 /*---------------------------------------------------------------------- 67 DEVICE ADDRESSES 68 ----------------------------------------------------------------------*/ 69 70 /* 71 * Strange place to find these, but the configuration GUI 72 * allows moving these around to account for various core 73 * configurations. Specific boards (and their BSP software) 74 * will have specific meanings for these components. 75 */ 76 77 /* I/O Block areas: */ 78 #define XSHAL_IOBLOCK_CACHED_VADDR 0x30000000 79 #define XSHAL_IOBLOCK_CACHED_PADDR 0x30000000 80 #define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000 81 82 #define XSHAL_IOBLOCK_BYPASS_VADDR 0xF0000000 83 #define XSHAL_IOBLOCK_BYPASS_PADDR 0xF0000000 84 #define XSHAL_IOBLOCK_BYPASS_SIZE 0x0E000000 85 86 /* System ROM: */ 87 #define XSHAL_ROM_VADDR 0xEE000000 88 #define XSHAL_ROM_PADDR 0xFE000000 89 #define XSHAL_ROM_SIZE 0x01000000 90 /* Largest available area (free of vectors): */ 91 #define XSHAL_ROM_AVAIL_VADDR 0xFE000300 92 #define XSHAL_ROM_AVAIL_VSIZE 0x00FFFD00 93 94 /* System RAM: */ 95 #define XSHAL_RAM_VADDR 0xD0000000 96 #define XSHAL_RAM_PADDR 0x00000000 97 #define XSHAL_RAM_VSIZE 0x04000000 98 #define XSHAL_RAM_PSIZE 0x04000000 99 #define XSHAL_RAM_SIZE XSHAL_RAM_PSIZE 100 /* Largest available area (free of vectors): */ 101 #define XSHAL_RAM_AVAIL_VADDR 0x00002500 102 #define XSHAL_RAM_AVAIL_VSIZE 0x03FFDB00 103 104 /* 105 * Shadow system RAM (same device as system RAM, at different address). 106 * (Emulation boards need this for the SONIC Ethernet driver 107 * when data caches are configured for writeback mode.) 108 * NOTE: on full MMU configs, this points to the BYPASS virtual address 109 * of system RAM, ie. is the same as XSHAL_RAM_* except that virtual 110 * addresses are viewed through the BYPASS static map rather than 111 * the CACHED static map. 112 */ 113 #define XSHAL_RAM_BYPASS_VADDR 0x40000000 114 #define XSHAL_RAM_BYPASS_PADDR 0x40000000 115 #define XSHAL_RAM_BYPASS_PSIZE 0x04000000 116 117 /* Alternate system RAM (different device than system RAM): */ 118 /*#define XSHAL_ALTRAM_[VP]ADDR ...not configured...*/ 119 /*#define XSHAL_ALTRAM_SIZE ...not configured...*/ 120 121 /* Some available location in which to place devices in a simulation (eg. XTMP): */ 122 #define XSHAL_SIMIO_CACHED_VADDR 0xA0000000 123 #define XSHAL_SIMIO_BYPASS_VADDR 0xA0000000 124 #define XSHAL_SIMIO_PADDR 0xA0000000 125 #define XSHAL_SIMIO_SIZE 0x20000000 126 127 128 /*---------------------------------------------------------------------- 129 * DEVICE-ADDRESS DEPENDENT... 130 * 131 * Values written to CACHEATTR special register (or its equivalent) 132 * to enable and disable caches in various modes. 133 *----------------------------------------------------------------------*/ 134 135 /*---------------------------------------------------------------------- 136 BACKWARD COMPATIBILITY ... 137 ----------------------------------------------------------------------*/ 138 139 /* 140 * NOTE: the following two macros are DEPRECATED. Use the latter 141 * board-specific macros instead, which are specially tuned for the 142 * particular target environments' memory maps. 143 */ 144 #define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */ 145 #define XSHAL_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT /* default setting to enable caches (no writeback!) */ 146 147 /*---------------------------------------------------------------------- 148 GENERIC 149 ----------------------------------------------------------------------*/ 150 151 /* For the following, a 512MB region is used if it contains a system (PIF) RAM, 152 * system (PIF) ROM, local memory, or XLMI. */ 153 154 /* These set any unused 512MB region to cache-BYPASS attribute: */ 155 #define XSHAL_ALLVALID_CACHEATTR_WRITEBACK 0x77333333 /* enable caches in write-back mode */ 156 #define XSHAL_ALLVALID_CACHEATTR_WRITEALLOC 0xBB333333 /* enable caches in write-allocate mode */ 157 #define XSHAL_ALLVALID_CACHEATTR_WRITETHRU 0xBB333333 /* enable caches in write-through mode */ 158 #define XSHAL_ALLVALID_CACHEATTR_BYPASS 0x33333333 /* disable caches in bypass mode */ 159 #define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK /* default setting to enable caches */ 160 161 /* These set any unused 512MB region to ILLEGAL attribute: */ 162 #define XSHAL_STRICT_CACHEATTR_WRITEBACK 0x77CCCCCC /* enable caches in write-back mode */ 163 #define XSHAL_STRICT_CACHEATTR_WRITEALLOC 0xBBCCCCCC /* enable caches in write-allocate mode */ 164 #define XSHAL_STRICT_CACHEATTR_WRITETHRU 0xBBCCCCCC /* enable caches in write-through mode */ 165 #define XSHAL_STRICT_CACHEATTR_BYPASS 0x33CCCCCC /* disable caches in bypass mode */ 166 #define XSHAL_STRICT_CACHEATTR_DEFAULT XSHAL_STRICT_CACHEATTR_WRITEBACK /* default setting to enable caches */ 167 168 /* These set the first 512MB, if unused, to ILLEGAL attribute to help catch 169 * NULL-pointer dereference bugs; all other unused 512MB regions are set 170 * to cache-BYPASS attribute: */ 171 #define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x7733333C /* enable caches in write-back mode */ 172 #define XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC 0xBB33333C /* enable caches in write-allocate mode */ 173 #define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU 0xBB33333C /* enable caches in write-through mode */ 174 #define XSHAL_TRAPNULL_CACHEATTR_BYPASS 0x3333333C /* disable caches in bypass mode */ 175 #define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to enable caches */ 176 177 /*---------------------------------------------------------------------- 178 ISS (Instruction Set Simulator) SPECIFIC ... 179 ----------------------------------------------------------------------*/ 180 181 /* For now, ISS defaults to the TRAPNULL settings: */ 182 #define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 183 #define XSHAL_ISS_CACHEATTR_WRITEALLOC XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC 184 #define XSHAL_ISS_CACHEATTR_WRITETHRU XSHAL_TRAPNULL_CACHEATTR_WRITETHRU 185 #define XSHAL_ISS_CACHEATTR_BYPASS XSHAL_TRAPNULL_CACHEATTR_BYPASS 186 #define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 187 188 #define XSHAL_ISS_PIPE_REGIONS 0 189 #define XSHAL_ISS_SDRAM_REGIONS 0 190 191 192 /*---------------------------------------------------------------------- 193 XT2000 BOARD SPECIFIC ... 194 ----------------------------------------------------------------------*/ 195 196 /* For the following, a 512MB region is used if it contains any system RAM, 197 * system ROM, local memory, XLMI, or other XT2000 board device or memory. 198 * Regions containing devices are forced to cache-BYPASS mode regardless 199 * of whether the macro is _WRITEBACK vs. _BYPASS etc. */ 200 201 /* These set any 512MB region unused on the XT2000 to ILLEGAL attribute: */ 202 #define XSHAL_XT2000_CACHEATTR_WRITEBACK 0x37CCC37C /* enable caches in write-back mode */ 203 #define XSHAL_XT2000_CACHEATTR_WRITEALLOC 0x3BCCC3BC /* enable caches in write-allocate mode */ 204 #define XSHAL_XT2000_CACHEATTR_WRITETHRU 0x3BCCC3BC /* enable caches in write-through mode */ 205 #define XSHAL_XT2000_CACHEATTR_BYPASS 0x33CCC33C /* disable caches in bypass mode */ 206 #define XSHAL_XT2000_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_WRITEBACK /* default setting to enable caches */ 207 208 #define XSHAL_XT2000_PIPE_REGIONS 0x00000000 /* BusInt pipeline regions */ 209 #define XSHAL_XT2000_SDRAM_REGIONS 0x00000011 /* BusInt SDRAM regions */ 210 211 212 /*---------------------------------------------------------------------- 213 VECTOR INFO AND SIZES 214 ----------------------------------------------------------------------*/ 215 216 #define XSHAL_VECTORS_PACKED 0 217 #define XSHAL_STATIC_VECTOR_SELECT 0 218 #define XSHAL_RESET_VECTOR_VADDR 0xFE000000 219 #define XSHAL_RESET_VECTOR_PADDR 0xFE000000 220 221 /* 222 * Sizes allocated to vectors by the system (memory map) configuration. 223 * These sizes are constrained by core configuration (eg. one vector's 224 * code cannot overflow into another vector) but are dependent on the 225 * system or board (or LSP) memory map configuration. 226 * 227 * Whether or not each vector happens to be in a system ROM is also 228 * a system configuration matter, sometimes useful, included here also: 229 */ 230 #define XSHAL_RESET_VECTOR_SIZE 0x00000300 231 #define XSHAL_RESET_VECTOR_ISROM 1 232 #define XSHAL_USER_VECTOR_SIZE 0x00000038 233 #define XSHAL_USER_VECTOR_ISROM 0 234 #define XSHAL_PROGRAMEXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */ 235 #define XSHAL_USEREXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */ 236 #define XSHAL_KERNEL_VECTOR_SIZE 0x00000038 237 #define XSHAL_KERNEL_VECTOR_ISROM 0 238 #define XSHAL_STACKEDEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */ 239 #define XSHAL_KERNELEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */ 240 #define XSHAL_DOUBLEEXC_VECTOR_SIZE 0x00000140 241 #define XSHAL_DOUBLEEXC_VECTOR_ISROM 0 242 #define XSHAL_WINDOW_VECTORS_SIZE 0x00000178 243 #define XSHAL_WINDOW_VECTORS_ISROM 0 244 #define XSHAL_INTLEVEL2_VECTOR_SIZE 0x00000038 245 #define XSHAL_INTLEVEL2_VECTOR_ISROM 0 246 #define XSHAL_INTLEVEL3_VECTOR_SIZE 0x00000038 247 #define XSHAL_INTLEVEL3_VECTOR_ISROM 0 248 #define XSHAL_INTLEVEL4_VECTOR_SIZE 0x00000038 249 #define XSHAL_INTLEVEL4_VECTOR_ISROM 0 250 #define XSHAL_INTLEVEL5_VECTOR_SIZE 0x00000038 251 #define XSHAL_INTLEVEL5_VECTOR_ISROM 0 252 #define XSHAL_INTLEVEL6_VECTOR_SIZE 0x00000038 253 #define XSHAL_INTLEVEL6_VECTOR_ISROM 0 254 #define XSHAL_DEBUG_VECTOR_SIZE XSHAL_INTLEVEL6_VECTOR_SIZE 255 #define XSHAL_DEBUG_VECTOR_ISROM XSHAL_INTLEVEL6_VECTOR_ISROM 256 #define XSHAL_NMI_VECTOR_SIZE 0x00000038 257 #define XSHAL_NMI_VECTOR_ISROM 0 258 #define XSHAL_INTLEVEL7_VECTOR_SIZE XSHAL_NMI_VECTOR_SIZE 259 260 261 #endif /*XTENSA_CONFIG_SYSTEM_H*/ 262 263
