1 /* 2 * xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration 3 * 4 * NOTE: The location and contents of this file are highly subject to change. 5 * 6 * Source for configuration-independent binaries (which link in a 7 * configuration-specific HAL library) must NEVER include this file. 8 * The HAL itself has historically included this file in some instances, 9 * but this is not appropriate either, because the HAL is meant to be 10 * core-specific but system independent. 11 */ 12 13 /* Copyright (c) 2000-2010 Tensilica Inc. 14 15 Permission is hereby granted, free of charge, to any person obtaining 16 a copy of this software and associated documentation files (the 17 "Software"), to deal in the Software without restriction, including 18 without limitation the rights to use, copy, modify, merge, publish, 19 distribute, sublicense, and/or sell copies of the Software, and to 20 permit persons to whom the Software is furnished to do so, subject to 21 the following conditions: 22 23 The above copyright notice and this permission notice shall be included 24 in all copies or substantial portions of the Software. 25 26 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 27 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 28 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 29 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 30 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 31 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 32 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 33 34 35 #ifndef XTENSA_CONFIG_SYSTEM_H 36 #define XTENSA_CONFIG_SYSTEM_H 37 38 39 /*---------------------------------------------------------------------- 40 CONFIGURED SOFTWARE OPTIONS 41 ----------------------------------------------------------------------*/ 42 43 #define XSHAL_USE_ABSOLUTE_LITERALS 0 /* (sw-only option, whether software uses absolute literals) */ 44 #define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */ 45 46 #define XSHAL_ABI XTHAL_ABI_WINDOWED /* (sw-only option, selected ABI) */ 47 /* The above maps to one of the following constants: */ 48 #define XTHAL_ABI_WINDOWED 0 49 #define XTHAL_ABI_CALL0 1 50 51 #define XSHAL_CLIB XTHAL_CLIB_NEWLIB /* (sw-only option, selected C library) */ 52 /* The above maps to one of the following constants: */ 53 #define XTHAL_CLIB_NEWLIB 0 54 #define XTHAL_CLIB_UCLIBC 1 55 #define XTHAL_CLIB_XCLIB 2 56 57 #define XSHAL_USE_FLOATING_POINT 1 58 59 #define XSHAL_FLOATING_POINT_ABI 1 60 61 /* SW workarounds enabled for HW errata: */ 62 63 /*---------------------------------------------------------------------- 64 DEVICE ADDRESSES 65 ----------------------------------------------------------------------*/ 66 67 /* 68 * Strange place to find these, but the configuration GUI 69 * allows moving these around to account for various core 70 * configurations. Specific boards (and their BSP software) 71 * will have specific meanings for these components. 72 */ 73 74 /* I/O Block areas: */ 75 #define XSHAL_IOBLOCK_CACHED_VADDR 0x70000000 76 #define XSHAL_IOBLOCK_CACHED_PADDR 0x70000000 77 #define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000 78 79 #define XSHAL_IOBLOCK_BYPASS_VADDR 0x90000000 80 #define XSHAL_IOBLOCK_BYPASS_PADDR 0x90000000 81 #define XSHAL_IOBLOCK_BYPASS_SIZE 0x0E000000 82 83 /* System ROM: */ 84 85 /* System RAM: */ 86 #define XSHAL_RAM_VADDR 0x20000000 87 #define XSHAL_RAM_PADDR 0x20000000 88 #define XSHAL_RAM_VSIZE 0x00500000 89 #define XSHAL_RAM_PSIZE 0x00500000 90 #define XSHAL_RAM_SIZE XSHAL_RAM_PSIZE 91 /* Largest available area (free of vectors): */ 92 #define XSHAL_RAM_AVAIL_VADDR 0x20000000 93 #define XSHAL_RAM_AVAIL_VSIZE 0x00500000 94 95 /* 96 * Shadow system RAM (same device as system RAM, at different address). 97 * (Emulation boards need this for the SONIC Ethernet driver 98 * when data caches are configured for writeback mode.) 99 * NOTE: on full MMU configs, this points to the BYPASS virtual address 100 * of system RAM, ie. is the same as XSHAL_RAM_* except that virtual 101 * addresses are viewed through the BYPASS static map rather than 102 * the CACHED static map. 103 */ 104 #define XSHAL_RAM_BYPASS_VADDR 0x40000000 105 #define XSHAL_RAM_BYPASS_PADDR 0x40000000 106 #define XSHAL_RAM_BYPASS_PSIZE 0x00500000 107 108 /* Alternate system RAM (different device than system RAM): */ 109 110 /* Some available location in which to place devices in a simulation (eg. XTMP): */ 111 #define XSHAL_SIMIO_CACHED_VADDR 0xC0000000 112 #define XSHAL_SIMIO_BYPASS_VADDR 0xC0000000 113 #define XSHAL_SIMIO_PADDR 0xC0000000 114 #define XSHAL_SIMIO_SIZE 0x20000000 115 116 117 /*---------------------------------------------------------------------- 118 * For use by reference testbench exit and diagnostic routines. 119 */ 120 #define XSHAL_MAGIC_EXIT 0x60000000 121 #define XSHAL_STL_INFO_LOCATION 0x9ffffffc 122 123 /*---------------------------------------------------------------------- 124 * DEVICE-ADDRESS DEPENDENT... 125 * 126 * Values written to CACHEATTR special register (or its equivalent) 127 * to enable and disable caches in various modes. 128 *----------------------------------------------------------------------*/ 129 130 /*---------------------------------------------------------------------- 131 BACKWARD COMPATIBILITY ... 132 ----------------------------------------------------------------------*/ 133 134 /* 135 * NOTE: the following two macros are DEPRECATED. Use the latter 136 * board-specific macros instead, which are specially tuned for the 137 * particular target environments' memory maps. 138 */ 139 #define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */ 140 #define XSHAL_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT /* default setting to enable caches (no writeback!) */ 141 142 /*---------------------------------------------------------------------- 143 GENERIC 144 ----------------------------------------------------------------------*/ 145 146 /* For the following, a 512MB region is used if it contains a system (PIF) RAM, 147 * system (PIF) ROM, local memory, or XLMI. */ 148 149 /* These set any unused 512MB region to cache-BYPASS attribute: */ 150 #define XSHAL_ALLVALID_CACHEATTR_WRITEBACK 0x22222211 /* enable caches in write-back mode */ 151 #define XSHAL_ALLVALID_CACHEATTR_WRITEALLOC 0x22222211 /* enable caches in write-allocate mode */ 152 #define XSHAL_ALLVALID_CACHEATTR_WRITETHRU 0x22222211 /* enable caches in write-through mode */ 153 #define XSHAL_ALLVALID_CACHEATTR_BYPASS 0x22222222 /* disable caches in bypass mode */ 154 #define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK /* default setting to enable caches */ 155 156 /* These set any unused 512MB region to ILLEGAL attribute: */ 157 #define XSHAL_STRICT_CACHEATTR_WRITEBACK 0xFFFFFF11 /* enable caches in write-back mode */ 158 #define XSHAL_STRICT_CACHEATTR_WRITEALLOC 0xFFFFFF11 /* enable caches in write-allocate mode */ 159 #define XSHAL_STRICT_CACHEATTR_WRITETHRU 0xFFFFFF11 /* enable caches in write-through mode */ 160 #define XSHAL_STRICT_CACHEATTR_BYPASS 0xFFFFFF22 /* disable caches in bypass mode */ 161 #define XSHAL_STRICT_CACHEATTR_DEFAULT XSHAL_STRICT_CACHEATTR_WRITEBACK /* default setting to enable caches */ 162 163 /* These set the first 512MB, if unused, to ILLEGAL attribute to help catch 164 * NULL-pointer dereference bugs; all other unused 512MB regions are set 165 * to cache-BYPASS attribute: */ 166 #define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x22222211 /* enable caches in write-back mode */ 167 #define XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC 0x22222211 /* enable caches in write-allocate mode */ 168 #define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU 0x22222211 /* enable caches in write-through mode */ 169 #define XSHAL_TRAPNULL_CACHEATTR_BYPASS 0x22222222 /* disable caches in bypass mode */ 170 #define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to enable caches */ 171 172 /*---------------------------------------------------------------------- 173 ISS (Instruction Set Simulator) SPECIFIC ... 174 ----------------------------------------------------------------------*/ 175 176 /* For now, ISS defaults to the TRAPNULL settings: */ 177 #define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 178 #define XSHAL_ISS_CACHEATTR_WRITEALLOC XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC 179 #define XSHAL_ISS_CACHEATTR_WRITETHRU XSHAL_TRAPNULL_CACHEATTR_WRITETHRU 180 #define XSHAL_ISS_CACHEATTR_BYPASS XSHAL_TRAPNULL_CACHEATTR_BYPASS 181 #define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 182 183 #define XSHAL_ISS_PIPE_REGIONS 0 184 #define XSHAL_ISS_SDRAM_REGIONS 0 185 186 187 /*---------------------------------------------------------------------- 188 XT2000 BOARD SPECIFIC ... 189 ----------------------------------------------------------------------*/ 190 191 /* For the following, a 512MB region is used if it contains any system RAM, 192 * system ROM, local memory, XLMI, or other XT2000 board device or memory. 193 * Regions containing devices are forced to cache-BYPASS mode regardless 194 * of whether the macro is _WRITEBACK vs. _BYPASS etc. */ 195 196 /* These set any 512MB region unused on the XT2000 to ILLEGAL attribute: */ 197 #define XSHAL_XT2000_CACHEATTR_WRITEBACK 0xFFF21211 /* enable caches in write-back mode */ 198 #define XSHAL_XT2000_CACHEATTR_WRITEALLOC 0xFFF21211 /* enable caches in write-allocate mode */ 199 #define XSHAL_XT2000_CACHEATTR_WRITETHRU 0xFFF21211 /* enable caches in write-through mode */ 200 #define XSHAL_XT2000_CACHEATTR_BYPASS 0xFFF22222 /* disable caches in bypass mode */ 201 #define XSHAL_XT2000_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_WRITEBACK /* default setting to enable caches */ 202 203 #define XSHAL_XT2000_PIPE_REGIONS 0x00000000 /* BusInt pipeline regions */ 204 #define XSHAL_XT2000_SDRAM_REGIONS 0x00000014 /* BusInt SDRAM regions */ 205 206 207 /*---------------------------------------------------------------------- 208 VECTOR INFO AND SIZES 209 ----------------------------------------------------------------------*/ 210 211 #define XSHAL_VECTORS_PACKED 0 /* UNUSED */ 212 #define XSHAL_STATIC_VECTOR_SELECT 0 213 #define XSHAL_RESET_VECTOR_VADDR 0x00000000 214 #define XSHAL_RESET_VECTOR_PADDR 0x00000000 215 216 /* 217 * Sizes allocated to vectors by the system (memory map) configuration. 218 * These sizes are constrained by core configuration (eg. one vector's 219 * code cannot overflow into another vector) but are dependent on the 220 * system or board (or LSP) memory map configuration. 221 * 222 * Whether or not each vector happens to be in a system ROM is also 223 * a system configuration matter, sometimes useful, included here also: 224 */ 225 #define XSHAL_RESET_VECTOR_SIZE 0x000002E0 226 #define XSHAL_RESET_VECTOR_ISROM 0 227 #define XSHAL_USER_VECTOR_SIZE 0x0000001C 228 #define XSHAL_USER_VECTOR_ISROM 0 229 #define XSHAL_PROGRAMEXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */ 230 #define XSHAL_USEREXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */ 231 #define XSHAL_KERNEL_VECTOR_SIZE 0x0000001C 232 #define XSHAL_KERNEL_VECTOR_ISROM 0 233 #define XSHAL_STACKEDEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */ 234 #define XSHAL_KERNELEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */ 235 #define XSHAL_DOUBLEEXC_VECTOR_SIZE 0x0000001C 236 #define XSHAL_DOUBLEEXC_VECTOR_ISROM 0 237 #define XSHAL_WINDOW_VECTORS_SIZE 0x00000178 238 #define XSHAL_WINDOW_VECTORS_ISROM 0 239 #define XSHAL_INTLEVEL2_VECTOR_SIZE 0x0000001C 240 #define XSHAL_INTLEVEL2_VECTOR_ISROM 0 241 #define XSHAL_INTLEVEL3_VECTOR_SIZE 0x0000001C 242 #define XSHAL_INTLEVEL3_VECTOR_ISROM 0 243 #define XSHAL_INTLEVEL4_VECTOR_SIZE 0x0000001C 244 #define XSHAL_INTLEVEL4_VECTOR_ISROM 0 245 #define XSHAL_DEBUG_VECTOR_SIZE XSHAL_INTLEVEL4_VECTOR_SIZE 246 #define XSHAL_DEBUG_VECTOR_ISROM XSHAL_INTLEVEL4_VECTOR_ISROM 247 #define XSHAL_NMI_VECTOR_SIZE 0x0000001C 248 #define XSHAL_NMI_VECTOR_ISROM 0 249 #define XSHAL_INTLEVEL5_VECTOR_SIZE XSHAL_NMI_VECTOR_SIZE 250 251 #endif /*XTENSA_CONFIG_SYSTEM_H*/ 252 253
