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Searched refs:QUADSPI_CCR_DDRM_Pos (Results 1 – 25 of 83) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32l4xx/soc/
Dstm32l422xx.h7692 #define QUADSPI_CCR_DDRM_Pos (31U) macro
7693 #define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
Dstm32l412xx.h7467 #define QUADSPI_CCR_DDRM_Pos (31U) macro
7468 #define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
Dstm32l433xx.h12157 #define QUADSPI_CCR_DDRM_Pos (31U) macro
12158 #define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
Dstm32l451xx.h12212 #define QUADSPI_CCR_DDRM_Pos (31U) macro
12213 #define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
Dstm32l442xx.h11387 #define QUADSPI_CCR_DDRM_Pos (31U) macro
11388 #define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
Dstm32l431xx.h11928 #define QUADSPI_CCR_DDRM_Pos (31U) macro
11929 #define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
Dstm32l432xx.h11162 #define QUADSPI_CCR_DDRM_Pos (31U) macro
11163 #define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/
Dstm32wb35xx.h7046 #define QUADSPI_CCR_DDRM_Pos (31U) macro
7047 #define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
Dstm32wb55xx.h7237 #define QUADSPI_CCR_DDRM_Pos (31U) macro
7238 #define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
Dstm32wb5mxx.h7237 #define QUADSPI_CCR_DDRM_Pos (31U) macro
7238 #define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
/hal_stm32-latest/stm32cube/stm32g4xx/soc/
Dstm32g4a1xx.h7764 #define QUADSPI_CCR_DDRM_Pos (31U) macro
7765 #define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
Dstm32g491xx.h7543 #define QUADSPI_CCR_DDRM_Pos (31U) macro
7544 #define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
Dstm32g473xx.h8206 #define QUADSPI_CCR_DDRM_Pos (31U) macro
8207 #define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
Dstm32g471xx.h7692 #define QUADSPI_CCR_DDRM_Pos (31U) macro
7693 #define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
Dstm32g483xx.h8427 #define QUADSPI_CCR_DDRM_Pos (31U) macro
8428 #define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
/hal_stm32-latest/stm32cube/stm32f7xx/soc/
Dstm32f723xx.h9070 #define QUADSPI_CCR_DDRM_Pos (31U) macro
9071 #define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
Dstm32f722xx.h9054 #define QUADSPI_CCR_DDRM_Pos (31U) macro
9055 #define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
Dstm32f730xx.h9284 #define QUADSPI_CCR_DDRM_Pos (31U) macro
9285 #define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
Dstm32f733xx.h9284 #define QUADSPI_CCR_DDRM_Pos (31U) macro
9285 #define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
Dstm32f732xx.h9268 #define QUADSPI_CCR_DDRM_Pos (31U) macro
9269 #define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f423xx.h9450 #define QUADSPI_CCR_DDRM_Pos (31U) macro
9451 #define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
Dstm32f412zx.h9180 #define QUADSPI_CCR_DDRM_Pos (31U) macro
9181 #define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
Dstm32f412rx.h9174 #define QUADSPI_CCR_DDRM_Pos (31U) macro
9175 #define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
Dstm32f412vx.h9176 #define QUADSPI_CCR_DDRM_Pos (31U) macro
9177 #define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
Dstm32f413xx.h9414 #define QUADSPI_CCR_DDRM_Pos (31U) macro
9415 #define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */

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