1 /** 2 ****************************************************************************** 3 * @file stm32l432xx.h 4 * @author MCD Application Team 5 * @brief CMSIS STM32L432xx Device Peripheral Access Layer Header File. 6 * 7 * This file contains: 8 * - Data structures and the address mapping for all peripherals 9 * - Peripheral's registers declarations and bits definition 10 * - Macros to access peripheral's registers hardware 11 * 12 ****************************************************************************** 13 * @attention 14 * 15 * Copyright (c) 2017 STMicroelectronics. 16 * All rights reserved. 17 * 18 * This software is licensed under terms that can be found in the LICENSE file 19 * in the root directory of this software component. 20 * If no LICENSE file comes with this software, it is provided AS-IS. 21 * 22 ****************************************************************************** 23 */ 24 25 /** @addtogroup CMSIS_Device 26 * @{ 27 */ 28 29 /** @addtogroup stm32l432xx 30 * @{ 31 */ 32 33 #ifndef __STM32L432xx_H 34 #define __STM32L432xx_H 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif /* __cplusplus */ 39 40 /** @addtogroup Configuration_section_for_CMSIS 41 * @{ 42 */ 43 44 /** 45 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 46 */ 47 #define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */ 48 #define __MPU_PRESENT 1U /*!< STM32L4XX provides an MPU */ 49 #define __NVIC_PRIO_BITS 4U /*!< STM32L4XX uses 4 Bits for the Priority Levels */ 50 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ 51 #define __FPU_PRESENT 1U /*!< FPU present */ 52 53 /** 54 * @} 55 */ 56 57 /** @addtogroup Peripheral_interrupt_number_definition 58 * @{ 59 */ 60 61 /** 62 * @brief STM32L4XX Interrupt Number Definition, according to the selected device 63 * in @ref Library_configuration_section 64 */ 65 typedef enum 66 { 67 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ 68 NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */ 69 HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ 70 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ 71 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ 72 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ 73 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ 74 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ 75 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ 76 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ 77 /****** STM32 specific Interrupt Numbers **********************************************************************/ 78 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ 79 PVD_PVM_IRQn = 1, /*!< PVD/PVM3/PVM4 through EXTI Line detection Interrupts */ 80 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ 81 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ 82 FLASH_IRQn = 4, /*!< FLASH global Interrupt */ 83 RCC_IRQn = 5, /*!< RCC global Interrupt */ 84 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ 85 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ 86 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ 87 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ 88 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ 89 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ 90 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ 91 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ 92 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ 93 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ 94 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ 95 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ 96 ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ 97 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ 98 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ 99 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ 100 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ 101 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ 102 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break interrupt and TIM15 global interrupt */ 103 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */ 104 TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ 105 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ 106 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ 107 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ 108 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ 109 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ 110 USART1_IRQn = 37, /*!< USART1 global Interrupt */ 111 USART2_IRQn = 38, /*!< USART2 global Interrupt */ 112 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ 113 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ 114 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ 115 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ 116 TIM7_IRQn = 55, /*!< TIM7 global interrupt */ 117 DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ 118 DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ 119 DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ 120 DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ 121 DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ 122 COMP_IRQn = 64, /*!< COMP1 and COMP2 Interrupts */ 123 LPTIM1_IRQn = 65, /*!< LP TIM1 interrupt */ 124 LPTIM2_IRQn = 66, /*!< LP TIM2 interrupt */ 125 USB_IRQn = 67, /*!< USB event Interrupt */ 126 DMA2_Channel6_IRQn = 68, /*!< DMA2 Channel 6 global interrupt */ 127 DMA2_Channel7_IRQn = 69, /*!< DMA2 Channel 7 global interrupt */ 128 LPUART1_IRQn = 70, /*!< LP UART1 interrupt */ 129 QUADSPI_IRQn = 71, /*!< Quad SPI global interrupt */ 130 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ 131 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ 132 SAI1_IRQn = 74, /*!< Serial Audio Interface 1 global interrupt */ 133 SWPMI1_IRQn = 76, /*!< Serial Wire Interface 1 global interrupt */ 134 TSC_IRQn = 77, /*!< Touch Sense Controller global interrupt */ 135 RNG_IRQn = 80, /*!< RNG global interrupt */ 136 FPU_IRQn = 81, /*!< FPU global interrupt */ 137 CRS_IRQn = 82 /*!< CRS global interrupt */ 138 } IRQn_Type; 139 140 /** 141 * @} 142 */ 143 144 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ 145 #include "system_stm32l4xx.h" 146 #include <stdint.h> 147 148 /** @addtogroup Peripheral_registers_structures 149 * @{ 150 */ 151 152 /** 153 * @brief Analog to Digital Converter 154 */ 155 156 typedef struct 157 { 158 __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ 159 __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ 160 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ 161 __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */ 162 __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ 163 __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */ 164 __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */ 165 uint32_t RESERVED1; /*!< Reserved, 0x1C */ 166 __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ 167 __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ 168 __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */ 169 uint32_t RESERVED2; /*!< Reserved, 0x2C */ 170 __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */ 171 __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */ 172 __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */ 173 __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */ 174 __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ 175 uint32_t RESERVED3; /*!< Reserved, 0x44 */ 176 uint32_t RESERVED4; /*!< Reserved, 0x48 */ 177 __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */ 178 uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */ 179 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ 180 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ 181 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ 182 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ 183 uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */ 184 __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */ 185 __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */ 186 __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */ 187 __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */ 188 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ 189 __IO uint32_t AWD2CR; /*!< ADC analog watchdog 1 configuration register, Address offset: 0xA0 */ 190 __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */ 191 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ 192 uint32_t RESERVED9; /*!< Reserved, 0x0AC */ 193 __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */ 194 __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */ 195 196 } ADC_TypeDef; 197 198 typedef struct 199 { 200 uint32_t RESERVED1; /*!< Reserved, Address offset: ADC1 base address + 0x300 */ 201 uint32_t RESERVED2; /*!< Reserved, Address offset: ADC1 base address + 0x304 */ 202 __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ 203 uint32_t RESERVED3; /*!< Reserved, Address offset: ADC1 base address + 0x30C */ 204 } ADC_Common_TypeDef; 205 206 207 /** 208 * @brief Controller Area Network TxMailBox 209 */ 210 211 typedef struct 212 { 213 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ 214 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ 215 __IO uint32_t TDLR; /*!< CAN mailbox data low register */ 216 __IO uint32_t TDHR; /*!< CAN mailbox data high register */ 217 } CAN_TxMailBox_TypeDef; 218 219 /** 220 * @brief Controller Area Network FIFOMailBox 221 */ 222 223 typedef struct 224 { 225 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ 226 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ 227 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ 228 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ 229 } CAN_FIFOMailBox_TypeDef; 230 231 /** 232 * @brief Controller Area Network FilterRegister 233 */ 234 235 typedef struct 236 { 237 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ 238 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ 239 } CAN_FilterRegister_TypeDef; 240 241 /** 242 * @brief Controller Area Network 243 */ 244 245 typedef struct 246 { 247 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ 248 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ 249 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ 250 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ 251 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ 252 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ 253 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ 254 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ 255 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ 256 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ 257 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ 258 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ 259 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ 260 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ 261 uint32_t RESERVED2; /*!< Reserved, 0x208 */ 262 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ 263 uint32_t RESERVED3; /*!< Reserved, 0x210 */ 264 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ 265 uint32_t RESERVED4; /*!< Reserved, 0x218 */ 266 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ 267 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ 268 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ 269 } CAN_TypeDef; 270 271 272 /** 273 * @brief Comparator 274 */ 275 276 typedef struct 277 { 278 __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ 279 } COMP_TypeDef; 280 281 typedef struct 282 { 283 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ 284 } COMP_Common_TypeDef; 285 286 /** 287 * @brief CRC calculation unit 288 */ 289 290 typedef struct 291 { 292 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ 293 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ 294 uint8_t RESERVED0; /*!< Reserved, 0x05 */ 295 uint16_t RESERVED1; /*!< Reserved, 0x06 */ 296 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ 297 uint32_t RESERVED2; /*!< Reserved, 0x0C */ 298 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ 299 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ 300 } CRC_TypeDef; 301 302 /** 303 * @brief Clock Recovery System 304 */ 305 typedef struct 306 { 307 __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ 308 __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ 309 __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ 310 __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ 311 } CRS_TypeDef; 312 313 /** 314 * @brief Digital to Analog Converter 315 */ 316 317 typedef struct 318 { 319 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ 320 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ 321 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ 322 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ 323 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ 324 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ 325 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ 326 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ 327 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ 328 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ 329 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ 330 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ 331 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ 332 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ 333 __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ 334 __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ 335 __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ 336 __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ 337 __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ 338 __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ 339 } DAC_TypeDef; 340 341 342 /** 343 * @brief Debug MCU 344 */ 345 346 typedef struct 347 { 348 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ 349 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ 350 __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ 351 __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ 352 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ 353 } DBGMCU_TypeDef; 354 355 356 /** 357 * @brief DMA Controller 358 */ 359 360 typedef struct 361 { 362 __IO uint32_t CCR; /*!< DMA channel x configuration register */ 363 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ 364 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ 365 __IO uint32_t CMAR; /*!< DMA channel x memory address register */ 366 } DMA_Channel_TypeDef; 367 368 typedef struct 369 { 370 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ 371 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ 372 } DMA_TypeDef; 373 374 typedef struct 375 { 376 __IO uint32_t CSELR; /*!< DMA channel selection register */ 377 } DMA_Request_TypeDef; 378 379 /* Legacy define */ 380 #define DMA_request_TypeDef DMA_Request_TypeDef 381 382 383 /** 384 * @brief External Interrupt/Event Controller 385 */ 386 387 typedef struct 388 { 389 __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ 390 __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */ 391 __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ 392 __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ 393 __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ 394 __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */ 395 uint32_t RESERVED1; /*!< Reserved, 0x18 */ 396 uint32_t RESERVED2; /*!< Reserved, 0x1C */ 397 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */ 398 __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */ 399 __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */ 400 __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */ 401 __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */ 402 __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */ 403 } EXTI_TypeDef; 404 405 406 /** 407 * @brief Firewall 408 */ 409 410 typedef struct 411 { 412 __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */ 413 __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */ 414 __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */ 415 __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */ 416 __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */ 417 __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */ 418 uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x18 */ 419 uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ 420 __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */ 421 } FIREWALL_TypeDef; 422 423 424 /** 425 * @brief FLASH Registers 426 */ 427 428 typedef struct 429 { 430 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ 431 __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */ 432 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */ 433 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ 434 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */ 435 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */ 436 __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ 437 __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */ 438 __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */ 439 __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */ 440 __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */ 441 __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */ 442 __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */ 443 } FLASH_TypeDef; 444 445 446 447 /** 448 * @brief General Purpose I/O 449 */ 450 451 typedef struct 452 { 453 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ 454 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ 455 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ 456 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ 457 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ 458 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ 459 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ 460 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ 461 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ 462 __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ 463 464 } GPIO_TypeDef; 465 466 467 /** 468 * @brief Inter-integrated Circuit Interface 469 */ 470 471 typedef struct 472 { 473 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ 474 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ 475 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ 476 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ 477 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ 478 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ 479 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ 480 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ 481 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ 482 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ 483 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ 484 } I2C_TypeDef; 485 486 /** 487 * @brief Independent WATCHDOG 488 */ 489 490 typedef struct 491 { 492 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ 493 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ 494 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ 495 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ 496 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ 497 } IWDG_TypeDef; 498 499 /** 500 * @brief LPTIMER 501 */ 502 typedef struct 503 { 504 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ 505 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ 506 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ 507 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ 508 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ 509 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ 510 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ 511 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ 512 __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ 513 } LPTIM_TypeDef; 514 515 /** 516 * @brief Operational Amplifier (OPAMP) 517 */ 518 519 typedef struct 520 { 521 __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ 522 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ 523 __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ 524 } OPAMP_TypeDef; 525 526 typedef struct 527 { 528 __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */ 529 } OPAMP_Common_TypeDef; 530 531 /** 532 * @brief Power Control 533 */ 534 535 typedef struct 536 { 537 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ 538 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */ 539 __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */ 540 __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */ 541 __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */ 542 __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */ 543 __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */ 544 uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */ 545 __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */ 546 __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */ 547 __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */ 548 __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */ 549 __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */ 550 __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */ 551 __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */ 552 __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */ 553 __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */ 554 __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */ 555 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x48 */ 556 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x4C */ 557 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x50 */ 558 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x54 */ 559 __IO uint32_t PUCRH; /*!< Pull_up control register of portH, Address offset: 0x58 */ 560 __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */ 561 } PWR_TypeDef; 562 563 564 /** 565 * @brief QUAD Serial Peripheral Interface 566 */ 567 568 typedef struct 569 { 570 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ 571 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ 572 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ 573 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ 574 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ 575 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ 576 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ 577 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ 578 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ 579 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ 580 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ 581 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ 582 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ 583 } QUADSPI_TypeDef; 584 585 586 /** 587 * @brief Reset and Clock Control 588 */ 589 590 typedef struct 591 { 592 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ 593 __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */ 594 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ 595 __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */ 596 __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register, Address offset: 0x10 */ 597 uint32_t RESERVED; /*!< Reserved, Address offset: 0x14 */ 598 __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */ 599 __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */ 600 __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */ 601 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x24 */ 602 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ 603 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ 604 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */ 605 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */ 606 __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */ 607 __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */ 608 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */ 609 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x44 */ 610 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */ 611 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */ 612 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */ 613 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x54 */ 614 __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */ 615 __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */ 616 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */ 617 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x64 */ 618 __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */ 619 __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */ 620 __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */ 621 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x74 */ 622 __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */ 623 __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */ 624 __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */ 625 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x84 */ 626 __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */ 627 uint32_t RESERVED7; /*!< Reserved, Address offset: 0x8C */ 628 __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */ 629 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */ 630 __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */ 631 } RCC_TypeDef; 632 633 /** 634 * @brief Real-Time Clock 635 */ 636 637 typedef struct 638 { 639 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ 640 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ 641 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ 642 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ 643 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ 644 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ 645 uint32_t reserved; /*!< Reserved */ 646 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ 647 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ 648 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ 649 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ 650 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ 651 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ 652 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ 653 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ 654 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ 655 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ 656 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ 657 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ 658 __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ 659 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ 660 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ 661 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ 662 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ 663 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ 664 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ 665 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ 666 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ 667 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ 668 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ 669 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ 670 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ 671 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ 672 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ 673 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ 674 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ 675 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ 676 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ 677 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ 678 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ 679 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ 680 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ 681 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ 682 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ 683 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ 684 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ 685 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ 686 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ 687 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ 688 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ 689 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ 690 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ 691 } RTC_TypeDef; 692 693 /** 694 * @brief Serial Audio Interface 695 */ 696 697 typedef struct 698 { 699 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ 700 } SAI_TypeDef; 701 702 typedef struct 703 { 704 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ 705 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ 706 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ 707 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ 708 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ 709 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ 710 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ 711 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ 712 } SAI_Block_TypeDef; 713 714 715 /** 716 * @brief Serial Peripheral Interface 717 */ 718 719 typedef struct 720 { 721 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ 722 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ 723 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ 724 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ 725 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ 726 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ 727 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ 728 } SPI_TypeDef; 729 730 731 /** 732 * @brief Single Wire Protocol Master Interface SPWMI 733 */ 734 735 typedef struct 736 { 737 __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */ 738 __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */ 739 uint32_t RESERVED1; /*!< Reserved, 0x08 */ 740 __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */ 741 __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */ 742 __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */ 743 __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */ 744 __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */ 745 __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */ 746 __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */ 747 } SWPMI_TypeDef; 748 749 750 /** 751 * @brief System configuration controller 752 */ 753 754 typedef struct 755 { 756 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ 757 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ 758 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ 759 __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */ 760 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */ 761 __IO uint32_t SWPR; /*!< SYSCFG SRAM2 write protection register, Address offset: 0x20 */ 762 __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */ 763 } SYSCFG_TypeDef; 764 765 766 /** 767 * @brief TIM 768 */ 769 770 typedef struct 771 { 772 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ 773 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ 774 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ 775 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ 776 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ 777 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ 778 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ 779 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ 780 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ 781 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ 782 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ 783 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ 784 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ 785 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ 786 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ 787 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ 788 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ 789 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ 790 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ 791 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ 792 __IO uint32_t OR1; /*!< TIM option register 1, Address offset: 0x50 */ 793 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ 794 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ 795 __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ 796 __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */ 797 __IO uint32_t OR3; /*!< TIM option register 3, Address offset: 0x64 */ 798 } TIM_TypeDef; 799 800 801 /** 802 * @brief Touch Sensing Controller (TSC) 803 */ 804 805 typedef struct 806 { 807 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ 808 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ 809 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ 810 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ 811 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ 812 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ 813 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ 814 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ 815 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ 816 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ 817 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ 818 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ 819 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ 820 __IO uint32_t IOGXCR[7]; /*!< TSC I/O group x counter register, Address offset: 0x34-4C */ 821 } TSC_TypeDef; 822 823 /** 824 * @brief Universal Synchronous Asynchronous Receiver Transmitter 825 */ 826 827 typedef struct 828 { 829 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ 830 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ 831 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ 832 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ 833 __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ 834 uint16_t RESERVED2; /*!< Reserved, 0x12 */ 835 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ 836 __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ 837 uint16_t RESERVED3; /*!< Reserved, 0x1A */ 838 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ 839 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ 840 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ 841 uint16_t RESERVED4; /*!< Reserved, 0x26 */ 842 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ 843 uint16_t RESERVED5; /*!< Reserved, 0x2A */ 844 } USART_TypeDef; 845 846 /** 847 * @brief Universal Serial Bus Full Speed Device 848 */ 849 850 typedef struct 851 { 852 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ 853 __IO uint16_t RESERVED0; /*!< Reserved */ 854 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ 855 __IO uint16_t RESERVED1; /*!< Reserved */ 856 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ 857 __IO uint16_t RESERVED2; /*!< Reserved */ 858 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ 859 __IO uint16_t RESERVED3; /*!< Reserved */ 860 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ 861 __IO uint16_t RESERVED4; /*!< Reserved */ 862 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ 863 __IO uint16_t RESERVED5; /*!< Reserved */ 864 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ 865 __IO uint16_t RESERVED6; /*!< Reserved */ 866 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ 867 __IO uint16_t RESERVED7[17]; /*!< Reserved */ 868 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ 869 __IO uint16_t RESERVED8; /*!< Reserved */ 870 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ 871 __IO uint16_t RESERVED9; /*!< Reserved */ 872 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ 873 __IO uint16_t RESERVEDA; /*!< Reserved */ 874 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ 875 __IO uint16_t RESERVEDB; /*!< Reserved */ 876 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ 877 __IO uint16_t RESERVEDC; /*!< Reserved */ 878 __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ 879 __IO uint16_t RESERVEDD; /*!< Reserved */ 880 __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ 881 __IO uint16_t RESERVEDE; /*!< Reserved */ 882 } USB_TypeDef; 883 884 885 /** 886 * @brief Window WATCHDOG 887 */ 888 889 typedef struct 890 { 891 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ 892 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ 893 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ 894 } WWDG_TypeDef; 895 896 /** 897 * @brief RNG 898 */ 899 900 typedef struct 901 { 902 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ 903 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ 904 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ 905 } RNG_TypeDef; 906 907 /** 908 * @} 909 */ 910 911 /** @addtogroup Peripheral_memory_map 912 * @{ 913 */ 914 #define FLASH_BASE (0x08000000UL) /*!< FLASH(up to 256 KB) base address */ 915 #define FLASH_END (0x0803FFFFUL) /*!< FLASH END address */ 916 #define FLASH_BANK1_END (0x0803FFFFUL) /*!< FLASH END address of bank1 */ 917 #define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 48 KB) base address */ 918 #define SRAM2_BASE (0x10000000UL) /*!< SRAM2(16 KB) base address */ 919 #define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ 920 #define QSPI_BASE (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */ 921 922 #define QSPI_R_BASE (0xA0001000UL) /*!< QUADSPI control registers base address */ 923 #define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(96 KB) base address in the bit-band region */ 924 #define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ 925 926 /* Legacy defines */ 927 #define SRAM_BASE SRAM1_BASE 928 #define SRAM_BB_BASE SRAM1_BB_BASE 929 930 #define SRAM1_SIZE_MAX (0x0000C000UL) /*!< maximum SRAM1 size (up to 48 KBytes) */ 931 #define SRAM2_SIZE (0x00004000UL) /*!< SRAM2 size (16 KBytes) */ 932 933 #define FLASH_SIZE_DATA_REGISTER (0x1FFF75E0UL) 934 935 #define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x100U << 10U) : \ 936 (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U)) 937 938 /*!< Peripheral memory map */ 939 #define APB1PERIPH_BASE PERIPH_BASE 940 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) 941 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) 942 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) 943 944 945 /*!< APB1 peripherals */ 946 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) 947 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) 948 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) 949 #define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) 950 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) 951 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) 952 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) 953 #define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) 954 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) 955 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) 956 #define CRS_BASE (APB1PERIPH_BASE + 0x6000UL) 957 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL) 958 #define USB_BASE (APB1PERIPH_BASE + 0x6800UL) /*!< USB_IP Peripheral Registers base address */ 959 #define USB_PMAADDR (APB1PERIPH_BASE + 0x6C00UL) /*!< USB_IP Packet Memory Area base address */ 960 #define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) 961 #define DAC_BASE (APB1PERIPH_BASE + 0x7400UL) 962 #define DAC1_BASE (APB1PERIPH_BASE + 0x7400UL) 963 #define OPAMP_BASE (APB1PERIPH_BASE + 0x7800UL) 964 #define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800UL) 965 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) 966 #define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) 967 #define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800UL) 968 #define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400UL) 969 970 971 /*!< APB2 peripherals */ 972 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) 973 #define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL) 974 #define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL) 975 #define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL) 976 #define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00UL) 977 #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) 978 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) 979 #define USART1_BASE (APB2PERIPH_BASE + 0x3800UL) 980 #define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) 981 #define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) 982 #define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL) 983 #define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) 984 #define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) 985 986 /*!< AHB1 peripherals */ 987 #define DMA1_BASE (AHB1PERIPH_BASE) 988 #define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) 989 #define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) 990 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) 991 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) 992 #define TSC_BASE (AHB1PERIPH_BASE + 0x4000UL) 993 994 995 #define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) 996 #define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) 997 #define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) 998 #define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) 999 #define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) 1000 #define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) 1001 #define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL) 1002 #define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8UL) 1003 1004 1005 #define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) 1006 #define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) 1007 #define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) 1008 #define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) 1009 #define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) 1010 #define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) 1011 #define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL) 1012 #define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8UL) 1013 1014 1015 /*!< AHB2 peripherals */ 1016 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL) 1017 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL) 1018 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL) 1019 #define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00UL) 1020 1021 1022 #define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000UL) 1023 #define ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300UL) 1024 1025 1026 #define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL) 1027 1028 1029 1030 /* Debug MCU registers base address */ 1031 #define DBGMCU_BASE (0xE0042000UL) 1032 1033 1034 #define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ 1035 #define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ 1036 #define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ 1037 /** 1038 * @} 1039 */ 1040 1041 /** @addtogroup Peripheral_declaration 1042 * @{ 1043 */ 1044 #define TIM2 ((TIM_TypeDef *) TIM2_BASE) 1045 #define TIM6 ((TIM_TypeDef *) TIM6_BASE) 1046 #define TIM7 ((TIM_TypeDef *) TIM7_BASE) 1047 #define RTC ((RTC_TypeDef *) RTC_BASE) 1048 #define WWDG ((WWDG_TypeDef *) WWDG_BASE) 1049 #define IWDG ((IWDG_TypeDef *) IWDG_BASE) 1050 #define SPI3 ((SPI_TypeDef *) SPI3_BASE) 1051 #define USART2 ((USART_TypeDef *) USART2_BASE) 1052 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) 1053 #define I2C3 ((I2C_TypeDef *) I2C3_BASE) 1054 #define CRS ((CRS_TypeDef *) CRS_BASE) 1055 #define CAN ((CAN_TypeDef *) CAN1_BASE) 1056 #define CAN1 ((CAN_TypeDef *) CAN1_BASE) 1057 #define USB ((USB_TypeDef *) USB_BASE) 1058 #define PWR ((PWR_TypeDef *) PWR_BASE) 1059 #define DAC ((DAC_TypeDef *) DAC1_BASE) 1060 #define DAC1 ((DAC_TypeDef *) DAC1_BASE) 1061 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) 1062 #define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) 1063 #define OPAMP1_COMMON ((OPAMP_Common_TypeDef *) OPAMP1_BASE) 1064 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) 1065 #define LPUART1 ((USART_TypeDef *) LPUART1_BASE) 1066 #define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE) 1067 #define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) 1068 1069 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) 1070 #define COMP1 ((COMP_TypeDef *) COMP1_BASE) 1071 #define COMP2 ((COMP_TypeDef *) COMP2_BASE) 1072 #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE) 1073 #define EXTI ((EXTI_TypeDef *) EXTI_BASE) 1074 #define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE) 1075 #define TIM1 ((TIM_TypeDef *) TIM1_BASE) 1076 #define SPI1 ((SPI_TypeDef *) SPI1_BASE) 1077 #define USART1 ((USART_TypeDef *) USART1_BASE) 1078 #define TIM15 ((TIM_TypeDef *) TIM15_BASE) 1079 #define TIM16 ((TIM_TypeDef *) TIM16_BASE) 1080 #define SAI1 ((SAI_TypeDef *) SAI1_BASE) 1081 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) 1082 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) 1083 #define DMA1 ((DMA_TypeDef *) DMA1_BASE) 1084 #define DMA2 ((DMA_TypeDef *) DMA2_BASE) 1085 #define RCC ((RCC_TypeDef *) RCC_BASE) 1086 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) 1087 #define CRC ((CRC_TypeDef *) CRC_BASE) 1088 #define TSC ((TSC_TypeDef *) TSC_BASE) 1089 1090 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) 1091 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) 1092 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) 1093 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) 1094 #define ADC1 ((ADC_TypeDef *) ADC1_BASE) 1095 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE) 1096 #define RNG ((RNG_TypeDef *) RNG_BASE) 1097 1098 1099 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) 1100 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) 1101 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) 1102 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) 1103 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) 1104 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) 1105 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) 1106 #define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE) 1107 1108 1109 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) 1110 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) 1111 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) 1112 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) 1113 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) 1114 #define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) 1115 #define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) 1116 #define DMA2_CSELR ((DMA_Request_TypeDef *) DMA2_CSELR_BASE) 1117 1118 1119 1120 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) 1121 1122 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) 1123 1124 /** 1125 * @} 1126 */ 1127 1128 /** @addtogroup Exported_constants 1129 * @{ 1130 */ 1131 1132 /** @addtogroup Hardware_Constant_Definition 1133 * @{ 1134 */ 1135 #define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ 1136 1137 /** 1138 * @} 1139 */ 1140 1141 /** @addtogroup Peripheral_Registers_Bits_Definition 1142 * @{ 1143 */ 1144 1145 /******************************************************************************/ 1146 /* Peripheral Registers_Bits_Definition */ 1147 /******************************************************************************/ 1148 1149 /******************************************************************************/ 1150 /* */ 1151 /* Analog to Digital Converter */ 1152 /* */ 1153 /******************************************************************************/ 1154 1155 /* 1156 * @brief Specific device feature definitions (not present on all devices in the STM32L4 series) 1157 */ 1158 /* Note: No specific macro feature on this device */ 1159 1160 /******************** Bit definition for ADC_ISR register *******************/ 1161 #define ADC_ISR_ADRDY_Pos (0U) 1162 #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ 1163 #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ 1164 #define ADC_ISR_EOSMP_Pos (1U) 1165 #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ 1166 #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ 1167 #define ADC_ISR_EOC_Pos (2U) 1168 #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ 1169 #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ 1170 #define ADC_ISR_EOS_Pos (3U) 1171 #define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ 1172 #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ 1173 #define ADC_ISR_OVR_Pos (4U) 1174 #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ 1175 #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ 1176 #define ADC_ISR_JEOC_Pos (5U) 1177 #define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ 1178 #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ 1179 #define ADC_ISR_JEOS_Pos (6U) 1180 #define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ 1181 #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ 1182 #define ADC_ISR_AWD1_Pos (7U) 1183 #define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ 1184 #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ 1185 #define ADC_ISR_AWD2_Pos (8U) 1186 #define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ 1187 #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ 1188 #define ADC_ISR_AWD3_Pos (9U) 1189 #define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ 1190 #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ 1191 #define ADC_ISR_JQOVF_Pos (10U) 1192 #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ 1193 #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ 1194 1195 /******************** Bit definition for ADC_IER register *******************/ 1196 #define ADC_IER_ADRDYIE_Pos (0U) 1197 #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ 1198 #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ 1199 #define ADC_IER_EOSMPIE_Pos (1U) 1200 #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ 1201 #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ 1202 #define ADC_IER_EOCIE_Pos (2U) 1203 #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ 1204 #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ 1205 #define ADC_IER_EOSIE_Pos (3U) 1206 #define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ 1207 #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ 1208 #define ADC_IER_OVRIE_Pos (4U) 1209 #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ 1210 #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ 1211 #define ADC_IER_JEOCIE_Pos (5U) 1212 #define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ 1213 #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ 1214 #define ADC_IER_JEOSIE_Pos (6U) 1215 #define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ 1216 #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ 1217 #define ADC_IER_AWD1IE_Pos (7U) 1218 #define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ 1219 #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ 1220 #define ADC_IER_AWD2IE_Pos (8U) 1221 #define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ 1222 #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ 1223 #define ADC_IER_AWD3IE_Pos (9U) 1224 #define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ 1225 #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ 1226 #define ADC_IER_JQOVFIE_Pos (10U) 1227 #define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ 1228 #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ 1229 1230 /* Legacy defines */ 1231 #define ADC_IER_ADRDY (ADC_IER_ADRDYIE) 1232 #define ADC_IER_EOSMP (ADC_IER_EOSMPIE) 1233 #define ADC_IER_EOC (ADC_IER_EOCIE) 1234 #define ADC_IER_EOS (ADC_IER_EOSIE) 1235 #define ADC_IER_OVR (ADC_IER_OVRIE) 1236 #define ADC_IER_JEOC (ADC_IER_JEOCIE) 1237 #define ADC_IER_JEOS (ADC_IER_JEOSIE) 1238 #define ADC_IER_AWD1 (ADC_IER_AWD1IE) 1239 #define ADC_IER_AWD2 (ADC_IER_AWD2IE) 1240 #define ADC_IER_AWD3 (ADC_IER_AWD3IE) 1241 #define ADC_IER_JQOVF (ADC_IER_JQOVFIE) 1242 1243 /******************** Bit definition for ADC_CR register ********************/ 1244 #define ADC_CR_ADEN_Pos (0U) 1245 #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ 1246 #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ 1247 #define ADC_CR_ADDIS_Pos (1U) 1248 #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ 1249 #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ 1250 #define ADC_CR_ADSTART_Pos (2U) 1251 #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ 1252 #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ 1253 #define ADC_CR_JADSTART_Pos (3U) 1254 #define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ 1255 #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ 1256 #define ADC_CR_ADSTP_Pos (4U) 1257 #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ 1258 #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ 1259 #define ADC_CR_JADSTP_Pos (5U) 1260 #define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ 1261 #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ 1262 #define ADC_CR_ADVREGEN_Pos (28U) 1263 #define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ 1264 #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ 1265 #define ADC_CR_DEEPPWD_Pos (29U) 1266 #define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ 1267 #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ 1268 #define ADC_CR_ADCALDIF_Pos (30U) 1269 #define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ 1270 #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ 1271 #define ADC_CR_ADCAL_Pos (31U) 1272 #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ 1273 #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ 1274 1275 /******************** Bit definition for ADC_CFGR register ******************/ 1276 #define ADC_CFGR_DMAEN_Pos (0U) 1277 #define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ 1278 #define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ 1279 #define ADC_CFGR_DMACFG_Pos (1U) 1280 #define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ 1281 #define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ 1282 1283 #define ADC_CFGR_RES_Pos (3U) 1284 #define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ 1285 #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ 1286 #define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ 1287 #define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ 1288 1289 #define ADC_CFGR_ALIGN_Pos (5U) 1290 #define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ 1291 #define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */ 1292 1293 #define ADC_CFGR_EXTSEL_Pos (6U) 1294 #define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ 1295 #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ 1296 #define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ 1297 #define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ 1298 #define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ 1299 #define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ 1300 1301 #define ADC_CFGR_EXTEN_Pos (10U) 1302 #define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ 1303 #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ 1304 #define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ 1305 #define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ 1306 1307 #define ADC_CFGR_OVRMOD_Pos (12U) 1308 #define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ 1309 #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ 1310 #define ADC_CFGR_CONT_Pos (13U) 1311 #define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ 1312 #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ 1313 #define ADC_CFGR_AUTDLY_Pos (14U) 1314 #define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ 1315 #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ 1316 1317 #define ADC_CFGR_DISCEN_Pos (16U) 1318 #define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ 1319 #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ 1320 1321 #define ADC_CFGR_DISCNUM_Pos (17U) 1322 #define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ 1323 #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ 1324 #define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ 1325 #define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ 1326 #define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ 1327 1328 #define ADC_CFGR_JDISCEN_Pos (20U) 1329 #define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ 1330 #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ 1331 #define ADC_CFGR_JQM_Pos (21U) 1332 #define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ 1333 #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ 1334 #define ADC_CFGR_AWD1SGL_Pos (22U) 1335 #define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ 1336 #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ 1337 #define ADC_CFGR_AWD1EN_Pos (23U) 1338 #define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ 1339 #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ 1340 #define ADC_CFGR_JAWD1EN_Pos (24U) 1341 #define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ 1342 #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ 1343 #define ADC_CFGR_JAUTO_Pos (25U) 1344 #define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ 1345 #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ 1346 1347 #define ADC_CFGR_AWD1CH_Pos (26U) 1348 #define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ 1349 #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ 1350 #define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ 1351 #define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ 1352 #define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ 1353 #define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ 1354 #define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ 1355 1356 #define ADC_CFGR_JQDIS_Pos (31U) 1357 #define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ 1358 #define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ 1359 1360 /******************** Bit definition for ADC_CFGR2 register *****************/ 1361 #define ADC_CFGR2_ROVSE_Pos (0U) 1362 #define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ 1363 #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ 1364 #define ADC_CFGR2_JOVSE_Pos (1U) 1365 #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ 1366 #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ 1367 1368 #define ADC_CFGR2_OVSR_Pos (2U) 1369 #define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ 1370 #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ 1371 #define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ 1372 #define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ 1373 #define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ 1374 1375 #define ADC_CFGR2_OVSS_Pos (5U) 1376 #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ 1377 #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ 1378 #define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ 1379 #define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ 1380 #define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ 1381 #define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ 1382 1383 #define ADC_CFGR2_TROVS_Pos (9U) 1384 #define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ 1385 #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ 1386 #define ADC_CFGR2_ROVSM_Pos (10U) 1387 #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ 1388 #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ 1389 1390 /******************** Bit definition for ADC_SMPR1 register *****************/ 1391 #define ADC_SMPR1_SMP0_Pos (0U) 1392 #define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ 1393 #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ 1394 #define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ 1395 #define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ 1396 #define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ 1397 1398 #define ADC_SMPR1_SMP1_Pos (3U) 1399 #define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ 1400 #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ 1401 #define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ 1402 #define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ 1403 #define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ 1404 1405 #define ADC_SMPR1_SMP2_Pos (6U) 1406 #define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ 1407 #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ 1408 #define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ 1409 #define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ 1410 #define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ 1411 1412 #define ADC_SMPR1_SMP3_Pos (9U) 1413 #define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ 1414 #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ 1415 #define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ 1416 #define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ 1417 #define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ 1418 1419 #define ADC_SMPR1_SMP4_Pos (12U) 1420 #define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ 1421 #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ 1422 #define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ 1423 #define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ 1424 #define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ 1425 1426 #define ADC_SMPR1_SMP5_Pos (15U) 1427 #define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ 1428 #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ 1429 #define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ 1430 #define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ 1431 #define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ 1432 1433 #define ADC_SMPR1_SMP6_Pos (18U) 1434 #define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ 1435 #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ 1436 #define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ 1437 #define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ 1438 #define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ 1439 1440 #define ADC_SMPR1_SMP7_Pos (21U) 1441 #define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ 1442 #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ 1443 #define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ 1444 #define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ 1445 #define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ 1446 1447 #define ADC_SMPR1_SMP8_Pos (24U) 1448 #define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ 1449 #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ 1450 #define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ 1451 #define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ 1452 #define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ 1453 1454 #define ADC_SMPR1_SMP9_Pos (27U) 1455 #define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ 1456 #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ 1457 #define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ 1458 #define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ 1459 #define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ 1460 1461 /******************** Bit definition for ADC_SMPR2 register *****************/ 1462 #define ADC_SMPR2_SMP10_Pos (0U) 1463 #define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ 1464 #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ 1465 #define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ 1466 #define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ 1467 #define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ 1468 1469 #define ADC_SMPR2_SMP11_Pos (3U) 1470 #define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ 1471 #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ 1472 #define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ 1473 #define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ 1474 #define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ 1475 1476 #define ADC_SMPR2_SMP12_Pos (6U) 1477 #define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ 1478 #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ 1479 #define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ 1480 #define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ 1481 #define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ 1482 1483 #define ADC_SMPR2_SMP13_Pos (9U) 1484 #define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ 1485 #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ 1486 #define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ 1487 #define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ 1488 #define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ 1489 1490 #define ADC_SMPR2_SMP14_Pos (12U) 1491 #define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ 1492 #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ 1493 #define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ 1494 #define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ 1495 #define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ 1496 1497 #define ADC_SMPR2_SMP15_Pos (15U) 1498 #define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ 1499 #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ 1500 #define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ 1501 #define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ 1502 #define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ 1503 1504 #define ADC_SMPR2_SMP16_Pos (18U) 1505 #define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ 1506 #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ 1507 #define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ 1508 #define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ 1509 #define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ 1510 1511 #define ADC_SMPR2_SMP17_Pos (21U) 1512 #define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ 1513 #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ 1514 #define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ 1515 #define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ 1516 #define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ 1517 1518 #define ADC_SMPR2_SMP18_Pos (24U) 1519 #define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ 1520 #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ 1521 #define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ 1522 #define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ 1523 #define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ 1524 1525 /******************** Bit definition for ADC_TR1 register *******************/ 1526 #define ADC_TR1_LT1_Pos (0U) 1527 #define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ 1528 #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ 1529 #define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ 1530 #define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ 1531 #define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ 1532 #define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ 1533 #define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ 1534 #define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ 1535 #define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ 1536 #define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ 1537 #define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ 1538 #define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ 1539 #define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ 1540 #define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ 1541 1542 #define ADC_TR1_HT1_Pos (16U) 1543 #define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ 1544 #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ 1545 #define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ 1546 #define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ 1547 #define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ 1548 #define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ 1549 #define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ 1550 #define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ 1551 #define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ 1552 #define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ 1553 #define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ 1554 #define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ 1555 #define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ 1556 #define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ 1557 1558 /******************** Bit definition for ADC_TR2 register *******************/ 1559 #define ADC_TR2_LT2_Pos (0U) 1560 #define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ 1561 #define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ 1562 #define ADC_TR2_LT2_0 (0x01UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ 1563 #define ADC_TR2_LT2_1 (0x02UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ 1564 #define ADC_TR2_LT2_2 (0x04UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ 1565 #define ADC_TR2_LT2_3 (0x08UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ 1566 #define ADC_TR2_LT2_4 (0x10UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ 1567 #define ADC_TR2_LT2_5 (0x20UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ 1568 #define ADC_TR2_LT2_6 (0x40UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ 1569 #define ADC_TR2_LT2_7 (0x80UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ 1570 1571 #define ADC_TR2_HT2_Pos (16U) 1572 #define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ 1573 #define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ 1574 #define ADC_TR2_HT2_0 (0x01UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ 1575 #define ADC_TR2_HT2_1 (0x02UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ 1576 #define ADC_TR2_HT2_2 (0x04UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ 1577 #define ADC_TR2_HT2_3 (0x08UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ 1578 #define ADC_TR2_HT2_4 (0x10UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ 1579 #define ADC_TR2_HT2_5 (0x20UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ 1580 #define ADC_TR2_HT2_6 (0x40UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ 1581 #define ADC_TR2_HT2_7 (0x80UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ 1582 1583 /******************** Bit definition for ADC_TR3 register *******************/ 1584 #define ADC_TR3_LT3_Pos (0U) 1585 #define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ 1586 #define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ 1587 #define ADC_TR3_LT3_0 (0x01UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ 1588 #define ADC_TR3_LT3_1 (0x02UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ 1589 #define ADC_TR3_LT3_2 (0x04UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ 1590 #define ADC_TR3_LT3_3 (0x08UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ 1591 #define ADC_TR3_LT3_4 (0x10UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ 1592 #define ADC_TR3_LT3_5 (0x20UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ 1593 #define ADC_TR3_LT3_6 (0x40UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ 1594 #define ADC_TR3_LT3_7 (0x80UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ 1595 1596 #define ADC_TR3_HT3_Pos (16U) 1597 #define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ 1598 #define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ 1599 #define ADC_TR3_HT3_0 (0x01UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ 1600 #define ADC_TR3_HT3_1 (0x02UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ 1601 #define ADC_TR3_HT3_2 (0x04UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ 1602 #define ADC_TR3_HT3_3 (0x08UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ 1603 #define ADC_TR3_HT3_4 (0x10UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ 1604 #define ADC_TR3_HT3_5 (0x20UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ 1605 #define ADC_TR3_HT3_6 (0x40UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ 1606 #define ADC_TR3_HT3_7 (0x80UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ 1607 1608 /******************** Bit definition for ADC_SQR1 register ******************/ 1609 #define ADC_SQR1_L_Pos (0U) 1610 #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ 1611 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ 1612 #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ 1613 #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ 1614 #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ 1615 #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ 1616 1617 #define ADC_SQR1_SQ1_Pos (6U) 1618 #define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ 1619 #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ 1620 #define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ 1621 #define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ 1622 #define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ 1623 #define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ 1624 #define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ 1625 1626 #define ADC_SQR1_SQ2_Pos (12U) 1627 #define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ 1628 #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ 1629 #define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ 1630 #define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ 1631 #define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ 1632 #define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ 1633 #define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ 1634 1635 #define ADC_SQR1_SQ3_Pos (18U) 1636 #define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ 1637 #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ 1638 #define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ 1639 #define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ 1640 #define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ 1641 #define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ 1642 #define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ 1643 1644 #define ADC_SQR1_SQ4_Pos (24U) 1645 #define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ 1646 #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ 1647 #define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ 1648 #define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ 1649 #define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ 1650 #define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ 1651 #define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ 1652 1653 /******************** Bit definition for ADC_SQR2 register ******************/ 1654 #define ADC_SQR2_SQ5_Pos (0U) 1655 #define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ 1656 #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ 1657 #define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ 1658 #define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ 1659 #define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ 1660 #define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ 1661 #define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ 1662 1663 #define ADC_SQR2_SQ6_Pos (6U) 1664 #define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ 1665 #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ 1666 #define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ 1667 #define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ 1668 #define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ 1669 #define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ 1670 #define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ 1671 1672 #define ADC_SQR2_SQ7_Pos (12U) 1673 #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ 1674 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ 1675 #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ 1676 #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ 1677 #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ 1678 #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ 1679 #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ 1680 1681 #define ADC_SQR2_SQ8_Pos (18U) 1682 #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ 1683 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ 1684 #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ 1685 #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ 1686 #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ 1687 #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ 1688 #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ 1689 1690 #define ADC_SQR2_SQ9_Pos (24U) 1691 #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ 1692 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ 1693 #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ 1694 #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ 1695 #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ 1696 #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ 1697 #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ 1698 1699 /******************** Bit definition for ADC_SQR3 register ******************/ 1700 #define ADC_SQR3_SQ10_Pos (0U) 1701 #define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ 1702 #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ 1703 #define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ 1704 #define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ 1705 #define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ 1706 #define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ 1707 #define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ 1708 1709 #define ADC_SQR3_SQ11_Pos (6U) 1710 #define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ 1711 #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ 1712 #define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ 1713 #define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ 1714 #define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ 1715 #define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ 1716 #define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ 1717 1718 #define ADC_SQR3_SQ12_Pos (12U) 1719 #define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ 1720 #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ 1721 #define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ 1722 #define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ 1723 #define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ 1724 #define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ 1725 #define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ 1726 1727 #define ADC_SQR3_SQ13_Pos (18U) 1728 #define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ 1729 #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ 1730 #define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ 1731 #define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ 1732 #define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ 1733 #define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ 1734 #define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ 1735 1736 #define ADC_SQR3_SQ14_Pos (24U) 1737 #define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ 1738 #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ 1739 #define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ 1740 #define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ 1741 #define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ 1742 #define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ 1743 #define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ 1744 1745 /******************** Bit definition for ADC_SQR4 register ******************/ 1746 #define ADC_SQR4_SQ15_Pos (0U) 1747 #define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ 1748 #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ 1749 #define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ 1750 #define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ 1751 #define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ 1752 #define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ 1753 #define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ 1754 1755 #define ADC_SQR4_SQ16_Pos (6U) 1756 #define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ 1757 #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ 1758 #define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ 1759 #define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ 1760 #define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ 1761 #define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ 1762 #define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ 1763 1764 /******************** Bit definition for ADC_DR register ********************/ 1765 #define ADC_DR_RDATA_Pos (0U) 1766 #define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ 1767 #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ 1768 #define ADC_DR_RDATA_0 (0x0001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ 1769 #define ADC_DR_RDATA_1 (0x0002UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ 1770 #define ADC_DR_RDATA_2 (0x0004UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ 1771 #define ADC_DR_RDATA_3 (0x0008UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ 1772 #define ADC_DR_RDATA_4 (0x0010UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ 1773 #define ADC_DR_RDATA_5 (0x0020UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ 1774 #define ADC_DR_RDATA_6 (0x0040UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ 1775 #define ADC_DR_RDATA_7 (0x0080UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ 1776 #define ADC_DR_RDATA_8 (0x0100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ 1777 #define ADC_DR_RDATA_9 (0x0200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ 1778 #define ADC_DR_RDATA_10 (0x0400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ 1779 #define ADC_DR_RDATA_11 (0x0800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ 1780 #define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ 1781 #define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ 1782 #define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ 1783 #define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ 1784 1785 /******************** Bit definition for ADC_JSQR register ******************/ 1786 #define ADC_JSQR_JL_Pos (0U) 1787 #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ 1788 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ 1789 #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ 1790 #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ 1791 1792 #define ADC_JSQR_JEXTSEL_Pos (2U) 1793 #define ADC_JSQR_JEXTSEL_Msk (0xFUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ 1794 #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ 1795 #define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ 1796 #define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ 1797 #define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ 1798 #define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ 1799 1800 #define ADC_JSQR_JEXTEN_Pos (6U) 1801 #define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ 1802 #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ 1803 #define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ 1804 #define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ 1805 1806 #define ADC_JSQR_JSQ1_Pos (8U) 1807 #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ 1808 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ 1809 #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ 1810 #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ 1811 #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ 1812 #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ 1813 #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ 1814 1815 #define ADC_JSQR_JSQ2_Pos (14U) 1816 #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ 1817 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ 1818 #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ 1819 #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ 1820 #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ 1821 #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ 1822 #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ 1823 1824 #define ADC_JSQR_JSQ3_Pos (20U) 1825 #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ 1826 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ 1827 #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ 1828 #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ 1829 #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ 1830 #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ 1831 #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ 1832 1833 #define ADC_JSQR_JSQ4_Pos (26U) 1834 #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ 1835 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ 1836 #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ 1837 #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ 1838 #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ 1839 #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ 1840 #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ 1841 1842 /******************** Bit definition for ADC_OFR1 register ******************/ 1843 #define ADC_OFR1_OFFSET1_Pos (0U) 1844 #define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ 1845 #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ 1846 #define ADC_OFR1_OFFSET1_0 (0x001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ 1847 #define ADC_OFR1_OFFSET1_1 (0x002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ 1848 #define ADC_OFR1_OFFSET1_2 (0x004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ 1849 #define ADC_OFR1_OFFSET1_3 (0x008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ 1850 #define ADC_OFR1_OFFSET1_4 (0x010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ 1851 #define ADC_OFR1_OFFSET1_5 (0x020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ 1852 #define ADC_OFR1_OFFSET1_6 (0x040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ 1853 #define ADC_OFR1_OFFSET1_7 (0x080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ 1854 #define ADC_OFR1_OFFSET1_8 (0x100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ 1855 #define ADC_OFR1_OFFSET1_9 (0x200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ 1856 #define ADC_OFR1_OFFSET1_10 (0x400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ 1857 #define ADC_OFR1_OFFSET1_11 (0x800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ 1858 1859 #define ADC_OFR1_OFFSET1_CH_Pos (26U) 1860 #define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ 1861 #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ 1862 #define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ 1863 #define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ 1864 #define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ 1865 #define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ 1866 #define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ 1867 1868 #define ADC_OFR1_OFFSET1_EN_Pos (31U) 1869 #define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ 1870 #define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ 1871 1872 /******************** Bit definition for ADC_OFR2 register ******************/ 1873 #define ADC_OFR2_OFFSET2_Pos (0U) 1874 #define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ 1875 #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ 1876 #define ADC_OFR2_OFFSET2_0 (0x001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ 1877 #define ADC_OFR2_OFFSET2_1 (0x002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ 1878 #define ADC_OFR2_OFFSET2_2 (0x004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ 1879 #define ADC_OFR2_OFFSET2_3 (0x008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ 1880 #define ADC_OFR2_OFFSET2_4 (0x010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ 1881 #define ADC_OFR2_OFFSET2_5 (0x020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ 1882 #define ADC_OFR2_OFFSET2_6 (0x040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ 1883 #define ADC_OFR2_OFFSET2_7 (0x080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ 1884 #define ADC_OFR2_OFFSET2_8 (0x100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ 1885 #define ADC_OFR2_OFFSET2_9 (0x200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ 1886 #define ADC_OFR2_OFFSET2_10 (0x400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ 1887 #define ADC_OFR2_OFFSET2_11 (0x800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ 1888 1889 #define ADC_OFR2_OFFSET2_CH_Pos (26U) 1890 #define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ 1891 #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ 1892 #define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ 1893 #define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ 1894 #define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ 1895 #define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ 1896 #define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ 1897 1898 #define ADC_OFR2_OFFSET2_EN_Pos (31U) 1899 #define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ 1900 #define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ 1901 1902 /******************** Bit definition for ADC_OFR3 register ******************/ 1903 #define ADC_OFR3_OFFSET3_Pos (0U) 1904 #define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ 1905 #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ 1906 #define ADC_OFR3_OFFSET3_0 (0x001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ 1907 #define ADC_OFR3_OFFSET3_1 (0x002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ 1908 #define ADC_OFR3_OFFSET3_2 (0x004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ 1909 #define ADC_OFR3_OFFSET3_3 (0x008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ 1910 #define ADC_OFR3_OFFSET3_4 (0x010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ 1911 #define ADC_OFR3_OFFSET3_5 (0x020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ 1912 #define ADC_OFR3_OFFSET3_6 (0x040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ 1913 #define ADC_OFR3_OFFSET3_7 (0x080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ 1914 #define ADC_OFR3_OFFSET3_8 (0x100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ 1915 #define ADC_OFR3_OFFSET3_9 (0x200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ 1916 #define ADC_OFR3_OFFSET3_10 (0x400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ 1917 #define ADC_OFR3_OFFSET3_11 (0x800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ 1918 1919 #define ADC_OFR3_OFFSET3_CH_Pos (26U) 1920 #define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ 1921 #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ 1922 #define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ 1923 #define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ 1924 #define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ 1925 #define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ 1926 #define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ 1927 1928 #define ADC_OFR3_OFFSET3_EN_Pos (31U) 1929 #define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ 1930 #define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ 1931 1932 /******************** Bit definition for ADC_OFR4 register ******************/ 1933 #define ADC_OFR4_OFFSET4_Pos (0U) 1934 #define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ 1935 #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ 1936 #define ADC_OFR4_OFFSET4_0 (0x001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ 1937 #define ADC_OFR4_OFFSET4_1 (0x002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ 1938 #define ADC_OFR4_OFFSET4_2 (0x004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ 1939 #define ADC_OFR4_OFFSET4_3 (0x008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ 1940 #define ADC_OFR4_OFFSET4_4 (0x010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ 1941 #define ADC_OFR4_OFFSET4_5 (0x020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ 1942 #define ADC_OFR4_OFFSET4_6 (0x040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ 1943 #define ADC_OFR4_OFFSET4_7 (0x080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ 1944 #define ADC_OFR4_OFFSET4_8 (0x100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ 1945 #define ADC_OFR4_OFFSET4_9 (0x200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ 1946 #define ADC_OFR4_OFFSET4_10 (0x400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ 1947 #define ADC_OFR4_OFFSET4_11 (0x800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ 1948 1949 #define ADC_OFR4_OFFSET4_CH_Pos (26U) 1950 #define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ 1951 #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ 1952 #define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ 1953 #define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ 1954 #define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ 1955 #define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ 1956 #define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ 1957 1958 #define ADC_OFR4_OFFSET4_EN_Pos (31U) 1959 #define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ 1960 #define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ 1961 1962 /******************** Bit definition for ADC_JDR1 register ******************/ 1963 #define ADC_JDR1_JDATA_Pos (0U) 1964 #define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ 1965 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ 1966 #define ADC_JDR1_JDATA_0 (0x0001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ 1967 #define ADC_JDR1_JDATA_1 (0x0002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ 1968 #define ADC_JDR1_JDATA_2 (0x0004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ 1969 #define ADC_JDR1_JDATA_3 (0x0008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ 1970 #define ADC_JDR1_JDATA_4 (0x0010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ 1971 #define ADC_JDR1_JDATA_5 (0x0020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ 1972 #define ADC_JDR1_JDATA_6 (0x0040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ 1973 #define ADC_JDR1_JDATA_7 (0x0080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ 1974 #define ADC_JDR1_JDATA_8 (0x0100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ 1975 #define ADC_JDR1_JDATA_9 (0x0200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ 1976 #define ADC_JDR1_JDATA_10 (0x0400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ 1977 #define ADC_JDR1_JDATA_11 (0x0800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ 1978 #define ADC_JDR1_JDATA_12 (0x1000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ 1979 #define ADC_JDR1_JDATA_13 (0x2000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ 1980 #define ADC_JDR1_JDATA_14 (0x4000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ 1981 #define ADC_JDR1_JDATA_15 (0x8000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ 1982 1983 /******************** Bit definition for ADC_JDR2 register ******************/ 1984 #define ADC_JDR2_JDATA_Pos (0U) 1985 #define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ 1986 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ 1987 #define ADC_JDR2_JDATA_0 (0x0001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ 1988 #define ADC_JDR2_JDATA_1 (0x0002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ 1989 #define ADC_JDR2_JDATA_2 (0x0004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ 1990 #define ADC_JDR2_JDATA_3 (0x0008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ 1991 #define ADC_JDR2_JDATA_4 (0x0010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ 1992 #define ADC_JDR2_JDATA_5 (0x0020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ 1993 #define ADC_JDR2_JDATA_6 (0x0040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ 1994 #define ADC_JDR2_JDATA_7 (0x0080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ 1995 #define ADC_JDR2_JDATA_8 (0x0100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ 1996 #define ADC_JDR2_JDATA_9 (0x0200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ 1997 #define ADC_JDR2_JDATA_10 (0x0400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ 1998 #define ADC_JDR2_JDATA_11 (0x0800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ 1999 #define ADC_JDR2_JDATA_12 (0x1000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ 2000 #define ADC_JDR2_JDATA_13 (0x2000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ 2001 #define ADC_JDR2_JDATA_14 (0x4000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ 2002 #define ADC_JDR2_JDATA_15 (0x8000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ 2003 2004 /******************** Bit definition for ADC_JDR3 register ******************/ 2005 #define ADC_JDR3_JDATA_Pos (0U) 2006 #define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ 2007 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ 2008 #define ADC_JDR3_JDATA_0 (0x0001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ 2009 #define ADC_JDR3_JDATA_1 (0x0002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ 2010 #define ADC_JDR3_JDATA_2 (0x0004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ 2011 #define ADC_JDR3_JDATA_3 (0x0008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ 2012 #define ADC_JDR3_JDATA_4 (0x0010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ 2013 #define ADC_JDR3_JDATA_5 (0x0020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ 2014 #define ADC_JDR3_JDATA_6 (0x0040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ 2015 #define ADC_JDR3_JDATA_7 (0x0080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ 2016 #define ADC_JDR3_JDATA_8 (0x0100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ 2017 #define ADC_JDR3_JDATA_9 (0x0200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ 2018 #define ADC_JDR3_JDATA_10 (0x0400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ 2019 #define ADC_JDR3_JDATA_11 (0x0800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ 2020 #define ADC_JDR3_JDATA_12 (0x1000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ 2021 #define ADC_JDR3_JDATA_13 (0x2000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ 2022 #define ADC_JDR3_JDATA_14 (0x4000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ 2023 #define ADC_JDR3_JDATA_15 (0x8000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ 2024 2025 /******************** Bit definition for ADC_JDR4 register ******************/ 2026 #define ADC_JDR4_JDATA_Pos (0U) 2027 #define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ 2028 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ 2029 #define ADC_JDR4_JDATA_0 (0x0001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ 2030 #define ADC_JDR4_JDATA_1 (0x0002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ 2031 #define ADC_JDR4_JDATA_2 (0x0004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ 2032 #define ADC_JDR4_JDATA_3 (0x0008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ 2033 #define ADC_JDR4_JDATA_4 (0x0010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ 2034 #define ADC_JDR4_JDATA_5 (0x0020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ 2035 #define ADC_JDR4_JDATA_6 (0x0040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ 2036 #define ADC_JDR4_JDATA_7 (0x0080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ 2037 #define ADC_JDR4_JDATA_8 (0x0100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ 2038 #define ADC_JDR4_JDATA_9 (0x0200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ 2039 #define ADC_JDR4_JDATA_10 (0x0400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ 2040 #define ADC_JDR4_JDATA_11 (0x0800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ 2041 #define ADC_JDR4_JDATA_12 (0x1000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ 2042 #define ADC_JDR4_JDATA_13 (0x2000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ 2043 #define ADC_JDR4_JDATA_14 (0x4000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ 2044 #define ADC_JDR4_JDATA_15 (0x8000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ 2045 2046 /******************** Bit definition for ADC_AWD2CR register ****************/ 2047 #define ADC_AWD2CR_AWD2CH_Pos (0U) 2048 #define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ 2049 #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ 2050 #define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ 2051 #define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ 2052 #define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ 2053 #define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ 2054 #define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ 2055 #define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ 2056 #define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ 2057 #define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ 2058 #define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ 2059 #define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ 2060 #define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ 2061 #define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ 2062 #define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ 2063 #define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ 2064 #define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ 2065 #define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ 2066 #define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ 2067 #define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ 2068 #define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ 2069 2070 /******************** Bit definition for ADC_AWD3CR register ****************/ 2071 #define ADC_AWD3CR_AWD3CH_Pos (0U) 2072 #define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ 2073 #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ 2074 #define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ 2075 #define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ 2076 #define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ 2077 #define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ 2078 #define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ 2079 #define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ 2080 #define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ 2081 #define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ 2082 #define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ 2083 #define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ 2084 #define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ 2085 #define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ 2086 #define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ 2087 #define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ 2088 #define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ 2089 #define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ 2090 #define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ 2091 #define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ 2092 #define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ 2093 2094 /******************** Bit definition for ADC_DIFSEL register ****************/ 2095 #define ADC_DIFSEL_DIFSEL_Pos (0U) 2096 #define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ 2097 #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ 2098 #define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ 2099 #define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ 2100 #define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ 2101 #define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ 2102 #define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ 2103 #define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ 2104 #define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ 2105 #define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ 2106 #define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ 2107 #define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ 2108 #define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ 2109 #define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ 2110 #define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ 2111 #define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ 2112 #define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ 2113 #define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ 2114 #define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ 2115 #define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ 2116 #define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ 2117 2118 /******************** Bit definition for ADC_CALFACT register ***************/ 2119 #define ADC_CALFACT_CALFACT_S_Pos (0U) 2120 #define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ 2121 #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ 2122 #define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ 2123 #define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ 2124 #define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ 2125 #define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ 2126 #define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ 2127 #define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ 2128 #define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ 2129 2130 #define ADC_CALFACT_CALFACT_D_Pos (16U) 2131 #define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ 2132 #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ 2133 #define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ 2134 #define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ 2135 #define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ 2136 #define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ 2137 #define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ 2138 #define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ 2139 #define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ 2140 2141 /************************* ADC Common registers *****************************/ 2142 /******************** Bit definition for ADC_CCR register *******************/ 2143 #define ADC_CCR_CKMODE_Pos (16U) 2144 #define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ 2145 #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ 2146 #define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ 2147 #define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ 2148 2149 #define ADC_CCR_PRESC_Pos (18U) 2150 #define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ 2151 #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ 2152 #define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ 2153 #define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ 2154 #define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ 2155 #define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ 2156 2157 #define ADC_CCR_VREFEN_Pos (22U) 2158 #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ 2159 #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ 2160 #define ADC_CCR_TSEN_Pos (23U) 2161 #define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ 2162 #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ 2163 #define ADC_CCR_VBATEN_Pos (24U) 2164 #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ 2165 #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ 2166 2167 /******************************************************************************/ 2168 /* */ 2169 /* Controller Area Network */ 2170 /* */ 2171 /******************************************************************************/ 2172 /*!<CAN control and status registers */ 2173 /******************* Bit definition for CAN_MCR register ********************/ 2174 #define CAN_MCR_INRQ_Pos (0U) 2175 #define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */ 2176 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */ 2177 #define CAN_MCR_SLEEP_Pos (1U) 2178 #define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */ 2179 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */ 2180 #define CAN_MCR_TXFP_Pos (2U) 2181 #define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */ 2182 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */ 2183 #define CAN_MCR_RFLM_Pos (3U) 2184 #define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */ 2185 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */ 2186 #define CAN_MCR_NART_Pos (4U) 2187 #define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos) /*!< 0x00000010 */ 2188 #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */ 2189 #define CAN_MCR_AWUM_Pos (5U) 2190 #define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */ 2191 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */ 2192 #define CAN_MCR_ABOM_Pos (6U) 2193 #define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */ 2194 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */ 2195 #define CAN_MCR_TTCM_Pos (7U) 2196 #define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */ 2197 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */ 2198 #define CAN_MCR_RESET_Pos (15U) 2199 #define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos) /*!< 0x00008000 */ 2200 #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */ 2201 2202 /******************* Bit definition for CAN_MSR register ********************/ 2203 #define CAN_MSR_INAK_Pos (0U) 2204 #define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos) /*!< 0x00000001 */ 2205 #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */ 2206 #define CAN_MSR_SLAK_Pos (1U) 2207 #define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */ 2208 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */ 2209 #define CAN_MSR_ERRI_Pos (2U) 2210 #define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */ 2211 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */ 2212 #define CAN_MSR_WKUI_Pos (3U) 2213 #define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */ 2214 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */ 2215 #define CAN_MSR_SLAKI_Pos (4U) 2216 #define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */ 2217 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */ 2218 #define CAN_MSR_TXM_Pos (8U) 2219 #define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos) /*!< 0x00000100 */ 2220 #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */ 2221 #define CAN_MSR_RXM_Pos (9U) 2222 #define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos) /*!< 0x00000200 */ 2223 #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */ 2224 #define CAN_MSR_SAMP_Pos (10U) 2225 #define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */ 2226 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */ 2227 #define CAN_MSR_RX_Pos (11U) 2228 #define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos) /*!< 0x00000800 */ 2229 #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */ 2230 2231 /******************* Bit definition for CAN_TSR register ********************/ 2232 #define CAN_TSR_RQCP0_Pos (0U) 2233 #define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */ 2234 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */ 2235 #define CAN_TSR_TXOK0_Pos (1U) 2236 #define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */ 2237 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */ 2238 #define CAN_TSR_ALST0_Pos (2U) 2239 #define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */ 2240 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */ 2241 #define CAN_TSR_TERR0_Pos (3U) 2242 #define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */ 2243 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */ 2244 #define CAN_TSR_ABRQ0_Pos (7U) 2245 #define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */ 2246 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */ 2247 #define CAN_TSR_RQCP1_Pos (8U) 2248 #define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */ 2249 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */ 2250 #define CAN_TSR_TXOK1_Pos (9U) 2251 #define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */ 2252 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */ 2253 #define CAN_TSR_ALST1_Pos (10U) 2254 #define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */ 2255 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */ 2256 #define CAN_TSR_TERR1_Pos (11U) 2257 #define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */ 2258 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */ 2259 #define CAN_TSR_ABRQ1_Pos (15U) 2260 #define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */ 2261 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */ 2262 #define CAN_TSR_RQCP2_Pos (16U) 2263 #define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */ 2264 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */ 2265 #define CAN_TSR_TXOK2_Pos (17U) 2266 #define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */ 2267 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */ 2268 #define CAN_TSR_ALST2_Pos (18U) 2269 #define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */ 2270 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */ 2271 #define CAN_TSR_TERR2_Pos (19U) 2272 #define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */ 2273 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */ 2274 #define CAN_TSR_ABRQ2_Pos (23U) 2275 #define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */ 2276 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */ 2277 #define CAN_TSR_CODE_Pos (24U) 2278 #define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos) /*!< 0x03000000 */ 2279 #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */ 2280 2281 #define CAN_TSR_TME_Pos (26U) 2282 #define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos) /*!< 0x1C000000 */ 2283 #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */ 2284 #define CAN_TSR_TME0_Pos (26U) 2285 #define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos) /*!< 0x04000000 */ 2286 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */ 2287 #define CAN_TSR_TME1_Pos (27U) 2288 #define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos) /*!< 0x08000000 */ 2289 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */ 2290 #define CAN_TSR_TME2_Pos (28U) 2291 #define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos) /*!< 0x10000000 */ 2292 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */ 2293 2294 #define CAN_TSR_LOW_Pos (29U) 2295 #define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */ 2296 #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */ 2297 #define CAN_TSR_LOW0_Pos (29U) 2298 #define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */ 2299 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */ 2300 #define CAN_TSR_LOW1_Pos (30U) 2301 #define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */ 2302 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */ 2303 #define CAN_TSR_LOW2_Pos (31U) 2304 #define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */ 2305 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */ 2306 2307 /******************* Bit definition for CAN_RF0R register *******************/ 2308 #define CAN_RF0R_FMP0_Pos (0U) 2309 #define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */ 2310 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */ 2311 #define CAN_RF0R_FULL0_Pos (3U) 2312 #define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */ 2313 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */ 2314 #define CAN_RF0R_FOVR0_Pos (4U) 2315 #define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */ 2316 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */ 2317 #define CAN_RF0R_RFOM0_Pos (5U) 2318 #define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */ 2319 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */ 2320 2321 /******************* Bit definition for CAN_RF1R register *******************/ 2322 #define CAN_RF1R_FMP1_Pos (0U) 2323 #define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */ 2324 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */ 2325 #define CAN_RF1R_FULL1_Pos (3U) 2326 #define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */ 2327 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */ 2328 #define CAN_RF1R_FOVR1_Pos (4U) 2329 #define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */ 2330 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */ 2331 #define CAN_RF1R_RFOM1_Pos (5U) 2332 #define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */ 2333 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */ 2334 2335 /******************** Bit definition for CAN_IER register *******************/ 2336 #define CAN_IER_TMEIE_Pos (0U) 2337 #define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */ 2338 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */ 2339 #define CAN_IER_FMPIE0_Pos (1U) 2340 #define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */ 2341 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */ 2342 #define CAN_IER_FFIE0_Pos (2U) 2343 #define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */ 2344 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */ 2345 #define CAN_IER_FOVIE0_Pos (3U) 2346 #define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */ 2347 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */ 2348 #define CAN_IER_FMPIE1_Pos (4U) 2349 #define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */ 2350 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */ 2351 #define CAN_IER_FFIE1_Pos (5U) 2352 #define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */ 2353 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */ 2354 #define CAN_IER_FOVIE1_Pos (6U) 2355 #define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */ 2356 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */ 2357 #define CAN_IER_EWGIE_Pos (8U) 2358 #define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */ 2359 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */ 2360 #define CAN_IER_EPVIE_Pos (9U) 2361 #define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */ 2362 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */ 2363 #define CAN_IER_BOFIE_Pos (10U) 2364 #define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */ 2365 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */ 2366 #define CAN_IER_LECIE_Pos (11U) 2367 #define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos) /*!< 0x00000800 */ 2368 #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */ 2369 #define CAN_IER_ERRIE_Pos (15U) 2370 #define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */ 2371 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */ 2372 #define CAN_IER_WKUIE_Pos (16U) 2373 #define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */ 2374 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */ 2375 #define CAN_IER_SLKIE_Pos (17U) 2376 #define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */ 2377 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */ 2378 2379 /******************** Bit definition for CAN_ESR register *******************/ 2380 #define CAN_ESR_EWGF_Pos (0U) 2381 #define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */ 2382 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */ 2383 #define CAN_ESR_EPVF_Pos (1U) 2384 #define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */ 2385 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */ 2386 #define CAN_ESR_BOFF_Pos (2U) 2387 #define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */ 2388 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */ 2389 2390 #define CAN_ESR_LEC_Pos (4U) 2391 #define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos) /*!< 0x00000070 */ 2392 #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */ 2393 #define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos) /*!< 0x00000010 */ 2394 #define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos) /*!< 0x00000020 */ 2395 #define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos) /*!< 0x00000040 */ 2396 2397 #define CAN_ESR_TEC_Pos (16U) 2398 #define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */ 2399 #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */ 2400 #define CAN_ESR_REC_Pos (24U) 2401 #define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos) /*!< 0xFF000000 */ 2402 #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */ 2403 2404 /******************* Bit definition for CAN_BTR register ********************/ 2405 #define CAN_BTR_BRP_Pos (0U) 2406 #define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos) /*!< 0x000003FF */ 2407 #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */ 2408 #define CAN_BTR_TS1_Pos (16U) 2409 #define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */ 2410 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */ 2411 #define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos) /*!< 0x00010000 */ 2412 #define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos) /*!< 0x00020000 */ 2413 #define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos) /*!< 0x00040000 */ 2414 #define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos) /*!< 0x00080000 */ 2415 #define CAN_BTR_TS2_Pos (20U) 2416 #define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos) /*!< 0x00700000 */ 2417 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */ 2418 #define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos) /*!< 0x00100000 */ 2419 #define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos) /*!< 0x00200000 */ 2420 #define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos) /*!< 0x00400000 */ 2421 #define CAN_BTR_SJW_Pos (24U) 2422 #define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos) /*!< 0x03000000 */ 2423 #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */ 2424 #define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos) /*!< 0x01000000 */ 2425 #define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos) /*!< 0x02000000 */ 2426 #define CAN_BTR_LBKM_Pos (30U) 2427 #define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */ 2428 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */ 2429 #define CAN_BTR_SILM_Pos (31U) 2430 #define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos) /*!< 0x80000000 */ 2431 #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */ 2432 2433 /*!<Mailbox registers */ 2434 /****************** Bit definition for CAN_TI0R register ********************/ 2435 #define CAN_TI0R_TXRQ_Pos (0U) 2436 #define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */ 2437 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */ 2438 #define CAN_TI0R_RTR_Pos (1U) 2439 #define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */ 2440 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */ 2441 #define CAN_TI0R_IDE_Pos (2U) 2442 #define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */ 2443 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */ 2444 #define CAN_TI0R_EXID_Pos (3U) 2445 #define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */ 2446 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */ 2447 #define CAN_TI0R_STID_Pos (21U) 2448 #define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */ 2449 #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */ 2450 2451 /****************** Bit definition for CAN_TDT0R register *******************/ 2452 #define CAN_TDT0R_DLC_Pos (0U) 2453 #define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */ 2454 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */ 2455 #define CAN_TDT0R_TGT_Pos (8U) 2456 #define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */ 2457 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */ 2458 #define CAN_TDT0R_TIME_Pos (16U) 2459 #define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */ 2460 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */ 2461 2462 /****************** Bit definition for CAN_TDL0R register *******************/ 2463 #define CAN_TDL0R_DATA0_Pos (0U) 2464 #define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */ 2465 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */ 2466 #define CAN_TDL0R_DATA1_Pos (8U) 2467 #define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */ 2468 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */ 2469 #define CAN_TDL0R_DATA2_Pos (16U) 2470 #define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */ 2471 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */ 2472 #define CAN_TDL0R_DATA3_Pos (24U) 2473 #define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */ 2474 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */ 2475 2476 /****************** Bit definition for CAN_TDH0R register *******************/ 2477 #define CAN_TDH0R_DATA4_Pos (0U) 2478 #define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */ 2479 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */ 2480 #define CAN_TDH0R_DATA5_Pos (8U) 2481 #define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */ 2482 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */ 2483 #define CAN_TDH0R_DATA6_Pos (16U) 2484 #define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */ 2485 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */ 2486 #define CAN_TDH0R_DATA7_Pos (24U) 2487 #define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */ 2488 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */ 2489 2490 /******************* Bit definition for CAN_TI1R register *******************/ 2491 #define CAN_TI1R_TXRQ_Pos (0U) 2492 #define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */ 2493 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */ 2494 #define CAN_TI1R_RTR_Pos (1U) 2495 #define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */ 2496 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */ 2497 #define CAN_TI1R_IDE_Pos (2U) 2498 #define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */ 2499 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */ 2500 #define CAN_TI1R_EXID_Pos (3U) 2501 #define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */ 2502 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */ 2503 #define CAN_TI1R_STID_Pos (21U) 2504 #define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */ 2505 #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */ 2506 2507 /******************* Bit definition for CAN_TDT1R register ******************/ 2508 #define CAN_TDT1R_DLC_Pos (0U) 2509 #define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */ 2510 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */ 2511 #define CAN_TDT1R_TGT_Pos (8U) 2512 #define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */ 2513 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */ 2514 #define CAN_TDT1R_TIME_Pos (16U) 2515 #define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */ 2516 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */ 2517 2518 /******************* Bit definition for CAN_TDL1R register ******************/ 2519 #define CAN_TDL1R_DATA0_Pos (0U) 2520 #define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */ 2521 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */ 2522 #define CAN_TDL1R_DATA1_Pos (8U) 2523 #define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */ 2524 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */ 2525 #define CAN_TDL1R_DATA2_Pos (16U) 2526 #define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */ 2527 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */ 2528 #define CAN_TDL1R_DATA3_Pos (24U) 2529 #define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */ 2530 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */ 2531 2532 /******************* Bit definition for CAN_TDH1R register ******************/ 2533 #define CAN_TDH1R_DATA4_Pos (0U) 2534 #define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */ 2535 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */ 2536 #define CAN_TDH1R_DATA5_Pos (8U) 2537 #define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */ 2538 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */ 2539 #define CAN_TDH1R_DATA6_Pos (16U) 2540 #define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */ 2541 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */ 2542 #define CAN_TDH1R_DATA7_Pos (24U) 2543 #define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */ 2544 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */ 2545 2546 /******************* Bit definition for CAN_TI2R register *******************/ 2547 #define CAN_TI2R_TXRQ_Pos (0U) 2548 #define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */ 2549 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */ 2550 #define CAN_TI2R_RTR_Pos (1U) 2551 #define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */ 2552 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */ 2553 #define CAN_TI2R_IDE_Pos (2U) 2554 #define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */ 2555 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */ 2556 #define CAN_TI2R_EXID_Pos (3U) 2557 #define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */ 2558 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */ 2559 #define CAN_TI2R_STID_Pos (21U) 2560 #define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */ 2561 #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */ 2562 2563 /******************* Bit definition for CAN_TDT2R register ******************/ 2564 #define CAN_TDT2R_DLC_Pos (0U) 2565 #define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */ 2566 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */ 2567 #define CAN_TDT2R_TGT_Pos (8U) 2568 #define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */ 2569 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */ 2570 #define CAN_TDT2R_TIME_Pos (16U) 2571 #define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */ 2572 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */ 2573 2574 /******************* Bit definition for CAN_TDL2R register ******************/ 2575 #define CAN_TDL2R_DATA0_Pos (0U) 2576 #define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */ 2577 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */ 2578 #define CAN_TDL2R_DATA1_Pos (8U) 2579 #define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */ 2580 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */ 2581 #define CAN_TDL2R_DATA2_Pos (16U) 2582 #define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */ 2583 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */ 2584 #define CAN_TDL2R_DATA3_Pos (24U) 2585 #define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */ 2586 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */ 2587 2588 /******************* Bit definition for CAN_TDH2R register ******************/ 2589 #define CAN_TDH2R_DATA4_Pos (0U) 2590 #define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */ 2591 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */ 2592 #define CAN_TDH2R_DATA5_Pos (8U) 2593 #define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */ 2594 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */ 2595 #define CAN_TDH2R_DATA6_Pos (16U) 2596 #define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */ 2597 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */ 2598 #define CAN_TDH2R_DATA7_Pos (24U) 2599 #define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */ 2600 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */ 2601 2602 /******************* Bit definition for CAN_RI0R register *******************/ 2603 #define CAN_RI0R_RTR_Pos (1U) 2604 #define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */ 2605 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */ 2606 #define CAN_RI0R_IDE_Pos (2U) 2607 #define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */ 2608 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */ 2609 #define CAN_RI0R_EXID_Pos (3U) 2610 #define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */ 2611 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */ 2612 #define CAN_RI0R_STID_Pos (21U) 2613 #define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */ 2614 #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */ 2615 2616 /******************* Bit definition for CAN_RDT0R register ******************/ 2617 #define CAN_RDT0R_DLC_Pos (0U) 2618 #define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */ 2619 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */ 2620 #define CAN_RDT0R_FMI_Pos (8U) 2621 #define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */ 2622 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */ 2623 #define CAN_RDT0R_TIME_Pos (16U) 2624 #define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */ 2625 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */ 2626 2627 /******************* Bit definition for CAN_RDL0R register ******************/ 2628 #define CAN_RDL0R_DATA0_Pos (0U) 2629 #define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */ 2630 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */ 2631 #define CAN_RDL0R_DATA1_Pos (8U) 2632 #define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */ 2633 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */ 2634 #define CAN_RDL0R_DATA2_Pos (16U) 2635 #define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */ 2636 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */ 2637 #define CAN_RDL0R_DATA3_Pos (24U) 2638 #define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */ 2639 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */ 2640 2641 /******************* Bit definition for CAN_RDH0R register ******************/ 2642 #define CAN_RDH0R_DATA4_Pos (0U) 2643 #define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */ 2644 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */ 2645 #define CAN_RDH0R_DATA5_Pos (8U) 2646 #define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */ 2647 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */ 2648 #define CAN_RDH0R_DATA6_Pos (16U) 2649 #define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */ 2650 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */ 2651 #define CAN_RDH0R_DATA7_Pos (24U) 2652 #define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */ 2653 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */ 2654 2655 /******************* Bit definition for CAN_RI1R register *******************/ 2656 #define CAN_RI1R_RTR_Pos (1U) 2657 #define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */ 2658 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */ 2659 #define CAN_RI1R_IDE_Pos (2U) 2660 #define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */ 2661 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */ 2662 #define CAN_RI1R_EXID_Pos (3U) 2663 #define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */ 2664 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */ 2665 #define CAN_RI1R_STID_Pos (21U) 2666 #define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */ 2667 #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */ 2668 2669 /******************* Bit definition for CAN_RDT1R register ******************/ 2670 #define CAN_RDT1R_DLC_Pos (0U) 2671 #define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */ 2672 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */ 2673 #define CAN_RDT1R_FMI_Pos (8U) 2674 #define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */ 2675 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */ 2676 #define CAN_RDT1R_TIME_Pos (16U) 2677 #define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */ 2678 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */ 2679 2680 /******************* Bit definition for CAN_RDL1R register ******************/ 2681 #define CAN_RDL1R_DATA0_Pos (0U) 2682 #define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */ 2683 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */ 2684 #define CAN_RDL1R_DATA1_Pos (8U) 2685 #define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */ 2686 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */ 2687 #define CAN_RDL1R_DATA2_Pos (16U) 2688 #define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */ 2689 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */ 2690 #define CAN_RDL1R_DATA3_Pos (24U) 2691 #define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */ 2692 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */ 2693 2694 /******************* Bit definition for CAN_RDH1R register ******************/ 2695 #define CAN_RDH1R_DATA4_Pos (0U) 2696 #define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */ 2697 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */ 2698 #define CAN_RDH1R_DATA5_Pos (8U) 2699 #define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */ 2700 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */ 2701 #define CAN_RDH1R_DATA6_Pos (16U) 2702 #define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */ 2703 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */ 2704 #define CAN_RDH1R_DATA7_Pos (24U) 2705 #define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */ 2706 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */ 2707 2708 /*!<CAN filter registers */ 2709 /******************* Bit definition for CAN_FMR register ********************/ 2710 #define CAN_FMR_FINIT_Pos (0U) 2711 #define CAN_FMR_FINIT_Msk (0x1UL << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */ 2712 #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */ 2713 2714 /******************* Bit definition for CAN_FM1R register *******************/ 2715 #define CAN_FM1R_FBM_Pos (0U) 2716 #define CAN_FM1R_FBM_Msk (0x3FFFUL << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */ 2717 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */ 2718 #define CAN_FM1R_FBM0_Pos (0U) 2719 #define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */ 2720 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */ 2721 #define CAN_FM1R_FBM1_Pos (1U) 2722 #define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */ 2723 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */ 2724 #define CAN_FM1R_FBM2_Pos (2U) 2725 #define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */ 2726 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */ 2727 #define CAN_FM1R_FBM3_Pos (3U) 2728 #define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */ 2729 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */ 2730 #define CAN_FM1R_FBM4_Pos (4U) 2731 #define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */ 2732 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */ 2733 #define CAN_FM1R_FBM5_Pos (5U) 2734 #define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */ 2735 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */ 2736 #define CAN_FM1R_FBM6_Pos (6U) 2737 #define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */ 2738 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */ 2739 #define CAN_FM1R_FBM7_Pos (7U) 2740 #define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */ 2741 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */ 2742 #define CAN_FM1R_FBM8_Pos (8U) 2743 #define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */ 2744 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */ 2745 #define CAN_FM1R_FBM9_Pos (9U) 2746 #define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */ 2747 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */ 2748 #define CAN_FM1R_FBM10_Pos (10U) 2749 #define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */ 2750 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */ 2751 #define CAN_FM1R_FBM11_Pos (11U) 2752 #define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */ 2753 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */ 2754 #define CAN_FM1R_FBM12_Pos (12U) 2755 #define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */ 2756 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */ 2757 #define CAN_FM1R_FBM13_Pos (13U) 2758 #define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */ 2759 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */ 2760 2761 /******************* Bit definition for CAN_FS1R register *******************/ 2762 #define CAN_FS1R_FSC_Pos (0U) 2763 #define CAN_FS1R_FSC_Msk (0x3FFFUL << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */ 2764 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */ 2765 #define CAN_FS1R_FSC0_Pos (0U) 2766 #define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */ 2767 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */ 2768 #define CAN_FS1R_FSC1_Pos (1U) 2769 #define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */ 2770 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */ 2771 #define CAN_FS1R_FSC2_Pos (2U) 2772 #define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */ 2773 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */ 2774 #define CAN_FS1R_FSC3_Pos (3U) 2775 #define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */ 2776 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */ 2777 #define CAN_FS1R_FSC4_Pos (4U) 2778 #define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */ 2779 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */ 2780 #define CAN_FS1R_FSC5_Pos (5U) 2781 #define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */ 2782 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */ 2783 #define CAN_FS1R_FSC6_Pos (6U) 2784 #define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */ 2785 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */ 2786 #define CAN_FS1R_FSC7_Pos (7U) 2787 #define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */ 2788 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */ 2789 #define CAN_FS1R_FSC8_Pos (8U) 2790 #define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */ 2791 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */ 2792 #define CAN_FS1R_FSC9_Pos (9U) 2793 #define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */ 2794 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */ 2795 #define CAN_FS1R_FSC10_Pos (10U) 2796 #define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */ 2797 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */ 2798 #define CAN_FS1R_FSC11_Pos (11U) 2799 #define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */ 2800 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */ 2801 #define CAN_FS1R_FSC12_Pos (12U) 2802 #define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */ 2803 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */ 2804 #define CAN_FS1R_FSC13_Pos (13U) 2805 #define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */ 2806 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */ 2807 2808 /****************** Bit definition for CAN_FFA1R register *******************/ 2809 #define CAN_FFA1R_FFA_Pos (0U) 2810 #define CAN_FFA1R_FFA_Msk (0x3FFFUL << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */ 2811 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */ 2812 #define CAN_FFA1R_FFA0_Pos (0U) 2813 #define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */ 2814 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment for Filter 0 */ 2815 #define CAN_FFA1R_FFA1_Pos (1U) 2816 #define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */ 2817 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment for Filter 1 */ 2818 #define CAN_FFA1R_FFA2_Pos (2U) 2819 #define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */ 2820 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment for Filter 2 */ 2821 #define CAN_FFA1R_FFA3_Pos (3U) 2822 #define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */ 2823 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment for Filter 3 */ 2824 #define CAN_FFA1R_FFA4_Pos (4U) 2825 #define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */ 2826 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment for Filter 4 */ 2827 #define CAN_FFA1R_FFA5_Pos (5U) 2828 #define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */ 2829 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment for Filter 5 */ 2830 #define CAN_FFA1R_FFA6_Pos (6U) 2831 #define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */ 2832 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment for Filter 6 */ 2833 #define CAN_FFA1R_FFA7_Pos (7U) 2834 #define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */ 2835 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment for Filter 7 */ 2836 #define CAN_FFA1R_FFA8_Pos (8U) 2837 #define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */ 2838 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment for Filter 8 */ 2839 #define CAN_FFA1R_FFA9_Pos (9U) 2840 #define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */ 2841 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment for Filter 9 */ 2842 #define CAN_FFA1R_FFA10_Pos (10U) 2843 #define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */ 2844 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment for Filter 10 */ 2845 #define CAN_FFA1R_FFA11_Pos (11U) 2846 #define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */ 2847 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment for Filter 11 */ 2848 #define CAN_FFA1R_FFA12_Pos (12U) 2849 #define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */ 2850 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment for Filter 12 */ 2851 #define CAN_FFA1R_FFA13_Pos (13U) 2852 #define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */ 2853 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment for Filter 13 */ 2854 2855 /******************* Bit definition for CAN_FA1R register *******************/ 2856 #define CAN_FA1R_FACT_Pos (0U) 2857 #define CAN_FA1R_FACT_Msk (0x3FFFUL << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */ 2858 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */ 2859 #define CAN_FA1R_FACT0_Pos (0U) 2860 #define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */ 2861 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter 0 Active */ 2862 #define CAN_FA1R_FACT1_Pos (1U) 2863 #define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */ 2864 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter 1 Active */ 2865 #define CAN_FA1R_FACT2_Pos (2U) 2866 #define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */ 2867 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter 2 Active */ 2868 #define CAN_FA1R_FACT3_Pos (3U) 2869 #define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */ 2870 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter 3 Active */ 2871 #define CAN_FA1R_FACT4_Pos (4U) 2872 #define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */ 2873 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter 4 Active */ 2874 #define CAN_FA1R_FACT5_Pos (5U) 2875 #define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */ 2876 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter 5 Active */ 2877 #define CAN_FA1R_FACT6_Pos (6U) 2878 #define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */ 2879 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter 6 Active */ 2880 #define CAN_FA1R_FACT7_Pos (7U) 2881 #define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */ 2882 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter 7 Active */ 2883 #define CAN_FA1R_FACT8_Pos (8U) 2884 #define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */ 2885 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter 8 Active */ 2886 #define CAN_FA1R_FACT9_Pos (9U) 2887 #define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */ 2888 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter 9 Active */ 2889 #define CAN_FA1R_FACT10_Pos (10U) 2890 #define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */ 2891 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter 10 Active */ 2892 #define CAN_FA1R_FACT11_Pos (11U) 2893 #define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */ 2894 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter 11 Active */ 2895 #define CAN_FA1R_FACT12_Pos (12U) 2896 #define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */ 2897 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter 12 Active */ 2898 #define CAN_FA1R_FACT13_Pos (13U) 2899 #define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */ 2900 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter 13 Active */ 2901 2902 /******************* Bit definition for CAN_F0R1 register *******************/ 2903 #define CAN_F0R1_FB0_Pos (0U) 2904 #define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */ 2905 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */ 2906 #define CAN_F0R1_FB1_Pos (1U) 2907 #define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */ 2908 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */ 2909 #define CAN_F0R1_FB2_Pos (2U) 2910 #define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */ 2911 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */ 2912 #define CAN_F0R1_FB3_Pos (3U) 2913 #define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */ 2914 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */ 2915 #define CAN_F0R1_FB4_Pos (4U) 2916 #define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */ 2917 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */ 2918 #define CAN_F0R1_FB5_Pos (5U) 2919 #define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */ 2920 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */ 2921 #define CAN_F0R1_FB6_Pos (6U) 2922 #define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */ 2923 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */ 2924 #define CAN_F0R1_FB7_Pos (7U) 2925 #define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */ 2926 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */ 2927 #define CAN_F0R1_FB8_Pos (8U) 2928 #define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */ 2929 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */ 2930 #define CAN_F0R1_FB9_Pos (9U) 2931 #define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */ 2932 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */ 2933 #define CAN_F0R1_FB10_Pos (10U) 2934 #define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */ 2935 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */ 2936 #define CAN_F0R1_FB11_Pos (11U) 2937 #define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */ 2938 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */ 2939 #define CAN_F0R1_FB12_Pos (12U) 2940 #define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */ 2941 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */ 2942 #define CAN_F0R1_FB13_Pos (13U) 2943 #define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */ 2944 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */ 2945 #define CAN_F0R1_FB14_Pos (14U) 2946 #define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */ 2947 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */ 2948 #define CAN_F0R1_FB15_Pos (15U) 2949 #define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */ 2950 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */ 2951 #define CAN_F0R1_FB16_Pos (16U) 2952 #define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */ 2953 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */ 2954 #define CAN_F0R1_FB17_Pos (17U) 2955 #define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */ 2956 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */ 2957 #define CAN_F0R1_FB18_Pos (18U) 2958 #define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */ 2959 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */ 2960 #define CAN_F0R1_FB19_Pos (19U) 2961 #define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */ 2962 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */ 2963 #define CAN_F0R1_FB20_Pos (20U) 2964 #define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */ 2965 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */ 2966 #define CAN_F0R1_FB21_Pos (21U) 2967 #define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */ 2968 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */ 2969 #define CAN_F0R1_FB22_Pos (22U) 2970 #define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */ 2971 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */ 2972 #define CAN_F0R1_FB23_Pos (23U) 2973 #define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */ 2974 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */ 2975 #define CAN_F0R1_FB24_Pos (24U) 2976 #define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */ 2977 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */ 2978 #define CAN_F0R1_FB25_Pos (25U) 2979 #define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */ 2980 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */ 2981 #define CAN_F0R1_FB26_Pos (26U) 2982 #define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */ 2983 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */ 2984 #define CAN_F0R1_FB27_Pos (27U) 2985 #define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */ 2986 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */ 2987 #define CAN_F0R1_FB28_Pos (28U) 2988 #define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */ 2989 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */ 2990 #define CAN_F0R1_FB29_Pos (29U) 2991 #define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */ 2992 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */ 2993 #define CAN_F0R1_FB30_Pos (30U) 2994 #define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */ 2995 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */ 2996 #define CAN_F0R1_FB31_Pos (31U) 2997 #define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */ 2998 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */ 2999 3000 /******************* Bit definition for CAN_F1R1 register *******************/ 3001 #define CAN_F1R1_FB0_Pos (0U) 3002 #define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */ 3003 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */ 3004 #define CAN_F1R1_FB1_Pos (1U) 3005 #define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */ 3006 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */ 3007 #define CAN_F1R1_FB2_Pos (2U) 3008 #define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */ 3009 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */ 3010 #define CAN_F1R1_FB3_Pos (3U) 3011 #define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */ 3012 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */ 3013 #define CAN_F1R1_FB4_Pos (4U) 3014 #define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */ 3015 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */ 3016 #define CAN_F1R1_FB5_Pos (5U) 3017 #define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */ 3018 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */ 3019 #define CAN_F1R1_FB6_Pos (6U) 3020 #define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */ 3021 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */ 3022 #define CAN_F1R1_FB7_Pos (7U) 3023 #define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */ 3024 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */ 3025 #define CAN_F1R1_FB8_Pos (8U) 3026 #define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */ 3027 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */ 3028 #define CAN_F1R1_FB9_Pos (9U) 3029 #define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */ 3030 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */ 3031 #define CAN_F1R1_FB10_Pos (10U) 3032 #define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */ 3033 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */ 3034 #define CAN_F1R1_FB11_Pos (11U) 3035 #define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */ 3036 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */ 3037 #define CAN_F1R1_FB12_Pos (12U) 3038 #define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */ 3039 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */ 3040 #define CAN_F1R1_FB13_Pos (13U) 3041 #define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */ 3042 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */ 3043 #define CAN_F1R1_FB14_Pos (14U) 3044 #define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */ 3045 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */ 3046 #define CAN_F1R1_FB15_Pos (15U) 3047 #define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */ 3048 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */ 3049 #define CAN_F1R1_FB16_Pos (16U) 3050 #define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */ 3051 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */ 3052 #define CAN_F1R1_FB17_Pos (17U) 3053 #define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */ 3054 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */ 3055 #define CAN_F1R1_FB18_Pos (18U) 3056 #define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */ 3057 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */ 3058 #define CAN_F1R1_FB19_Pos (19U) 3059 #define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */ 3060 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */ 3061 #define CAN_F1R1_FB20_Pos (20U) 3062 #define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */ 3063 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */ 3064 #define CAN_F1R1_FB21_Pos (21U) 3065 #define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */ 3066 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */ 3067 #define CAN_F1R1_FB22_Pos (22U) 3068 #define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */ 3069 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */ 3070 #define CAN_F1R1_FB23_Pos (23U) 3071 #define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */ 3072 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */ 3073 #define CAN_F1R1_FB24_Pos (24U) 3074 #define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */ 3075 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */ 3076 #define CAN_F1R1_FB25_Pos (25U) 3077 #define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */ 3078 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */ 3079 #define CAN_F1R1_FB26_Pos (26U) 3080 #define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */ 3081 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */ 3082 #define CAN_F1R1_FB27_Pos (27U) 3083 #define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */ 3084 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */ 3085 #define CAN_F1R1_FB28_Pos (28U) 3086 #define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */ 3087 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */ 3088 #define CAN_F1R1_FB29_Pos (29U) 3089 #define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */ 3090 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */ 3091 #define CAN_F1R1_FB30_Pos (30U) 3092 #define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */ 3093 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */ 3094 #define CAN_F1R1_FB31_Pos (31U) 3095 #define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */ 3096 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */ 3097 3098 /******************* Bit definition for CAN_F2R1 register *******************/ 3099 #define CAN_F2R1_FB0_Pos (0U) 3100 #define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */ 3101 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */ 3102 #define CAN_F2R1_FB1_Pos (1U) 3103 #define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */ 3104 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */ 3105 #define CAN_F2R1_FB2_Pos (2U) 3106 #define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */ 3107 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */ 3108 #define CAN_F2R1_FB3_Pos (3U) 3109 #define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */ 3110 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */ 3111 #define CAN_F2R1_FB4_Pos (4U) 3112 #define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */ 3113 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */ 3114 #define CAN_F2R1_FB5_Pos (5U) 3115 #define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */ 3116 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */ 3117 #define CAN_F2R1_FB6_Pos (6U) 3118 #define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */ 3119 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */ 3120 #define CAN_F2R1_FB7_Pos (7U) 3121 #define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */ 3122 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */ 3123 #define CAN_F2R1_FB8_Pos (8U) 3124 #define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */ 3125 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */ 3126 #define CAN_F2R1_FB9_Pos (9U) 3127 #define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */ 3128 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */ 3129 #define CAN_F2R1_FB10_Pos (10U) 3130 #define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */ 3131 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */ 3132 #define CAN_F2R1_FB11_Pos (11U) 3133 #define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */ 3134 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */ 3135 #define CAN_F2R1_FB12_Pos (12U) 3136 #define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */ 3137 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */ 3138 #define CAN_F2R1_FB13_Pos (13U) 3139 #define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */ 3140 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */ 3141 #define CAN_F2R1_FB14_Pos (14U) 3142 #define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */ 3143 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */ 3144 #define CAN_F2R1_FB15_Pos (15U) 3145 #define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */ 3146 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */ 3147 #define CAN_F2R1_FB16_Pos (16U) 3148 #define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */ 3149 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */ 3150 #define CAN_F2R1_FB17_Pos (17U) 3151 #define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */ 3152 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */ 3153 #define CAN_F2R1_FB18_Pos (18U) 3154 #define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */ 3155 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */ 3156 #define CAN_F2R1_FB19_Pos (19U) 3157 #define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */ 3158 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */ 3159 #define CAN_F2R1_FB20_Pos (20U) 3160 #define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */ 3161 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */ 3162 #define CAN_F2R1_FB21_Pos (21U) 3163 #define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */ 3164 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */ 3165 #define CAN_F2R1_FB22_Pos (22U) 3166 #define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */ 3167 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */ 3168 #define CAN_F2R1_FB23_Pos (23U) 3169 #define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */ 3170 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */ 3171 #define CAN_F2R1_FB24_Pos (24U) 3172 #define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */ 3173 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */ 3174 #define CAN_F2R1_FB25_Pos (25U) 3175 #define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */ 3176 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */ 3177 #define CAN_F2R1_FB26_Pos (26U) 3178 #define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */ 3179 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */ 3180 #define CAN_F2R1_FB27_Pos (27U) 3181 #define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */ 3182 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */ 3183 #define CAN_F2R1_FB28_Pos (28U) 3184 #define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */ 3185 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */ 3186 #define CAN_F2R1_FB29_Pos (29U) 3187 #define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */ 3188 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */ 3189 #define CAN_F2R1_FB30_Pos (30U) 3190 #define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */ 3191 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */ 3192 #define CAN_F2R1_FB31_Pos (31U) 3193 #define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */ 3194 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */ 3195 3196 /******************* Bit definition for CAN_F3R1 register *******************/ 3197 #define CAN_F3R1_FB0_Pos (0U) 3198 #define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */ 3199 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */ 3200 #define CAN_F3R1_FB1_Pos (1U) 3201 #define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */ 3202 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */ 3203 #define CAN_F3R1_FB2_Pos (2U) 3204 #define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */ 3205 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */ 3206 #define CAN_F3R1_FB3_Pos (3U) 3207 #define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */ 3208 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */ 3209 #define CAN_F3R1_FB4_Pos (4U) 3210 #define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */ 3211 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */ 3212 #define CAN_F3R1_FB5_Pos (5U) 3213 #define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */ 3214 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */ 3215 #define CAN_F3R1_FB6_Pos (6U) 3216 #define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */ 3217 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */ 3218 #define CAN_F3R1_FB7_Pos (7U) 3219 #define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */ 3220 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */ 3221 #define CAN_F3R1_FB8_Pos (8U) 3222 #define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */ 3223 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */ 3224 #define CAN_F3R1_FB9_Pos (9U) 3225 #define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */ 3226 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */ 3227 #define CAN_F3R1_FB10_Pos (10U) 3228 #define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */ 3229 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */ 3230 #define CAN_F3R1_FB11_Pos (11U) 3231 #define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */ 3232 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */ 3233 #define CAN_F3R1_FB12_Pos (12U) 3234 #define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */ 3235 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */ 3236 #define CAN_F3R1_FB13_Pos (13U) 3237 #define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */ 3238 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */ 3239 #define CAN_F3R1_FB14_Pos (14U) 3240 #define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */ 3241 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */ 3242 #define CAN_F3R1_FB15_Pos (15U) 3243 #define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */ 3244 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */ 3245 #define CAN_F3R1_FB16_Pos (16U) 3246 #define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */ 3247 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */ 3248 #define CAN_F3R1_FB17_Pos (17U) 3249 #define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */ 3250 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */ 3251 #define CAN_F3R1_FB18_Pos (18U) 3252 #define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */ 3253 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */ 3254 #define CAN_F3R1_FB19_Pos (19U) 3255 #define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */ 3256 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */ 3257 #define CAN_F3R1_FB20_Pos (20U) 3258 #define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */ 3259 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */ 3260 #define CAN_F3R1_FB21_Pos (21U) 3261 #define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */ 3262 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */ 3263 #define CAN_F3R1_FB22_Pos (22U) 3264 #define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */ 3265 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */ 3266 #define CAN_F3R1_FB23_Pos (23U) 3267 #define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */ 3268 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */ 3269 #define CAN_F3R1_FB24_Pos (24U) 3270 #define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */ 3271 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */ 3272 #define CAN_F3R1_FB25_Pos (25U) 3273 #define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */ 3274 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */ 3275 #define CAN_F3R1_FB26_Pos (26U) 3276 #define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */ 3277 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */ 3278 #define CAN_F3R1_FB27_Pos (27U) 3279 #define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */ 3280 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */ 3281 #define CAN_F3R1_FB28_Pos (28U) 3282 #define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */ 3283 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */ 3284 #define CAN_F3R1_FB29_Pos (29U) 3285 #define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */ 3286 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */ 3287 #define CAN_F3R1_FB30_Pos (30U) 3288 #define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */ 3289 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */ 3290 #define CAN_F3R1_FB31_Pos (31U) 3291 #define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */ 3292 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */ 3293 3294 /******************* Bit definition for CAN_F4R1 register *******************/ 3295 #define CAN_F4R1_FB0_Pos (0U) 3296 #define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */ 3297 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */ 3298 #define CAN_F4R1_FB1_Pos (1U) 3299 #define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */ 3300 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */ 3301 #define CAN_F4R1_FB2_Pos (2U) 3302 #define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */ 3303 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */ 3304 #define CAN_F4R1_FB3_Pos (3U) 3305 #define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */ 3306 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */ 3307 #define CAN_F4R1_FB4_Pos (4U) 3308 #define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */ 3309 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */ 3310 #define CAN_F4R1_FB5_Pos (5U) 3311 #define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */ 3312 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */ 3313 #define CAN_F4R1_FB6_Pos (6U) 3314 #define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */ 3315 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */ 3316 #define CAN_F4R1_FB7_Pos (7U) 3317 #define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */ 3318 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */ 3319 #define CAN_F4R1_FB8_Pos (8U) 3320 #define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */ 3321 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */ 3322 #define CAN_F4R1_FB9_Pos (9U) 3323 #define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */ 3324 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */ 3325 #define CAN_F4R1_FB10_Pos (10U) 3326 #define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */ 3327 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */ 3328 #define CAN_F4R1_FB11_Pos (11U) 3329 #define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */ 3330 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */ 3331 #define CAN_F4R1_FB12_Pos (12U) 3332 #define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */ 3333 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */ 3334 #define CAN_F4R1_FB13_Pos (13U) 3335 #define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */ 3336 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */ 3337 #define CAN_F4R1_FB14_Pos (14U) 3338 #define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */ 3339 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */ 3340 #define CAN_F4R1_FB15_Pos (15U) 3341 #define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */ 3342 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */ 3343 #define CAN_F4R1_FB16_Pos (16U) 3344 #define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */ 3345 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */ 3346 #define CAN_F4R1_FB17_Pos (17U) 3347 #define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */ 3348 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */ 3349 #define CAN_F4R1_FB18_Pos (18U) 3350 #define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */ 3351 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */ 3352 #define CAN_F4R1_FB19_Pos (19U) 3353 #define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */ 3354 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */ 3355 #define CAN_F4R1_FB20_Pos (20U) 3356 #define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */ 3357 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */ 3358 #define CAN_F4R1_FB21_Pos (21U) 3359 #define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */ 3360 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */ 3361 #define CAN_F4R1_FB22_Pos (22U) 3362 #define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */ 3363 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */ 3364 #define CAN_F4R1_FB23_Pos (23U) 3365 #define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */ 3366 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */ 3367 #define CAN_F4R1_FB24_Pos (24U) 3368 #define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */ 3369 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */ 3370 #define CAN_F4R1_FB25_Pos (25U) 3371 #define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */ 3372 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */ 3373 #define CAN_F4R1_FB26_Pos (26U) 3374 #define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */ 3375 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */ 3376 #define CAN_F4R1_FB27_Pos (27U) 3377 #define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */ 3378 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */ 3379 #define CAN_F4R1_FB28_Pos (28U) 3380 #define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */ 3381 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */ 3382 #define CAN_F4R1_FB29_Pos (29U) 3383 #define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */ 3384 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */ 3385 #define CAN_F4R1_FB30_Pos (30U) 3386 #define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */ 3387 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */ 3388 #define CAN_F4R1_FB31_Pos (31U) 3389 #define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */ 3390 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */ 3391 3392 /******************* Bit definition for CAN_F5R1 register *******************/ 3393 #define CAN_F5R1_FB0_Pos (0U) 3394 #define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */ 3395 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */ 3396 #define CAN_F5R1_FB1_Pos (1U) 3397 #define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */ 3398 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */ 3399 #define CAN_F5R1_FB2_Pos (2U) 3400 #define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */ 3401 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */ 3402 #define CAN_F5R1_FB3_Pos (3U) 3403 #define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */ 3404 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */ 3405 #define CAN_F5R1_FB4_Pos (4U) 3406 #define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */ 3407 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */ 3408 #define CAN_F5R1_FB5_Pos (5U) 3409 #define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */ 3410 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */ 3411 #define CAN_F5R1_FB6_Pos (6U) 3412 #define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */ 3413 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */ 3414 #define CAN_F5R1_FB7_Pos (7U) 3415 #define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */ 3416 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */ 3417 #define CAN_F5R1_FB8_Pos (8U) 3418 #define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */ 3419 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */ 3420 #define CAN_F5R1_FB9_Pos (9U) 3421 #define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */ 3422 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */ 3423 #define CAN_F5R1_FB10_Pos (10U) 3424 #define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */ 3425 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */ 3426 #define CAN_F5R1_FB11_Pos (11U) 3427 #define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */ 3428 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */ 3429 #define CAN_F5R1_FB12_Pos (12U) 3430 #define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */ 3431 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */ 3432 #define CAN_F5R1_FB13_Pos (13U) 3433 #define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */ 3434 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */ 3435 #define CAN_F5R1_FB14_Pos (14U) 3436 #define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */ 3437 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */ 3438 #define CAN_F5R1_FB15_Pos (15U) 3439 #define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */ 3440 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */ 3441 #define CAN_F5R1_FB16_Pos (16U) 3442 #define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */ 3443 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */ 3444 #define CAN_F5R1_FB17_Pos (17U) 3445 #define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */ 3446 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */ 3447 #define CAN_F5R1_FB18_Pos (18U) 3448 #define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */ 3449 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */ 3450 #define CAN_F5R1_FB19_Pos (19U) 3451 #define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */ 3452 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */ 3453 #define CAN_F5R1_FB20_Pos (20U) 3454 #define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */ 3455 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */ 3456 #define CAN_F5R1_FB21_Pos (21U) 3457 #define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */ 3458 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */ 3459 #define CAN_F5R1_FB22_Pos (22U) 3460 #define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */ 3461 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */ 3462 #define CAN_F5R1_FB23_Pos (23U) 3463 #define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */ 3464 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */ 3465 #define CAN_F5R1_FB24_Pos (24U) 3466 #define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */ 3467 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */ 3468 #define CAN_F5R1_FB25_Pos (25U) 3469 #define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */ 3470 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */ 3471 #define CAN_F5R1_FB26_Pos (26U) 3472 #define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */ 3473 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */ 3474 #define CAN_F5R1_FB27_Pos (27U) 3475 #define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */ 3476 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */ 3477 #define CAN_F5R1_FB28_Pos (28U) 3478 #define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */ 3479 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */ 3480 #define CAN_F5R1_FB29_Pos (29U) 3481 #define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */ 3482 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */ 3483 #define CAN_F5R1_FB30_Pos (30U) 3484 #define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */ 3485 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */ 3486 #define CAN_F5R1_FB31_Pos (31U) 3487 #define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */ 3488 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */ 3489 3490 /******************* Bit definition for CAN_F6R1 register *******************/ 3491 #define CAN_F6R1_FB0_Pos (0U) 3492 #define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */ 3493 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */ 3494 #define CAN_F6R1_FB1_Pos (1U) 3495 #define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */ 3496 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */ 3497 #define CAN_F6R1_FB2_Pos (2U) 3498 #define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */ 3499 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */ 3500 #define CAN_F6R1_FB3_Pos (3U) 3501 #define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */ 3502 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */ 3503 #define CAN_F6R1_FB4_Pos (4U) 3504 #define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */ 3505 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */ 3506 #define CAN_F6R1_FB5_Pos (5U) 3507 #define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */ 3508 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */ 3509 #define CAN_F6R1_FB6_Pos (6U) 3510 #define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */ 3511 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */ 3512 #define CAN_F6R1_FB7_Pos (7U) 3513 #define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */ 3514 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */ 3515 #define CAN_F6R1_FB8_Pos (8U) 3516 #define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */ 3517 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */ 3518 #define CAN_F6R1_FB9_Pos (9U) 3519 #define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */ 3520 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */ 3521 #define CAN_F6R1_FB10_Pos (10U) 3522 #define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */ 3523 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */ 3524 #define CAN_F6R1_FB11_Pos (11U) 3525 #define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */ 3526 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */ 3527 #define CAN_F6R1_FB12_Pos (12U) 3528 #define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */ 3529 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */ 3530 #define CAN_F6R1_FB13_Pos (13U) 3531 #define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */ 3532 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */ 3533 #define CAN_F6R1_FB14_Pos (14U) 3534 #define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */ 3535 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */ 3536 #define CAN_F6R1_FB15_Pos (15U) 3537 #define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */ 3538 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */ 3539 #define CAN_F6R1_FB16_Pos (16U) 3540 #define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */ 3541 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */ 3542 #define CAN_F6R1_FB17_Pos (17U) 3543 #define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */ 3544 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */ 3545 #define CAN_F6R1_FB18_Pos (18U) 3546 #define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */ 3547 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */ 3548 #define CAN_F6R1_FB19_Pos (19U) 3549 #define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */ 3550 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */ 3551 #define CAN_F6R1_FB20_Pos (20U) 3552 #define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */ 3553 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */ 3554 #define CAN_F6R1_FB21_Pos (21U) 3555 #define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */ 3556 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */ 3557 #define CAN_F6R1_FB22_Pos (22U) 3558 #define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */ 3559 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */ 3560 #define CAN_F6R1_FB23_Pos (23U) 3561 #define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */ 3562 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */ 3563 #define CAN_F6R1_FB24_Pos (24U) 3564 #define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */ 3565 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */ 3566 #define CAN_F6R1_FB25_Pos (25U) 3567 #define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */ 3568 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */ 3569 #define CAN_F6R1_FB26_Pos (26U) 3570 #define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */ 3571 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */ 3572 #define CAN_F6R1_FB27_Pos (27U) 3573 #define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */ 3574 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */ 3575 #define CAN_F6R1_FB28_Pos (28U) 3576 #define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */ 3577 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */ 3578 #define CAN_F6R1_FB29_Pos (29U) 3579 #define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */ 3580 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */ 3581 #define CAN_F6R1_FB30_Pos (30U) 3582 #define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */ 3583 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */ 3584 #define CAN_F6R1_FB31_Pos (31U) 3585 #define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */ 3586 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */ 3587 3588 /******************* Bit definition for CAN_F7R1 register *******************/ 3589 #define CAN_F7R1_FB0_Pos (0U) 3590 #define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */ 3591 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */ 3592 #define CAN_F7R1_FB1_Pos (1U) 3593 #define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */ 3594 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */ 3595 #define CAN_F7R1_FB2_Pos (2U) 3596 #define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */ 3597 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */ 3598 #define CAN_F7R1_FB3_Pos (3U) 3599 #define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */ 3600 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */ 3601 #define CAN_F7R1_FB4_Pos (4U) 3602 #define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */ 3603 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */ 3604 #define CAN_F7R1_FB5_Pos (5U) 3605 #define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */ 3606 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */ 3607 #define CAN_F7R1_FB6_Pos (6U) 3608 #define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */ 3609 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */ 3610 #define CAN_F7R1_FB7_Pos (7U) 3611 #define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */ 3612 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */ 3613 #define CAN_F7R1_FB8_Pos (8U) 3614 #define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */ 3615 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */ 3616 #define CAN_F7R1_FB9_Pos (9U) 3617 #define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */ 3618 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */ 3619 #define CAN_F7R1_FB10_Pos (10U) 3620 #define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */ 3621 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */ 3622 #define CAN_F7R1_FB11_Pos (11U) 3623 #define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */ 3624 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */ 3625 #define CAN_F7R1_FB12_Pos (12U) 3626 #define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */ 3627 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */ 3628 #define CAN_F7R1_FB13_Pos (13U) 3629 #define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */ 3630 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */ 3631 #define CAN_F7R1_FB14_Pos (14U) 3632 #define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */ 3633 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */ 3634 #define CAN_F7R1_FB15_Pos (15U) 3635 #define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */ 3636 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */ 3637 #define CAN_F7R1_FB16_Pos (16U) 3638 #define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */ 3639 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */ 3640 #define CAN_F7R1_FB17_Pos (17U) 3641 #define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */ 3642 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */ 3643 #define CAN_F7R1_FB18_Pos (18U) 3644 #define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */ 3645 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */ 3646 #define CAN_F7R1_FB19_Pos (19U) 3647 #define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */ 3648 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */ 3649 #define CAN_F7R1_FB20_Pos (20U) 3650 #define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */ 3651 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */ 3652 #define CAN_F7R1_FB21_Pos (21U) 3653 #define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */ 3654 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */ 3655 #define CAN_F7R1_FB22_Pos (22U) 3656 #define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */ 3657 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */ 3658 #define CAN_F7R1_FB23_Pos (23U) 3659 #define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */ 3660 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */ 3661 #define CAN_F7R1_FB24_Pos (24U) 3662 #define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */ 3663 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */ 3664 #define CAN_F7R1_FB25_Pos (25U) 3665 #define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */ 3666 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */ 3667 #define CAN_F7R1_FB26_Pos (26U) 3668 #define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */ 3669 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */ 3670 #define CAN_F7R1_FB27_Pos (27U) 3671 #define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */ 3672 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */ 3673 #define CAN_F7R1_FB28_Pos (28U) 3674 #define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */ 3675 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */ 3676 #define CAN_F7R1_FB29_Pos (29U) 3677 #define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */ 3678 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */ 3679 #define CAN_F7R1_FB30_Pos (30U) 3680 #define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */ 3681 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */ 3682 #define CAN_F7R1_FB31_Pos (31U) 3683 #define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */ 3684 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */ 3685 3686 /******************* Bit definition for CAN_F8R1 register *******************/ 3687 #define CAN_F8R1_FB0_Pos (0U) 3688 #define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */ 3689 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */ 3690 #define CAN_F8R1_FB1_Pos (1U) 3691 #define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */ 3692 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */ 3693 #define CAN_F8R1_FB2_Pos (2U) 3694 #define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */ 3695 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */ 3696 #define CAN_F8R1_FB3_Pos (3U) 3697 #define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */ 3698 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */ 3699 #define CAN_F8R1_FB4_Pos (4U) 3700 #define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */ 3701 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */ 3702 #define CAN_F8R1_FB5_Pos (5U) 3703 #define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */ 3704 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */ 3705 #define CAN_F8R1_FB6_Pos (6U) 3706 #define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */ 3707 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */ 3708 #define CAN_F8R1_FB7_Pos (7U) 3709 #define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */ 3710 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */ 3711 #define CAN_F8R1_FB8_Pos (8U) 3712 #define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */ 3713 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */ 3714 #define CAN_F8R1_FB9_Pos (9U) 3715 #define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */ 3716 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */ 3717 #define CAN_F8R1_FB10_Pos (10U) 3718 #define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */ 3719 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */ 3720 #define CAN_F8R1_FB11_Pos (11U) 3721 #define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */ 3722 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */ 3723 #define CAN_F8R1_FB12_Pos (12U) 3724 #define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */ 3725 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */ 3726 #define CAN_F8R1_FB13_Pos (13U) 3727 #define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */ 3728 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */ 3729 #define CAN_F8R1_FB14_Pos (14U) 3730 #define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */ 3731 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */ 3732 #define CAN_F8R1_FB15_Pos (15U) 3733 #define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */ 3734 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */ 3735 #define CAN_F8R1_FB16_Pos (16U) 3736 #define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */ 3737 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */ 3738 #define CAN_F8R1_FB17_Pos (17U) 3739 #define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */ 3740 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */ 3741 #define CAN_F8R1_FB18_Pos (18U) 3742 #define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */ 3743 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */ 3744 #define CAN_F8R1_FB19_Pos (19U) 3745 #define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */ 3746 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */ 3747 #define CAN_F8R1_FB20_Pos (20U) 3748 #define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */ 3749 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */ 3750 #define CAN_F8R1_FB21_Pos (21U) 3751 #define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */ 3752 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */ 3753 #define CAN_F8R1_FB22_Pos (22U) 3754 #define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */ 3755 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */ 3756 #define CAN_F8R1_FB23_Pos (23U) 3757 #define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */ 3758 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */ 3759 #define CAN_F8R1_FB24_Pos (24U) 3760 #define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */ 3761 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */ 3762 #define CAN_F8R1_FB25_Pos (25U) 3763 #define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */ 3764 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */ 3765 #define CAN_F8R1_FB26_Pos (26U) 3766 #define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */ 3767 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */ 3768 #define CAN_F8R1_FB27_Pos (27U) 3769 #define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */ 3770 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */ 3771 #define CAN_F8R1_FB28_Pos (28U) 3772 #define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */ 3773 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */ 3774 #define CAN_F8R1_FB29_Pos (29U) 3775 #define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */ 3776 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */ 3777 #define CAN_F8R1_FB30_Pos (30U) 3778 #define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */ 3779 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */ 3780 #define CAN_F8R1_FB31_Pos (31U) 3781 #define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */ 3782 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */ 3783 3784 /******************* Bit definition for CAN_F9R1 register *******************/ 3785 #define CAN_F9R1_FB0_Pos (0U) 3786 #define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */ 3787 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */ 3788 #define CAN_F9R1_FB1_Pos (1U) 3789 #define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */ 3790 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */ 3791 #define CAN_F9R1_FB2_Pos (2U) 3792 #define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */ 3793 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */ 3794 #define CAN_F9R1_FB3_Pos (3U) 3795 #define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */ 3796 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */ 3797 #define CAN_F9R1_FB4_Pos (4U) 3798 #define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */ 3799 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */ 3800 #define CAN_F9R1_FB5_Pos (5U) 3801 #define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */ 3802 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */ 3803 #define CAN_F9R1_FB6_Pos (6U) 3804 #define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */ 3805 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */ 3806 #define CAN_F9R1_FB7_Pos (7U) 3807 #define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */ 3808 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */ 3809 #define CAN_F9R1_FB8_Pos (8U) 3810 #define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */ 3811 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */ 3812 #define CAN_F9R1_FB9_Pos (9U) 3813 #define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */ 3814 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */ 3815 #define CAN_F9R1_FB10_Pos (10U) 3816 #define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */ 3817 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */ 3818 #define CAN_F9R1_FB11_Pos (11U) 3819 #define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */ 3820 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */ 3821 #define CAN_F9R1_FB12_Pos (12U) 3822 #define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */ 3823 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */ 3824 #define CAN_F9R1_FB13_Pos (13U) 3825 #define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */ 3826 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */ 3827 #define CAN_F9R1_FB14_Pos (14U) 3828 #define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */ 3829 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */ 3830 #define CAN_F9R1_FB15_Pos (15U) 3831 #define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */ 3832 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */ 3833 #define CAN_F9R1_FB16_Pos (16U) 3834 #define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */ 3835 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */ 3836 #define CAN_F9R1_FB17_Pos (17U) 3837 #define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */ 3838 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */ 3839 #define CAN_F9R1_FB18_Pos (18U) 3840 #define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */ 3841 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */ 3842 #define CAN_F9R1_FB19_Pos (19U) 3843 #define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */ 3844 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */ 3845 #define CAN_F9R1_FB20_Pos (20U) 3846 #define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */ 3847 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */ 3848 #define CAN_F9R1_FB21_Pos (21U) 3849 #define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */ 3850 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */ 3851 #define CAN_F9R1_FB22_Pos (22U) 3852 #define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */ 3853 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */ 3854 #define CAN_F9R1_FB23_Pos (23U) 3855 #define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */ 3856 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */ 3857 #define CAN_F9R1_FB24_Pos (24U) 3858 #define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */ 3859 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */ 3860 #define CAN_F9R1_FB25_Pos (25U) 3861 #define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */ 3862 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */ 3863 #define CAN_F9R1_FB26_Pos (26U) 3864 #define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */ 3865 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */ 3866 #define CAN_F9R1_FB27_Pos (27U) 3867 #define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */ 3868 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */ 3869 #define CAN_F9R1_FB28_Pos (28U) 3870 #define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */ 3871 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */ 3872 #define CAN_F9R1_FB29_Pos (29U) 3873 #define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */ 3874 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */ 3875 #define CAN_F9R1_FB30_Pos (30U) 3876 #define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */ 3877 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */ 3878 #define CAN_F9R1_FB31_Pos (31U) 3879 #define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */ 3880 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */ 3881 3882 /******************* Bit definition for CAN_F10R1 register ******************/ 3883 #define CAN_F10R1_FB0_Pos (0U) 3884 #define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */ 3885 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */ 3886 #define CAN_F10R1_FB1_Pos (1U) 3887 #define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */ 3888 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */ 3889 #define CAN_F10R1_FB2_Pos (2U) 3890 #define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */ 3891 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */ 3892 #define CAN_F10R1_FB3_Pos (3U) 3893 #define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */ 3894 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */ 3895 #define CAN_F10R1_FB4_Pos (4U) 3896 #define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */ 3897 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */ 3898 #define CAN_F10R1_FB5_Pos (5U) 3899 #define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */ 3900 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */ 3901 #define CAN_F10R1_FB6_Pos (6U) 3902 #define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */ 3903 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */ 3904 #define CAN_F10R1_FB7_Pos (7U) 3905 #define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */ 3906 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */ 3907 #define CAN_F10R1_FB8_Pos (8U) 3908 #define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */ 3909 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */ 3910 #define CAN_F10R1_FB9_Pos (9U) 3911 #define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */ 3912 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */ 3913 #define CAN_F10R1_FB10_Pos (10U) 3914 #define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */ 3915 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */ 3916 #define CAN_F10R1_FB11_Pos (11U) 3917 #define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */ 3918 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */ 3919 #define CAN_F10R1_FB12_Pos (12U) 3920 #define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */ 3921 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */ 3922 #define CAN_F10R1_FB13_Pos (13U) 3923 #define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */ 3924 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */ 3925 #define CAN_F10R1_FB14_Pos (14U) 3926 #define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */ 3927 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */ 3928 #define CAN_F10R1_FB15_Pos (15U) 3929 #define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */ 3930 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */ 3931 #define CAN_F10R1_FB16_Pos (16U) 3932 #define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */ 3933 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */ 3934 #define CAN_F10R1_FB17_Pos (17U) 3935 #define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */ 3936 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */ 3937 #define CAN_F10R1_FB18_Pos (18U) 3938 #define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */ 3939 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */ 3940 #define CAN_F10R1_FB19_Pos (19U) 3941 #define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */ 3942 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */ 3943 #define CAN_F10R1_FB20_Pos (20U) 3944 #define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */ 3945 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */ 3946 #define CAN_F10R1_FB21_Pos (21U) 3947 #define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */ 3948 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */ 3949 #define CAN_F10R1_FB22_Pos (22U) 3950 #define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */ 3951 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */ 3952 #define CAN_F10R1_FB23_Pos (23U) 3953 #define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */ 3954 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */ 3955 #define CAN_F10R1_FB24_Pos (24U) 3956 #define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */ 3957 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */ 3958 #define CAN_F10R1_FB25_Pos (25U) 3959 #define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */ 3960 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */ 3961 #define CAN_F10R1_FB26_Pos (26U) 3962 #define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */ 3963 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */ 3964 #define CAN_F10R1_FB27_Pos (27U) 3965 #define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */ 3966 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */ 3967 #define CAN_F10R1_FB28_Pos (28U) 3968 #define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */ 3969 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */ 3970 #define CAN_F10R1_FB29_Pos (29U) 3971 #define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */ 3972 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */ 3973 #define CAN_F10R1_FB30_Pos (30U) 3974 #define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */ 3975 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */ 3976 #define CAN_F10R1_FB31_Pos (31U) 3977 #define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */ 3978 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */ 3979 3980 /******************* Bit definition for CAN_F11R1 register ******************/ 3981 #define CAN_F11R1_FB0_Pos (0U) 3982 #define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */ 3983 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */ 3984 #define CAN_F11R1_FB1_Pos (1U) 3985 #define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */ 3986 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */ 3987 #define CAN_F11R1_FB2_Pos (2U) 3988 #define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */ 3989 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */ 3990 #define CAN_F11R1_FB3_Pos (3U) 3991 #define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */ 3992 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */ 3993 #define CAN_F11R1_FB4_Pos (4U) 3994 #define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */ 3995 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */ 3996 #define CAN_F11R1_FB5_Pos (5U) 3997 #define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */ 3998 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */ 3999 #define CAN_F11R1_FB6_Pos (6U) 4000 #define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */ 4001 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */ 4002 #define CAN_F11R1_FB7_Pos (7U) 4003 #define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */ 4004 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */ 4005 #define CAN_F11R1_FB8_Pos (8U) 4006 #define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */ 4007 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */ 4008 #define CAN_F11R1_FB9_Pos (9U) 4009 #define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */ 4010 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */ 4011 #define CAN_F11R1_FB10_Pos (10U) 4012 #define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */ 4013 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */ 4014 #define CAN_F11R1_FB11_Pos (11U) 4015 #define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */ 4016 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */ 4017 #define CAN_F11R1_FB12_Pos (12U) 4018 #define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */ 4019 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */ 4020 #define CAN_F11R1_FB13_Pos (13U) 4021 #define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */ 4022 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */ 4023 #define CAN_F11R1_FB14_Pos (14U) 4024 #define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */ 4025 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */ 4026 #define CAN_F11R1_FB15_Pos (15U) 4027 #define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */ 4028 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */ 4029 #define CAN_F11R1_FB16_Pos (16U) 4030 #define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */ 4031 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */ 4032 #define CAN_F11R1_FB17_Pos (17U) 4033 #define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */ 4034 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */ 4035 #define CAN_F11R1_FB18_Pos (18U) 4036 #define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */ 4037 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */ 4038 #define CAN_F11R1_FB19_Pos (19U) 4039 #define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */ 4040 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */ 4041 #define CAN_F11R1_FB20_Pos (20U) 4042 #define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */ 4043 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */ 4044 #define CAN_F11R1_FB21_Pos (21U) 4045 #define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */ 4046 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */ 4047 #define CAN_F11R1_FB22_Pos (22U) 4048 #define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */ 4049 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */ 4050 #define CAN_F11R1_FB23_Pos (23U) 4051 #define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */ 4052 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */ 4053 #define CAN_F11R1_FB24_Pos (24U) 4054 #define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */ 4055 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */ 4056 #define CAN_F11R1_FB25_Pos (25U) 4057 #define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */ 4058 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */ 4059 #define CAN_F11R1_FB26_Pos (26U) 4060 #define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */ 4061 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */ 4062 #define CAN_F11R1_FB27_Pos (27U) 4063 #define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */ 4064 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */ 4065 #define CAN_F11R1_FB28_Pos (28U) 4066 #define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */ 4067 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */ 4068 #define CAN_F11R1_FB29_Pos (29U) 4069 #define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */ 4070 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */ 4071 #define CAN_F11R1_FB30_Pos (30U) 4072 #define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */ 4073 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */ 4074 #define CAN_F11R1_FB31_Pos (31U) 4075 #define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */ 4076 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */ 4077 4078 /******************* Bit definition for CAN_F12R1 register ******************/ 4079 #define CAN_F12R1_FB0_Pos (0U) 4080 #define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */ 4081 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */ 4082 #define CAN_F12R1_FB1_Pos (1U) 4083 #define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */ 4084 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */ 4085 #define CAN_F12R1_FB2_Pos (2U) 4086 #define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */ 4087 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */ 4088 #define CAN_F12R1_FB3_Pos (3U) 4089 #define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */ 4090 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */ 4091 #define CAN_F12R1_FB4_Pos (4U) 4092 #define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */ 4093 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */ 4094 #define CAN_F12R1_FB5_Pos (5U) 4095 #define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */ 4096 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */ 4097 #define CAN_F12R1_FB6_Pos (6U) 4098 #define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */ 4099 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */ 4100 #define CAN_F12R1_FB7_Pos (7U) 4101 #define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */ 4102 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */ 4103 #define CAN_F12R1_FB8_Pos (8U) 4104 #define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */ 4105 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */ 4106 #define CAN_F12R1_FB9_Pos (9U) 4107 #define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */ 4108 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */ 4109 #define CAN_F12R1_FB10_Pos (10U) 4110 #define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */ 4111 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */ 4112 #define CAN_F12R1_FB11_Pos (11U) 4113 #define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */ 4114 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */ 4115 #define CAN_F12R1_FB12_Pos (12U) 4116 #define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */ 4117 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */ 4118 #define CAN_F12R1_FB13_Pos (13U) 4119 #define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */ 4120 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */ 4121 #define CAN_F12R1_FB14_Pos (14U) 4122 #define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */ 4123 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */ 4124 #define CAN_F12R1_FB15_Pos (15U) 4125 #define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */ 4126 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */ 4127 #define CAN_F12R1_FB16_Pos (16U) 4128 #define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */ 4129 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */ 4130 #define CAN_F12R1_FB17_Pos (17U) 4131 #define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */ 4132 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */ 4133 #define CAN_F12R1_FB18_Pos (18U) 4134 #define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */ 4135 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */ 4136 #define CAN_F12R1_FB19_Pos (19U) 4137 #define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */ 4138 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */ 4139 #define CAN_F12R1_FB20_Pos (20U) 4140 #define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */ 4141 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */ 4142 #define CAN_F12R1_FB21_Pos (21U) 4143 #define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */ 4144 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */ 4145 #define CAN_F12R1_FB22_Pos (22U) 4146 #define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */ 4147 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */ 4148 #define CAN_F12R1_FB23_Pos (23U) 4149 #define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */ 4150 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */ 4151 #define CAN_F12R1_FB24_Pos (24U) 4152 #define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */ 4153 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */ 4154 #define CAN_F12R1_FB25_Pos (25U) 4155 #define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */ 4156 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */ 4157 #define CAN_F12R1_FB26_Pos (26U) 4158 #define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */ 4159 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */ 4160 #define CAN_F12R1_FB27_Pos (27U) 4161 #define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */ 4162 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */ 4163 #define CAN_F12R1_FB28_Pos (28U) 4164 #define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */ 4165 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */ 4166 #define CAN_F12R1_FB29_Pos (29U) 4167 #define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */ 4168 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */ 4169 #define CAN_F12R1_FB30_Pos (30U) 4170 #define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */ 4171 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */ 4172 #define CAN_F12R1_FB31_Pos (31U) 4173 #define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */ 4174 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */ 4175 4176 /******************* Bit definition for CAN_F13R1 register ******************/ 4177 #define CAN_F13R1_FB0_Pos (0U) 4178 #define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */ 4179 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */ 4180 #define CAN_F13R1_FB1_Pos (1U) 4181 #define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */ 4182 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */ 4183 #define CAN_F13R1_FB2_Pos (2U) 4184 #define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */ 4185 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */ 4186 #define CAN_F13R1_FB3_Pos (3U) 4187 #define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */ 4188 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */ 4189 #define CAN_F13R1_FB4_Pos (4U) 4190 #define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */ 4191 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */ 4192 #define CAN_F13R1_FB5_Pos (5U) 4193 #define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */ 4194 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */ 4195 #define CAN_F13R1_FB6_Pos (6U) 4196 #define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */ 4197 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */ 4198 #define CAN_F13R1_FB7_Pos (7U) 4199 #define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */ 4200 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */ 4201 #define CAN_F13R1_FB8_Pos (8U) 4202 #define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */ 4203 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */ 4204 #define CAN_F13R1_FB9_Pos (9U) 4205 #define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */ 4206 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */ 4207 #define CAN_F13R1_FB10_Pos (10U) 4208 #define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */ 4209 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */ 4210 #define CAN_F13R1_FB11_Pos (11U) 4211 #define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */ 4212 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */ 4213 #define CAN_F13R1_FB12_Pos (12U) 4214 #define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */ 4215 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */ 4216 #define CAN_F13R1_FB13_Pos (13U) 4217 #define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */ 4218 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */ 4219 #define CAN_F13R1_FB14_Pos (14U) 4220 #define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */ 4221 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */ 4222 #define CAN_F13R1_FB15_Pos (15U) 4223 #define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */ 4224 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */ 4225 #define CAN_F13R1_FB16_Pos (16U) 4226 #define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */ 4227 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */ 4228 #define CAN_F13R1_FB17_Pos (17U) 4229 #define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */ 4230 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */ 4231 #define CAN_F13R1_FB18_Pos (18U) 4232 #define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */ 4233 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */ 4234 #define CAN_F13R1_FB19_Pos (19U) 4235 #define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */ 4236 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */ 4237 #define CAN_F13R1_FB20_Pos (20U) 4238 #define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */ 4239 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */ 4240 #define CAN_F13R1_FB21_Pos (21U) 4241 #define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */ 4242 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */ 4243 #define CAN_F13R1_FB22_Pos (22U) 4244 #define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */ 4245 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */ 4246 #define CAN_F13R1_FB23_Pos (23U) 4247 #define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */ 4248 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */ 4249 #define CAN_F13R1_FB24_Pos (24U) 4250 #define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */ 4251 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */ 4252 #define CAN_F13R1_FB25_Pos (25U) 4253 #define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */ 4254 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */ 4255 #define CAN_F13R1_FB26_Pos (26U) 4256 #define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */ 4257 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */ 4258 #define CAN_F13R1_FB27_Pos (27U) 4259 #define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */ 4260 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */ 4261 #define CAN_F13R1_FB28_Pos (28U) 4262 #define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */ 4263 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */ 4264 #define CAN_F13R1_FB29_Pos (29U) 4265 #define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */ 4266 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */ 4267 #define CAN_F13R1_FB30_Pos (30U) 4268 #define CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */ 4269 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */ 4270 #define CAN_F13R1_FB31_Pos (31U) 4271 #define CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */ 4272 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */ 4273 4274 /******************* Bit definition for CAN_F0R2 register *******************/ 4275 #define CAN_F0R2_FB0_Pos (0U) 4276 #define CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */ 4277 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */ 4278 #define CAN_F0R2_FB1_Pos (1U) 4279 #define CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */ 4280 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */ 4281 #define CAN_F0R2_FB2_Pos (2U) 4282 #define CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */ 4283 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */ 4284 #define CAN_F0R2_FB3_Pos (3U) 4285 #define CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */ 4286 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */ 4287 #define CAN_F0R2_FB4_Pos (4U) 4288 #define CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */ 4289 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */ 4290 #define CAN_F0R2_FB5_Pos (5U) 4291 #define CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */ 4292 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */ 4293 #define CAN_F0R2_FB6_Pos (6U) 4294 #define CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */ 4295 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */ 4296 #define CAN_F0R2_FB7_Pos (7U) 4297 #define CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */ 4298 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */ 4299 #define CAN_F0R2_FB8_Pos (8U) 4300 #define CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */ 4301 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */ 4302 #define CAN_F0R2_FB9_Pos (9U) 4303 #define CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */ 4304 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */ 4305 #define CAN_F0R2_FB10_Pos (10U) 4306 #define CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */ 4307 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */ 4308 #define CAN_F0R2_FB11_Pos (11U) 4309 #define CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */ 4310 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */ 4311 #define CAN_F0R2_FB12_Pos (12U) 4312 #define CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */ 4313 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */ 4314 #define CAN_F0R2_FB13_Pos (13U) 4315 #define CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */ 4316 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */ 4317 #define CAN_F0R2_FB14_Pos (14U) 4318 #define CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */ 4319 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */ 4320 #define CAN_F0R2_FB15_Pos (15U) 4321 #define CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */ 4322 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */ 4323 #define CAN_F0R2_FB16_Pos (16U) 4324 #define CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */ 4325 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */ 4326 #define CAN_F0R2_FB17_Pos (17U) 4327 #define CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */ 4328 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */ 4329 #define CAN_F0R2_FB18_Pos (18U) 4330 #define CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */ 4331 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */ 4332 #define CAN_F0R2_FB19_Pos (19U) 4333 #define CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */ 4334 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */ 4335 #define CAN_F0R2_FB20_Pos (20U) 4336 #define CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */ 4337 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */ 4338 #define CAN_F0R2_FB21_Pos (21U) 4339 #define CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */ 4340 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */ 4341 #define CAN_F0R2_FB22_Pos (22U) 4342 #define CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */ 4343 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */ 4344 #define CAN_F0R2_FB23_Pos (23U) 4345 #define CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */ 4346 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */ 4347 #define CAN_F0R2_FB24_Pos (24U) 4348 #define CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */ 4349 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */ 4350 #define CAN_F0R2_FB25_Pos (25U) 4351 #define CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */ 4352 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */ 4353 #define CAN_F0R2_FB26_Pos (26U) 4354 #define CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */ 4355 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */ 4356 #define CAN_F0R2_FB27_Pos (27U) 4357 #define CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */ 4358 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */ 4359 #define CAN_F0R2_FB28_Pos (28U) 4360 #define CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */ 4361 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */ 4362 #define CAN_F0R2_FB29_Pos (29U) 4363 #define CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */ 4364 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */ 4365 #define CAN_F0R2_FB30_Pos (30U) 4366 #define CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */ 4367 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */ 4368 #define CAN_F0R2_FB31_Pos (31U) 4369 #define CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */ 4370 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */ 4371 4372 /******************* Bit definition for CAN_F1R2 register *******************/ 4373 #define CAN_F1R2_FB0_Pos (0U) 4374 #define CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */ 4375 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */ 4376 #define CAN_F1R2_FB1_Pos (1U) 4377 #define CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */ 4378 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */ 4379 #define CAN_F1R2_FB2_Pos (2U) 4380 #define CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */ 4381 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */ 4382 #define CAN_F1R2_FB3_Pos (3U) 4383 #define CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */ 4384 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */ 4385 #define CAN_F1R2_FB4_Pos (4U) 4386 #define CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */ 4387 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */ 4388 #define CAN_F1R2_FB5_Pos (5U) 4389 #define CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */ 4390 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */ 4391 #define CAN_F1R2_FB6_Pos (6U) 4392 #define CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */ 4393 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */ 4394 #define CAN_F1R2_FB7_Pos (7U) 4395 #define CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */ 4396 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */ 4397 #define CAN_F1R2_FB8_Pos (8U) 4398 #define CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */ 4399 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */ 4400 #define CAN_F1R2_FB9_Pos (9U) 4401 #define CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */ 4402 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */ 4403 #define CAN_F1R2_FB10_Pos (10U) 4404 #define CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */ 4405 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */ 4406 #define CAN_F1R2_FB11_Pos (11U) 4407 #define CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */ 4408 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */ 4409 #define CAN_F1R2_FB12_Pos (12U) 4410 #define CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */ 4411 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */ 4412 #define CAN_F1R2_FB13_Pos (13U) 4413 #define CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */ 4414 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */ 4415 #define CAN_F1R2_FB14_Pos (14U) 4416 #define CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */ 4417 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */ 4418 #define CAN_F1R2_FB15_Pos (15U) 4419 #define CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */ 4420 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */ 4421 #define CAN_F1R2_FB16_Pos (16U) 4422 #define CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */ 4423 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */ 4424 #define CAN_F1R2_FB17_Pos (17U) 4425 #define CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */ 4426 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */ 4427 #define CAN_F1R2_FB18_Pos (18U) 4428 #define CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */ 4429 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */ 4430 #define CAN_F1R2_FB19_Pos (19U) 4431 #define CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */ 4432 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */ 4433 #define CAN_F1R2_FB20_Pos (20U) 4434 #define CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */ 4435 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */ 4436 #define CAN_F1R2_FB21_Pos (21U) 4437 #define CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */ 4438 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */ 4439 #define CAN_F1R2_FB22_Pos (22U) 4440 #define CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */ 4441 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */ 4442 #define CAN_F1R2_FB23_Pos (23U) 4443 #define CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */ 4444 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */ 4445 #define CAN_F1R2_FB24_Pos (24U) 4446 #define CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */ 4447 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */ 4448 #define CAN_F1R2_FB25_Pos (25U) 4449 #define CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */ 4450 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */ 4451 #define CAN_F1R2_FB26_Pos (26U) 4452 #define CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */ 4453 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */ 4454 #define CAN_F1R2_FB27_Pos (27U) 4455 #define CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */ 4456 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */ 4457 #define CAN_F1R2_FB28_Pos (28U) 4458 #define CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */ 4459 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */ 4460 #define CAN_F1R2_FB29_Pos (29U) 4461 #define CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */ 4462 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */ 4463 #define CAN_F1R2_FB30_Pos (30U) 4464 #define CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */ 4465 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */ 4466 #define CAN_F1R2_FB31_Pos (31U) 4467 #define CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */ 4468 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */ 4469 4470 /******************* Bit definition for CAN_F2R2 register *******************/ 4471 #define CAN_F2R2_FB0_Pos (0U) 4472 #define CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */ 4473 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */ 4474 #define CAN_F2R2_FB1_Pos (1U) 4475 #define CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */ 4476 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */ 4477 #define CAN_F2R2_FB2_Pos (2U) 4478 #define CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */ 4479 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */ 4480 #define CAN_F2R2_FB3_Pos (3U) 4481 #define CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */ 4482 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */ 4483 #define CAN_F2R2_FB4_Pos (4U) 4484 #define CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */ 4485 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */ 4486 #define CAN_F2R2_FB5_Pos (5U) 4487 #define CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */ 4488 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */ 4489 #define CAN_F2R2_FB6_Pos (6U) 4490 #define CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */ 4491 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */ 4492 #define CAN_F2R2_FB7_Pos (7U) 4493 #define CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */ 4494 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */ 4495 #define CAN_F2R2_FB8_Pos (8U) 4496 #define CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */ 4497 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */ 4498 #define CAN_F2R2_FB9_Pos (9U) 4499 #define CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */ 4500 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */ 4501 #define CAN_F2R2_FB10_Pos (10U) 4502 #define CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */ 4503 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */ 4504 #define CAN_F2R2_FB11_Pos (11U) 4505 #define CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */ 4506 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */ 4507 #define CAN_F2R2_FB12_Pos (12U) 4508 #define CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */ 4509 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */ 4510 #define CAN_F2R2_FB13_Pos (13U) 4511 #define CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */ 4512 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */ 4513 #define CAN_F2R2_FB14_Pos (14U) 4514 #define CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */ 4515 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */ 4516 #define CAN_F2R2_FB15_Pos (15U) 4517 #define CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */ 4518 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */ 4519 #define CAN_F2R2_FB16_Pos (16U) 4520 #define CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */ 4521 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */ 4522 #define CAN_F2R2_FB17_Pos (17U) 4523 #define CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */ 4524 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */ 4525 #define CAN_F2R2_FB18_Pos (18U) 4526 #define CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */ 4527 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */ 4528 #define CAN_F2R2_FB19_Pos (19U) 4529 #define CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */ 4530 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */ 4531 #define CAN_F2R2_FB20_Pos (20U) 4532 #define CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */ 4533 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */ 4534 #define CAN_F2R2_FB21_Pos (21U) 4535 #define CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */ 4536 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */ 4537 #define CAN_F2R2_FB22_Pos (22U) 4538 #define CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */ 4539 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */ 4540 #define CAN_F2R2_FB23_Pos (23U) 4541 #define CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */ 4542 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */ 4543 #define CAN_F2R2_FB24_Pos (24U) 4544 #define CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */ 4545 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */ 4546 #define CAN_F2R2_FB25_Pos (25U) 4547 #define CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */ 4548 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */ 4549 #define CAN_F2R2_FB26_Pos (26U) 4550 #define CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */ 4551 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */ 4552 #define CAN_F2R2_FB27_Pos (27U) 4553 #define CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */ 4554 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */ 4555 #define CAN_F2R2_FB28_Pos (28U) 4556 #define CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */ 4557 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */ 4558 #define CAN_F2R2_FB29_Pos (29U) 4559 #define CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */ 4560 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */ 4561 #define CAN_F2R2_FB30_Pos (30U) 4562 #define CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */ 4563 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */ 4564 #define CAN_F2R2_FB31_Pos (31U) 4565 #define CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */ 4566 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */ 4567 4568 /******************* Bit definition for CAN_F3R2 register *******************/ 4569 #define CAN_F3R2_FB0_Pos (0U) 4570 #define CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */ 4571 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */ 4572 #define CAN_F3R2_FB1_Pos (1U) 4573 #define CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */ 4574 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */ 4575 #define CAN_F3R2_FB2_Pos (2U) 4576 #define CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */ 4577 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */ 4578 #define CAN_F3R2_FB3_Pos (3U) 4579 #define CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */ 4580 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */ 4581 #define CAN_F3R2_FB4_Pos (4U) 4582 #define CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */ 4583 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */ 4584 #define CAN_F3R2_FB5_Pos (5U) 4585 #define CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */ 4586 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */ 4587 #define CAN_F3R2_FB6_Pos (6U) 4588 #define CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */ 4589 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */ 4590 #define CAN_F3R2_FB7_Pos (7U) 4591 #define CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */ 4592 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */ 4593 #define CAN_F3R2_FB8_Pos (8U) 4594 #define CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */ 4595 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */ 4596 #define CAN_F3R2_FB9_Pos (9U) 4597 #define CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */ 4598 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */ 4599 #define CAN_F3R2_FB10_Pos (10U) 4600 #define CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */ 4601 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */ 4602 #define CAN_F3R2_FB11_Pos (11U) 4603 #define CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */ 4604 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */ 4605 #define CAN_F3R2_FB12_Pos (12U) 4606 #define CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */ 4607 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */ 4608 #define CAN_F3R2_FB13_Pos (13U) 4609 #define CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */ 4610 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */ 4611 #define CAN_F3R2_FB14_Pos (14U) 4612 #define CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */ 4613 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */ 4614 #define CAN_F3R2_FB15_Pos (15U) 4615 #define CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */ 4616 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */ 4617 #define CAN_F3R2_FB16_Pos (16U) 4618 #define CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */ 4619 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */ 4620 #define CAN_F3R2_FB17_Pos (17U) 4621 #define CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */ 4622 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */ 4623 #define CAN_F3R2_FB18_Pos (18U) 4624 #define CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */ 4625 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */ 4626 #define CAN_F3R2_FB19_Pos (19U) 4627 #define CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */ 4628 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */ 4629 #define CAN_F3R2_FB20_Pos (20U) 4630 #define CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */ 4631 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */ 4632 #define CAN_F3R2_FB21_Pos (21U) 4633 #define CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */ 4634 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */ 4635 #define CAN_F3R2_FB22_Pos (22U) 4636 #define CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */ 4637 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */ 4638 #define CAN_F3R2_FB23_Pos (23U) 4639 #define CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */ 4640 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */ 4641 #define CAN_F3R2_FB24_Pos (24U) 4642 #define CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */ 4643 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */ 4644 #define CAN_F3R2_FB25_Pos (25U) 4645 #define CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */ 4646 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */ 4647 #define CAN_F3R2_FB26_Pos (26U) 4648 #define CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */ 4649 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */ 4650 #define CAN_F3R2_FB27_Pos (27U) 4651 #define CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */ 4652 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */ 4653 #define CAN_F3R2_FB28_Pos (28U) 4654 #define CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */ 4655 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */ 4656 #define CAN_F3R2_FB29_Pos (29U) 4657 #define CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */ 4658 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */ 4659 #define CAN_F3R2_FB30_Pos (30U) 4660 #define CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */ 4661 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */ 4662 #define CAN_F3R2_FB31_Pos (31U) 4663 #define CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */ 4664 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */ 4665 4666 /******************* Bit definition for CAN_F4R2 register *******************/ 4667 #define CAN_F4R2_FB0_Pos (0U) 4668 #define CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */ 4669 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */ 4670 #define CAN_F4R2_FB1_Pos (1U) 4671 #define CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */ 4672 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */ 4673 #define CAN_F4R2_FB2_Pos (2U) 4674 #define CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */ 4675 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */ 4676 #define CAN_F4R2_FB3_Pos (3U) 4677 #define CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */ 4678 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */ 4679 #define CAN_F4R2_FB4_Pos (4U) 4680 #define CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */ 4681 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */ 4682 #define CAN_F4R2_FB5_Pos (5U) 4683 #define CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */ 4684 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */ 4685 #define CAN_F4R2_FB6_Pos (6U) 4686 #define CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */ 4687 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */ 4688 #define CAN_F4R2_FB7_Pos (7U) 4689 #define CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */ 4690 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */ 4691 #define CAN_F4R2_FB8_Pos (8U) 4692 #define CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */ 4693 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */ 4694 #define CAN_F4R2_FB9_Pos (9U) 4695 #define CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */ 4696 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */ 4697 #define CAN_F4R2_FB10_Pos (10U) 4698 #define CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */ 4699 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */ 4700 #define CAN_F4R2_FB11_Pos (11U) 4701 #define CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */ 4702 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */ 4703 #define CAN_F4R2_FB12_Pos (12U) 4704 #define CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */ 4705 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */ 4706 #define CAN_F4R2_FB13_Pos (13U) 4707 #define CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */ 4708 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */ 4709 #define CAN_F4R2_FB14_Pos (14U) 4710 #define CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */ 4711 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */ 4712 #define CAN_F4R2_FB15_Pos (15U) 4713 #define CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */ 4714 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */ 4715 #define CAN_F4R2_FB16_Pos (16U) 4716 #define CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */ 4717 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */ 4718 #define CAN_F4R2_FB17_Pos (17U) 4719 #define CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */ 4720 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */ 4721 #define CAN_F4R2_FB18_Pos (18U) 4722 #define CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */ 4723 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */ 4724 #define CAN_F4R2_FB19_Pos (19U) 4725 #define CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */ 4726 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */ 4727 #define CAN_F4R2_FB20_Pos (20U) 4728 #define CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */ 4729 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */ 4730 #define CAN_F4R2_FB21_Pos (21U) 4731 #define CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */ 4732 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */ 4733 #define CAN_F4R2_FB22_Pos (22U) 4734 #define CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */ 4735 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */ 4736 #define CAN_F4R2_FB23_Pos (23U) 4737 #define CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */ 4738 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */ 4739 #define CAN_F4R2_FB24_Pos (24U) 4740 #define CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */ 4741 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */ 4742 #define CAN_F4R2_FB25_Pos (25U) 4743 #define CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */ 4744 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */ 4745 #define CAN_F4R2_FB26_Pos (26U) 4746 #define CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */ 4747 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */ 4748 #define CAN_F4R2_FB27_Pos (27U) 4749 #define CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */ 4750 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */ 4751 #define CAN_F4R2_FB28_Pos (28U) 4752 #define CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */ 4753 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */ 4754 #define CAN_F4R2_FB29_Pos (29U) 4755 #define CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */ 4756 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */ 4757 #define CAN_F4R2_FB30_Pos (30U) 4758 #define CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */ 4759 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */ 4760 #define CAN_F4R2_FB31_Pos (31U) 4761 #define CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */ 4762 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */ 4763 4764 /******************* Bit definition for CAN_F5R2 register *******************/ 4765 #define CAN_F5R2_FB0_Pos (0U) 4766 #define CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */ 4767 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */ 4768 #define CAN_F5R2_FB1_Pos (1U) 4769 #define CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */ 4770 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */ 4771 #define CAN_F5R2_FB2_Pos (2U) 4772 #define CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */ 4773 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */ 4774 #define CAN_F5R2_FB3_Pos (3U) 4775 #define CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */ 4776 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */ 4777 #define CAN_F5R2_FB4_Pos (4U) 4778 #define CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */ 4779 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */ 4780 #define CAN_F5R2_FB5_Pos (5U) 4781 #define CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */ 4782 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */ 4783 #define CAN_F5R2_FB6_Pos (6U) 4784 #define CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */ 4785 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */ 4786 #define CAN_F5R2_FB7_Pos (7U) 4787 #define CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */ 4788 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */ 4789 #define CAN_F5R2_FB8_Pos (8U) 4790 #define CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */ 4791 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */ 4792 #define CAN_F5R2_FB9_Pos (9U) 4793 #define CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */ 4794 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */ 4795 #define CAN_F5R2_FB10_Pos (10U) 4796 #define CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */ 4797 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */ 4798 #define CAN_F5R2_FB11_Pos (11U) 4799 #define CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */ 4800 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */ 4801 #define CAN_F5R2_FB12_Pos (12U) 4802 #define CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */ 4803 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */ 4804 #define CAN_F5R2_FB13_Pos (13U) 4805 #define CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */ 4806 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */ 4807 #define CAN_F5R2_FB14_Pos (14U) 4808 #define CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */ 4809 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */ 4810 #define CAN_F5R2_FB15_Pos (15U) 4811 #define CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */ 4812 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */ 4813 #define CAN_F5R2_FB16_Pos (16U) 4814 #define CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */ 4815 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */ 4816 #define CAN_F5R2_FB17_Pos (17U) 4817 #define CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */ 4818 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */ 4819 #define CAN_F5R2_FB18_Pos (18U) 4820 #define CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */ 4821 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */ 4822 #define CAN_F5R2_FB19_Pos (19U) 4823 #define CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */ 4824 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */ 4825 #define CAN_F5R2_FB20_Pos (20U) 4826 #define CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */ 4827 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */ 4828 #define CAN_F5R2_FB21_Pos (21U) 4829 #define CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */ 4830 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */ 4831 #define CAN_F5R2_FB22_Pos (22U) 4832 #define CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */ 4833 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */ 4834 #define CAN_F5R2_FB23_Pos (23U) 4835 #define CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */ 4836 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */ 4837 #define CAN_F5R2_FB24_Pos (24U) 4838 #define CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */ 4839 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */ 4840 #define CAN_F5R2_FB25_Pos (25U) 4841 #define CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */ 4842 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */ 4843 #define CAN_F5R2_FB26_Pos (26U) 4844 #define CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */ 4845 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */ 4846 #define CAN_F5R2_FB27_Pos (27U) 4847 #define CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */ 4848 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */ 4849 #define CAN_F5R2_FB28_Pos (28U) 4850 #define CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */ 4851 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */ 4852 #define CAN_F5R2_FB29_Pos (29U) 4853 #define CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */ 4854 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */ 4855 #define CAN_F5R2_FB30_Pos (30U) 4856 #define CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */ 4857 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */ 4858 #define CAN_F5R2_FB31_Pos (31U) 4859 #define CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */ 4860 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */ 4861 4862 /******************* Bit definition for CAN_F6R2 register *******************/ 4863 #define CAN_F6R2_FB0_Pos (0U) 4864 #define CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */ 4865 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */ 4866 #define CAN_F6R2_FB1_Pos (1U) 4867 #define CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */ 4868 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */ 4869 #define CAN_F6R2_FB2_Pos (2U) 4870 #define CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */ 4871 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */ 4872 #define CAN_F6R2_FB3_Pos (3U) 4873 #define CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */ 4874 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */ 4875 #define CAN_F6R2_FB4_Pos (4U) 4876 #define CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */ 4877 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */ 4878 #define CAN_F6R2_FB5_Pos (5U) 4879 #define CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */ 4880 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */ 4881 #define CAN_F6R2_FB6_Pos (6U) 4882 #define CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */ 4883 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */ 4884 #define CAN_F6R2_FB7_Pos (7U) 4885 #define CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */ 4886 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */ 4887 #define CAN_F6R2_FB8_Pos (8U) 4888 #define CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */ 4889 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */ 4890 #define CAN_F6R2_FB9_Pos (9U) 4891 #define CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */ 4892 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */ 4893 #define CAN_F6R2_FB10_Pos (10U) 4894 #define CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */ 4895 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */ 4896 #define CAN_F6R2_FB11_Pos (11U) 4897 #define CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */ 4898 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */ 4899 #define CAN_F6R2_FB12_Pos (12U) 4900 #define CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */ 4901 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */ 4902 #define CAN_F6R2_FB13_Pos (13U) 4903 #define CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */ 4904 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */ 4905 #define CAN_F6R2_FB14_Pos (14U) 4906 #define CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */ 4907 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */ 4908 #define CAN_F6R2_FB15_Pos (15U) 4909 #define CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */ 4910 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */ 4911 #define CAN_F6R2_FB16_Pos (16U) 4912 #define CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */ 4913 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */ 4914 #define CAN_F6R2_FB17_Pos (17U) 4915 #define CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */ 4916 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */ 4917 #define CAN_F6R2_FB18_Pos (18U) 4918 #define CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */ 4919 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */ 4920 #define CAN_F6R2_FB19_Pos (19U) 4921 #define CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */ 4922 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */ 4923 #define CAN_F6R2_FB20_Pos (20U) 4924 #define CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */ 4925 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */ 4926 #define CAN_F6R2_FB21_Pos (21U) 4927 #define CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */ 4928 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */ 4929 #define CAN_F6R2_FB22_Pos (22U) 4930 #define CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */ 4931 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */ 4932 #define CAN_F6R2_FB23_Pos (23U) 4933 #define CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */ 4934 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */ 4935 #define CAN_F6R2_FB24_Pos (24U) 4936 #define CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */ 4937 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */ 4938 #define CAN_F6R2_FB25_Pos (25U) 4939 #define CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */ 4940 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */ 4941 #define CAN_F6R2_FB26_Pos (26U) 4942 #define CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */ 4943 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */ 4944 #define CAN_F6R2_FB27_Pos (27U) 4945 #define CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */ 4946 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */ 4947 #define CAN_F6R2_FB28_Pos (28U) 4948 #define CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */ 4949 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */ 4950 #define CAN_F6R2_FB29_Pos (29U) 4951 #define CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */ 4952 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */ 4953 #define CAN_F6R2_FB30_Pos (30U) 4954 #define CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */ 4955 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */ 4956 #define CAN_F6R2_FB31_Pos (31U) 4957 #define CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */ 4958 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */ 4959 4960 /******************* Bit definition for CAN_F7R2 register *******************/ 4961 #define CAN_F7R2_FB0_Pos (0U) 4962 #define CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */ 4963 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */ 4964 #define CAN_F7R2_FB1_Pos (1U) 4965 #define CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */ 4966 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */ 4967 #define CAN_F7R2_FB2_Pos (2U) 4968 #define CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */ 4969 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */ 4970 #define CAN_F7R2_FB3_Pos (3U) 4971 #define CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */ 4972 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */ 4973 #define CAN_F7R2_FB4_Pos (4U) 4974 #define CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */ 4975 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */ 4976 #define CAN_F7R2_FB5_Pos (5U) 4977 #define CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */ 4978 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */ 4979 #define CAN_F7R2_FB6_Pos (6U) 4980 #define CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */ 4981 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */ 4982 #define CAN_F7R2_FB7_Pos (7U) 4983 #define CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */ 4984 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */ 4985 #define CAN_F7R2_FB8_Pos (8U) 4986 #define CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */ 4987 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */ 4988 #define CAN_F7R2_FB9_Pos (9U) 4989 #define CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */ 4990 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */ 4991 #define CAN_F7R2_FB10_Pos (10U) 4992 #define CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */ 4993 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */ 4994 #define CAN_F7R2_FB11_Pos (11U) 4995 #define CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */ 4996 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */ 4997 #define CAN_F7R2_FB12_Pos (12U) 4998 #define CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */ 4999 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */ 5000 #define CAN_F7R2_FB13_Pos (13U) 5001 #define CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */ 5002 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */ 5003 #define CAN_F7R2_FB14_Pos (14U) 5004 #define CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */ 5005 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */ 5006 #define CAN_F7R2_FB15_Pos (15U) 5007 #define CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */ 5008 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */ 5009 #define CAN_F7R2_FB16_Pos (16U) 5010 #define CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */ 5011 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */ 5012 #define CAN_F7R2_FB17_Pos (17U) 5013 #define CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */ 5014 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */ 5015 #define CAN_F7R2_FB18_Pos (18U) 5016 #define CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */ 5017 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */ 5018 #define CAN_F7R2_FB19_Pos (19U) 5019 #define CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */ 5020 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */ 5021 #define CAN_F7R2_FB20_Pos (20U) 5022 #define CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */ 5023 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */ 5024 #define CAN_F7R2_FB21_Pos (21U) 5025 #define CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */ 5026 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */ 5027 #define CAN_F7R2_FB22_Pos (22U) 5028 #define CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */ 5029 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */ 5030 #define CAN_F7R2_FB23_Pos (23U) 5031 #define CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */ 5032 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */ 5033 #define CAN_F7R2_FB24_Pos (24U) 5034 #define CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */ 5035 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */ 5036 #define CAN_F7R2_FB25_Pos (25U) 5037 #define CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */ 5038 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */ 5039 #define CAN_F7R2_FB26_Pos (26U) 5040 #define CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */ 5041 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */ 5042 #define CAN_F7R2_FB27_Pos (27U) 5043 #define CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */ 5044 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */ 5045 #define CAN_F7R2_FB28_Pos (28U) 5046 #define CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */ 5047 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */ 5048 #define CAN_F7R2_FB29_Pos (29U) 5049 #define CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */ 5050 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */ 5051 #define CAN_F7R2_FB30_Pos (30U) 5052 #define CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */ 5053 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */ 5054 #define CAN_F7R2_FB31_Pos (31U) 5055 #define CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */ 5056 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */ 5057 5058 /******************* Bit definition for CAN_F8R2 register *******************/ 5059 #define CAN_F8R2_FB0_Pos (0U) 5060 #define CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */ 5061 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */ 5062 #define CAN_F8R2_FB1_Pos (1U) 5063 #define CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */ 5064 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */ 5065 #define CAN_F8R2_FB2_Pos (2U) 5066 #define CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */ 5067 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */ 5068 #define CAN_F8R2_FB3_Pos (3U) 5069 #define CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */ 5070 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */ 5071 #define CAN_F8R2_FB4_Pos (4U) 5072 #define CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */ 5073 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */ 5074 #define CAN_F8R2_FB5_Pos (5U) 5075 #define CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */ 5076 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */ 5077 #define CAN_F8R2_FB6_Pos (6U) 5078 #define CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */ 5079 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */ 5080 #define CAN_F8R2_FB7_Pos (7U) 5081 #define CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */ 5082 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */ 5083 #define CAN_F8R2_FB8_Pos (8U) 5084 #define CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */ 5085 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */ 5086 #define CAN_F8R2_FB9_Pos (9U) 5087 #define CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */ 5088 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */ 5089 #define CAN_F8R2_FB10_Pos (10U) 5090 #define CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */ 5091 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */ 5092 #define CAN_F8R2_FB11_Pos (11U) 5093 #define CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */ 5094 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */ 5095 #define CAN_F8R2_FB12_Pos (12U) 5096 #define CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */ 5097 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */ 5098 #define CAN_F8R2_FB13_Pos (13U) 5099 #define CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */ 5100 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */ 5101 #define CAN_F8R2_FB14_Pos (14U) 5102 #define CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */ 5103 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */ 5104 #define CAN_F8R2_FB15_Pos (15U) 5105 #define CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */ 5106 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */ 5107 #define CAN_F8R2_FB16_Pos (16U) 5108 #define CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */ 5109 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */ 5110 #define CAN_F8R2_FB17_Pos (17U) 5111 #define CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */ 5112 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */ 5113 #define CAN_F8R2_FB18_Pos (18U) 5114 #define CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */ 5115 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */ 5116 #define CAN_F8R2_FB19_Pos (19U) 5117 #define CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */ 5118 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */ 5119 #define CAN_F8R2_FB20_Pos (20U) 5120 #define CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */ 5121 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */ 5122 #define CAN_F8R2_FB21_Pos (21U) 5123 #define CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */ 5124 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */ 5125 #define CAN_F8R2_FB22_Pos (22U) 5126 #define CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */ 5127 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */ 5128 #define CAN_F8R2_FB23_Pos (23U) 5129 #define CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */ 5130 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */ 5131 #define CAN_F8R2_FB24_Pos (24U) 5132 #define CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */ 5133 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */ 5134 #define CAN_F8R2_FB25_Pos (25U) 5135 #define CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */ 5136 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */ 5137 #define CAN_F8R2_FB26_Pos (26U) 5138 #define CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */ 5139 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */ 5140 #define CAN_F8R2_FB27_Pos (27U) 5141 #define CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */ 5142 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */ 5143 #define CAN_F8R2_FB28_Pos (28U) 5144 #define CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */ 5145 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */ 5146 #define CAN_F8R2_FB29_Pos (29U) 5147 #define CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */ 5148 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */ 5149 #define CAN_F8R2_FB30_Pos (30U) 5150 #define CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */ 5151 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */ 5152 #define CAN_F8R2_FB31_Pos (31U) 5153 #define CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */ 5154 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */ 5155 5156 /******************* Bit definition for CAN_F9R2 register *******************/ 5157 #define CAN_F9R2_FB0_Pos (0U) 5158 #define CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */ 5159 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */ 5160 #define CAN_F9R2_FB1_Pos (1U) 5161 #define CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */ 5162 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */ 5163 #define CAN_F9R2_FB2_Pos (2U) 5164 #define CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */ 5165 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */ 5166 #define CAN_F9R2_FB3_Pos (3U) 5167 #define CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */ 5168 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */ 5169 #define CAN_F9R2_FB4_Pos (4U) 5170 #define CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */ 5171 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */ 5172 #define CAN_F9R2_FB5_Pos (5U) 5173 #define CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */ 5174 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */ 5175 #define CAN_F9R2_FB6_Pos (6U) 5176 #define CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */ 5177 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */ 5178 #define CAN_F9R2_FB7_Pos (7U) 5179 #define CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */ 5180 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */ 5181 #define CAN_F9R2_FB8_Pos (8U) 5182 #define CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */ 5183 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */ 5184 #define CAN_F9R2_FB9_Pos (9U) 5185 #define CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */ 5186 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */ 5187 #define CAN_F9R2_FB10_Pos (10U) 5188 #define CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */ 5189 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */ 5190 #define CAN_F9R2_FB11_Pos (11U) 5191 #define CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */ 5192 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */ 5193 #define CAN_F9R2_FB12_Pos (12U) 5194 #define CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */ 5195 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */ 5196 #define CAN_F9R2_FB13_Pos (13U) 5197 #define CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */ 5198 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */ 5199 #define CAN_F9R2_FB14_Pos (14U) 5200 #define CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */ 5201 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */ 5202 #define CAN_F9R2_FB15_Pos (15U) 5203 #define CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */ 5204 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */ 5205 #define CAN_F9R2_FB16_Pos (16U) 5206 #define CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */ 5207 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */ 5208 #define CAN_F9R2_FB17_Pos (17U) 5209 #define CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */ 5210 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */ 5211 #define CAN_F9R2_FB18_Pos (18U) 5212 #define CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */ 5213 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */ 5214 #define CAN_F9R2_FB19_Pos (19U) 5215 #define CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */ 5216 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */ 5217 #define CAN_F9R2_FB20_Pos (20U) 5218 #define CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */ 5219 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */ 5220 #define CAN_F9R2_FB21_Pos (21U) 5221 #define CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */ 5222 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */ 5223 #define CAN_F9R2_FB22_Pos (22U) 5224 #define CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */ 5225 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */ 5226 #define CAN_F9R2_FB23_Pos (23U) 5227 #define CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */ 5228 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */ 5229 #define CAN_F9R2_FB24_Pos (24U) 5230 #define CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */ 5231 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */ 5232 #define CAN_F9R2_FB25_Pos (25U) 5233 #define CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */ 5234 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */ 5235 #define CAN_F9R2_FB26_Pos (26U) 5236 #define CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */ 5237 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */ 5238 #define CAN_F9R2_FB27_Pos (27U) 5239 #define CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */ 5240 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */ 5241 #define CAN_F9R2_FB28_Pos (28U) 5242 #define CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */ 5243 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */ 5244 #define CAN_F9R2_FB29_Pos (29U) 5245 #define CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */ 5246 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */ 5247 #define CAN_F9R2_FB30_Pos (30U) 5248 #define CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */ 5249 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */ 5250 #define CAN_F9R2_FB31_Pos (31U) 5251 #define CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */ 5252 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */ 5253 5254 /******************* Bit definition for CAN_F10R2 register ******************/ 5255 #define CAN_F10R2_FB0_Pos (0U) 5256 #define CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */ 5257 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */ 5258 #define CAN_F10R2_FB1_Pos (1U) 5259 #define CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */ 5260 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */ 5261 #define CAN_F10R2_FB2_Pos (2U) 5262 #define CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */ 5263 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */ 5264 #define CAN_F10R2_FB3_Pos (3U) 5265 #define CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */ 5266 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */ 5267 #define CAN_F10R2_FB4_Pos (4U) 5268 #define CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */ 5269 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */ 5270 #define CAN_F10R2_FB5_Pos (5U) 5271 #define CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */ 5272 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */ 5273 #define CAN_F10R2_FB6_Pos (6U) 5274 #define CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */ 5275 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */ 5276 #define CAN_F10R2_FB7_Pos (7U) 5277 #define CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */ 5278 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */ 5279 #define CAN_F10R2_FB8_Pos (8U) 5280 #define CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */ 5281 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */ 5282 #define CAN_F10R2_FB9_Pos (9U) 5283 #define CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */ 5284 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */ 5285 #define CAN_F10R2_FB10_Pos (10U) 5286 #define CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */ 5287 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */ 5288 #define CAN_F10R2_FB11_Pos (11U) 5289 #define CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */ 5290 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */ 5291 #define CAN_F10R2_FB12_Pos (12U) 5292 #define CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */ 5293 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */ 5294 #define CAN_F10R2_FB13_Pos (13U) 5295 #define CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */ 5296 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */ 5297 #define CAN_F10R2_FB14_Pos (14U) 5298 #define CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */ 5299 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */ 5300 #define CAN_F10R2_FB15_Pos (15U) 5301 #define CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */ 5302 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */ 5303 #define CAN_F10R2_FB16_Pos (16U) 5304 #define CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */ 5305 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */ 5306 #define CAN_F10R2_FB17_Pos (17U) 5307 #define CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */ 5308 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */ 5309 #define CAN_F10R2_FB18_Pos (18U) 5310 #define CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */ 5311 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */ 5312 #define CAN_F10R2_FB19_Pos (19U) 5313 #define CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */ 5314 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */ 5315 #define CAN_F10R2_FB20_Pos (20U) 5316 #define CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */ 5317 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */ 5318 #define CAN_F10R2_FB21_Pos (21U) 5319 #define CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */ 5320 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */ 5321 #define CAN_F10R2_FB22_Pos (22U) 5322 #define CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */ 5323 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */ 5324 #define CAN_F10R2_FB23_Pos (23U) 5325 #define CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */ 5326 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */ 5327 #define CAN_F10R2_FB24_Pos (24U) 5328 #define CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */ 5329 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */ 5330 #define CAN_F10R2_FB25_Pos (25U) 5331 #define CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */ 5332 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */ 5333 #define CAN_F10R2_FB26_Pos (26U) 5334 #define CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */ 5335 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */ 5336 #define CAN_F10R2_FB27_Pos (27U) 5337 #define CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */ 5338 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */ 5339 #define CAN_F10R2_FB28_Pos (28U) 5340 #define CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */ 5341 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */ 5342 #define CAN_F10R2_FB29_Pos (29U) 5343 #define CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */ 5344 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */ 5345 #define CAN_F10R2_FB30_Pos (30U) 5346 #define CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */ 5347 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */ 5348 #define CAN_F10R2_FB31_Pos (31U) 5349 #define CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */ 5350 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */ 5351 5352 /******************* Bit definition for CAN_F11R2 register ******************/ 5353 #define CAN_F11R2_FB0_Pos (0U) 5354 #define CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */ 5355 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */ 5356 #define CAN_F11R2_FB1_Pos (1U) 5357 #define CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */ 5358 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */ 5359 #define CAN_F11R2_FB2_Pos (2U) 5360 #define CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */ 5361 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */ 5362 #define CAN_F11R2_FB3_Pos (3U) 5363 #define CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */ 5364 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */ 5365 #define CAN_F11R2_FB4_Pos (4U) 5366 #define CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */ 5367 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */ 5368 #define CAN_F11R2_FB5_Pos (5U) 5369 #define CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */ 5370 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */ 5371 #define CAN_F11R2_FB6_Pos (6U) 5372 #define CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */ 5373 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */ 5374 #define CAN_F11R2_FB7_Pos (7U) 5375 #define CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */ 5376 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */ 5377 #define CAN_F11R2_FB8_Pos (8U) 5378 #define CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */ 5379 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */ 5380 #define CAN_F11R2_FB9_Pos (9U) 5381 #define CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */ 5382 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */ 5383 #define CAN_F11R2_FB10_Pos (10U) 5384 #define CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */ 5385 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */ 5386 #define CAN_F11R2_FB11_Pos (11U) 5387 #define CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */ 5388 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */ 5389 #define CAN_F11R2_FB12_Pos (12U) 5390 #define CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */ 5391 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */ 5392 #define CAN_F11R2_FB13_Pos (13U) 5393 #define CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */ 5394 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */ 5395 #define CAN_F11R2_FB14_Pos (14U) 5396 #define CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */ 5397 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */ 5398 #define CAN_F11R2_FB15_Pos (15U) 5399 #define CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */ 5400 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */ 5401 #define CAN_F11R2_FB16_Pos (16U) 5402 #define CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */ 5403 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */ 5404 #define CAN_F11R2_FB17_Pos (17U) 5405 #define CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */ 5406 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */ 5407 #define CAN_F11R2_FB18_Pos (18U) 5408 #define CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */ 5409 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */ 5410 #define CAN_F11R2_FB19_Pos (19U) 5411 #define CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */ 5412 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */ 5413 #define CAN_F11R2_FB20_Pos (20U) 5414 #define CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */ 5415 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */ 5416 #define CAN_F11R2_FB21_Pos (21U) 5417 #define CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */ 5418 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */ 5419 #define CAN_F11R2_FB22_Pos (22U) 5420 #define CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */ 5421 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */ 5422 #define CAN_F11R2_FB23_Pos (23U) 5423 #define CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */ 5424 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */ 5425 #define CAN_F11R2_FB24_Pos (24U) 5426 #define CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */ 5427 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */ 5428 #define CAN_F11R2_FB25_Pos (25U) 5429 #define CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */ 5430 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */ 5431 #define CAN_F11R2_FB26_Pos (26U) 5432 #define CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */ 5433 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */ 5434 #define CAN_F11R2_FB27_Pos (27U) 5435 #define CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */ 5436 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */ 5437 #define CAN_F11R2_FB28_Pos (28U) 5438 #define CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */ 5439 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */ 5440 #define CAN_F11R2_FB29_Pos (29U) 5441 #define CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */ 5442 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */ 5443 #define CAN_F11R2_FB30_Pos (30U) 5444 #define CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */ 5445 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */ 5446 #define CAN_F11R2_FB31_Pos (31U) 5447 #define CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */ 5448 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */ 5449 5450 /******************* Bit definition for CAN_F12R2 register ******************/ 5451 #define CAN_F12R2_FB0_Pos (0U) 5452 #define CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */ 5453 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */ 5454 #define CAN_F12R2_FB1_Pos (1U) 5455 #define CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */ 5456 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */ 5457 #define CAN_F12R2_FB2_Pos (2U) 5458 #define CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */ 5459 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */ 5460 #define CAN_F12R2_FB3_Pos (3U) 5461 #define CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */ 5462 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */ 5463 #define CAN_F12R2_FB4_Pos (4U) 5464 #define CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */ 5465 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */ 5466 #define CAN_F12R2_FB5_Pos (5U) 5467 #define CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */ 5468 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */ 5469 #define CAN_F12R2_FB6_Pos (6U) 5470 #define CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */ 5471 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */ 5472 #define CAN_F12R2_FB7_Pos (7U) 5473 #define CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */ 5474 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */ 5475 #define CAN_F12R2_FB8_Pos (8U) 5476 #define CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */ 5477 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */ 5478 #define CAN_F12R2_FB9_Pos (9U) 5479 #define CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */ 5480 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */ 5481 #define CAN_F12R2_FB10_Pos (10U) 5482 #define CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */ 5483 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */ 5484 #define CAN_F12R2_FB11_Pos (11U) 5485 #define CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */ 5486 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */ 5487 #define CAN_F12R2_FB12_Pos (12U) 5488 #define CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */ 5489 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */ 5490 #define CAN_F12R2_FB13_Pos (13U) 5491 #define CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */ 5492 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */ 5493 #define CAN_F12R2_FB14_Pos (14U) 5494 #define CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */ 5495 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */ 5496 #define CAN_F12R2_FB15_Pos (15U) 5497 #define CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */ 5498 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */ 5499 #define CAN_F12R2_FB16_Pos (16U) 5500 #define CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */ 5501 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */ 5502 #define CAN_F12R2_FB17_Pos (17U) 5503 #define CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */ 5504 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */ 5505 #define CAN_F12R2_FB18_Pos (18U) 5506 #define CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */ 5507 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */ 5508 #define CAN_F12R2_FB19_Pos (19U) 5509 #define CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */ 5510 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */ 5511 #define CAN_F12R2_FB20_Pos (20U) 5512 #define CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */ 5513 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */ 5514 #define CAN_F12R2_FB21_Pos (21U) 5515 #define CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */ 5516 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */ 5517 #define CAN_F12R2_FB22_Pos (22U) 5518 #define CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */ 5519 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */ 5520 #define CAN_F12R2_FB23_Pos (23U) 5521 #define CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */ 5522 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */ 5523 #define CAN_F12R2_FB24_Pos (24U) 5524 #define CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */ 5525 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */ 5526 #define CAN_F12R2_FB25_Pos (25U) 5527 #define CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */ 5528 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */ 5529 #define CAN_F12R2_FB26_Pos (26U) 5530 #define CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */ 5531 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */ 5532 #define CAN_F12R2_FB27_Pos (27U) 5533 #define CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */ 5534 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */ 5535 #define CAN_F12R2_FB28_Pos (28U) 5536 #define CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */ 5537 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */ 5538 #define CAN_F12R2_FB29_Pos (29U) 5539 #define CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */ 5540 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */ 5541 #define CAN_F12R2_FB30_Pos (30U) 5542 #define CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */ 5543 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */ 5544 #define CAN_F12R2_FB31_Pos (31U) 5545 #define CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */ 5546 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */ 5547 5548 /******************* Bit definition for CAN_F13R2 register ******************/ 5549 #define CAN_F13R2_FB0_Pos (0U) 5550 #define CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */ 5551 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */ 5552 #define CAN_F13R2_FB1_Pos (1U) 5553 #define CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */ 5554 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */ 5555 #define CAN_F13R2_FB2_Pos (2U) 5556 #define CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */ 5557 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */ 5558 #define CAN_F13R2_FB3_Pos (3U) 5559 #define CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */ 5560 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */ 5561 #define CAN_F13R2_FB4_Pos (4U) 5562 #define CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */ 5563 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */ 5564 #define CAN_F13R2_FB5_Pos (5U) 5565 #define CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */ 5566 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */ 5567 #define CAN_F13R2_FB6_Pos (6U) 5568 #define CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */ 5569 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */ 5570 #define CAN_F13R2_FB7_Pos (7U) 5571 #define CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */ 5572 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */ 5573 #define CAN_F13R2_FB8_Pos (8U) 5574 #define CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */ 5575 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */ 5576 #define CAN_F13R2_FB9_Pos (9U) 5577 #define CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */ 5578 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */ 5579 #define CAN_F13R2_FB10_Pos (10U) 5580 #define CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */ 5581 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */ 5582 #define CAN_F13R2_FB11_Pos (11U) 5583 #define CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */ 5584 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */ 5585 #define CAN_F13R2_FB12_Pos (12U) 5586 #define CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */ 5587 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */ 5588 #define CAN_F13R2_FB13_Pos (13U) 5589 #define CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */ 5590 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */ 5591 #define CAN_F13R2_FB14_Pos (14U) 5592 #define CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */ 5593 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */ 5594 #define CAN_F13R2_FB15_Pos (15U) 5595 #define CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */ 5596 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */ 5597 #define CAN_F13R2_FB16_Pos (16U) 5598 #define CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */ 5599 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */ 5600 #define CAN_F13R2_FB17_Pos (17U) 5601 #define CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */ 5602 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */ 5603 #define CAN_F13R2_FB18_Pos (18U) 5604 #define CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */ 5605 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */ 5606 #define CAN_F13R2_FB19_Pos (19U) 5607 #define CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */ 5608 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */ 5609 #define CAN_F13R2_FB20_Pos (20U) 5610 #define CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */ 5611 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */ 5612 #define CAN_F13R2_FB21_Pos (21U) 5613 #define CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */ 5614 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */ 5615 #define CAN_F13R2_FB22_Pos (22U) 5616 #define CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */ 5617 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */ 5618 #define CAN_F13R2_FB23_Pos (23U) 5619 #define CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */ 5620 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */ 5621 #define CAN_F13R2_FB24_Pos (24U) 5622 #define CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */ 5623 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */ 5624 #define CAN_F13R2_FB25_Pos (25U) 5625 #define CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */ 5626 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */ 5627 #define CAN_F13R2_FB26_Pos (26U) 5628 #define CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */ 5629 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */ 5630 #define CAN_F13R2_FB27_Pos (27U) 5631 #define CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */ 5632 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */ 5633 #define CAN_F13R2_FB28_Pos (28U) 5634 #define CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */ 5635 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */ 5636 #define CAN_F13R2_FB29_Pos (29U) 5637 #define CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */ 5638 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */ 5639 #define CAN_F13R2_FB30_Pos (30U) 5640 #define CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */ 5641 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */ 5642 #define CAN_F13R2_FB31_Pos (31U) 5643 #define CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */ 5644 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */ 5645 5646 /******************************************************************************/ 5647 /* */ 5648 /* CRC calculation unit */ 5649 /* */ 5650 /******************************************************************************/ 5651 /******************* Bit definition for CRC_DR register *********************/ 5652 #define CRC_DR_DR_Pos (0U) 5653 #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ 5654 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ 5655 5656 /******************* Bit definition for CRC_IDR register ********************/ 5657 #define CRC_IDR_IDR_Pos (0U) 5658 #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ 5659 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */ 5660 5661 /******************** Bit definition for CRC_CR register ********************/ 5662 #define CRC_CR_RESET_Pos (0U) 5663 #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ 5664 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ 5665 #define CRC_CR_POLYSIZE_Pos (3U) 5666 #define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ 5667 #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ 5668 #define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ 5669 #define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ 5670 #define CRC_CR_REV_IN_Pos (5U) 5671 #define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ 5672 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ 5673 #define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ 5674 #define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ 5675 #define CRC_CR_REV_OUT_Pos (7U) 5676 #define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ 5677 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ 5678 5679 /******************* Bit definition for CRC_INIT register *******************/ 5680 #define CRC_INIT_INIT_Pos (0U) 5681 #define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ 5682 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ 5683 5684 /******************* Bit definition for CRC_POL register ********************/ 5685 #define CRC_POL_POL_Pos (0U) 5686 #define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ 5687 #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ 5688 5689 /******************************************************************************/ 5690 /* */ 5691 /* CRS Clock Recovery System */ 5692 /******************************************************************************/ 5693 5694 /******************* Bit definition for CRS_CR register *********************/ 5695 #define CRS_CR_SYNCOKIE_Pos (0U) 5696 #define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ 5697 #define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ 5698 #define CRS_CR_SYNCWARNIE_Pos (1U) 5699 #define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ 5700 #define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ 5701 #define CRS_CR_ERRIE_Pos (2U) 5702 #define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ 5703 #define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ 5704 #define CRS_CR_ESYNCIE_Pos (3U) 5705 #define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ 5706 #define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ 5707 #define CRS_CR_CEN_Pos (5U) 5708 #define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ 5709 #define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ 5710 #define CRS_CR_AUTOTRIMEN_Pos (6U) 5711 #define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ 5712 #define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ 5713 #define CRS_CR_SWSYNC_Pos (7U) 5714 #define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ 5715 #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ 5716 #define CRS_CR_TRIM_Pos (8U) 5717 #define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ 5718 #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< TRIM[5:0] HSI48 oscillator smooth trimming */ 5719 #define CRS_CR_TRIM_0 (0x01UL << CRS_CR_TRIM_Pos) /*!< 0x00000100 */ 5720 #define CRS_CR_TRIM_1 (0x02UL << CRS_CR_TRIM_Pos) /*!< 0x00000200 */ 5721 #define CRS_CR_TRIM_2 (0x04UL << CRS_CR_TRIM_Pos) /*!< 0x00000400 */ 5722 #define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */ 5723 #define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */ 5724 #define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */ 5725 5726 /******************* Bit definition for CRS_CFGR register *********************/ 5727 #define CRS_CFGR_RELOAD_Pos (0U) 5728 #define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ 5729 #define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ 5730 #define CRS_CFGR_FELIM_Pos (16U) 5731 #define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ 5732 #define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ 5733 5734 #define CRS_CFGR_SYNCDIV_Pos (24U) 5735 #define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ 5736 #define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ 5737 #define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ 5738 #define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ 5739 #define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ 5740 5741 #define CRS_CFGR_SYNCSRC_Pos (28U) 5742 #define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ 5743 #define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ 5744 #define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ 5745 #define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ 5746 5747 #define CRS_CFGR_SYNCPOL_Pos (31U) 5748 #define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ 5749 #define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ 5750 5751 /******************* Bit definition for CRS_ISR register *********************/ 5752 #define CRS_ISR_SYNCOKF_Pos (0U) 5753 #define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ 5754 #define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ 5755 #define CRS_ISR_SYNCWARNF_Pos (1U) 5756 #define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ 5757 #define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ 5758 #define CRS_ISR_ERRF_Pos (2U) 5759 #define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ 5760 #define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ 5761 #define CRS_ISR_ESYNCF_Pos (3U) 5762 #define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ 5763 #define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ 5764 #define CRS_ISR_SYNCERR_Pos (8U) 5765 #define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ 5766 #define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ 5767 #define CRS_ISR_SYNCMISS_Pos (9U) 5768 #define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ 5769 #define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ 5770 #define CRS_ISR_TRIMOVF_Pos (10U) 5771 #define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ 5772 #define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ 5773 #define CRS_ISR_FEDIR_Pos (15U) 5774 #define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ 5775 #define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ 5776 #define CRS_ISR_FECAP_Pos (16U) 5777 #define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ 5778 #define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ 5779 5780 /******************* Bit definition for CRS_ICR register *********************/ 5781 #define CRS_ICR_SYNCOKC_Pos (0U) 5782 #define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ 5783 #define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ 5784 #define CRS_ICR_SYNCWARNC_Pos (1U) 5785 #define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ 5786 #define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ 5787 #define CRS_ICR_ERRC_Pos (2U) 5788 #define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ 5789 #define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ 5790 #define CRS_ICR_ESYNCC_Pos (3U) 5791 #define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ 5792 #define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ 5793 5794 /******************************************************************************/ 5795 /* */ 5796 /* Digital to Analog Converter */ 5797 /* */ 5798 /******************************************************************************/ 5799 /* 5800 * @brief Specific device feature definitions (not present on all devices in the STM32L4 series) 5801 */ 5802 #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ 5803 5804 /******************** Bit definition for DAC_CR register ********************/ 5805 #define DAC_CR_EN1_Pos (0U) 5806 #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ 5807 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */ 5808 #define DAC_CR_TEN1_Pos (2U) 5809 #define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000004 */ 5810 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */ 5811 5812 #define DAC_CR_TSEL1_Pos (3U) 5813 #define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */ 5814 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */ 5815 #define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */ 5816 #define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */ 5817 #define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */ 5818 5819 #define DAC_CR_WAVE1_Pos (6U) 5820 #define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */ 5821 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ 5822 #define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */ 5823 #define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */ 5824 5825 #define DAC_CR_MAMP1_Pos (8U) 5826 #define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */ 5827 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ 5828 #define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */ 5829 #define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */ 5830 #define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */ 5831 #define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */ 5832 5833 #define DAC_CR_DMAEN1_Pos (12U) 5834 #define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */ 5835 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */ 5836 #define DAC_CR_DMAUDRIE1_Pos (13U) 5837 #define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */ 5838 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/ 5839 #define DAC_CR_CEN1_Pos (14U) 5840 #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ 5841 #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/ 5842 5843 #define DAC_CR_EN2_Pos (16U) 5844 #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ 5845 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */ 5846 #define DAC_CR_TEN2_Pos (18U) 5847 #define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00040000 */ 5848 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */ 5849 5850 #define DAC_CR_TSEL2_Pos (19U) 5851 #define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */ 5852 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */ 5853 #define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */ 5854 #define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */ 5855 #define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */ 5856 5857 #define DAC_CR_WAVE2_Pos (22U) 5858 #define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */ 5859 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ 5860 #define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */ 5861 #define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */ 5862 5863 #define DAC_CR_MAMP2_Pos (24U) 5864 #define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */ 5865 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ 5866 #define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */ 5867 #define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */ 5868 #define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */ 5869 #define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */ 5870 5871 #define DAC_CR_DMAEN2_Pos (28U) 5872 #define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */ 5873 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */ 5874 #define DAC_CR_DMAUDRIE2_Pos (29U) 5875 #define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */ 5876 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable >*/ 5877 #define DAC_CR_CEN2_Pos (30U) 5878 #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ 5879 #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!<DAC channel2 calibration enable >*/ 5880 5881 /***************** Bit definition for DAC_SWTRIGR register ******************/ 5882 #define DAC_SWTRIGR_SWTRIG1_Pos (0U) 5883 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ 5884 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */ 5885 #define DAC_SWTRIGR_SWTRIG2_Pos (1U) 5886 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */ 5887 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */ 5888 5889 /***************** Bit definition for DAC_DHR12R1 register ******************/ 5890 #define DAC_DHR12R1_DACC1DHR_Pos (0U) 5891 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */ 5892 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */ 5893 5894 /***************** Bit definition for DAC_DHR12L1 register ******************/ 5895 #define DAC_DHR12L1_DACC1DHR_Pos (4U) 5896 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */ 5897 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */ 5898 5899 /****************** Bit definition for DAC_DHR8R1 register ******************/ 5900 #define DAC_DHR8R1_DACC1DHR_Pos (0U) 5901 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */ 5902 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */ 5903 5904 /***************** Bit definition for DAC_DHR12R2 register ******************/ 5905 #define DAC_DHR12R2_DACC2DHR_Pos (0U) 5906 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */ 5907 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */ 5908 5909 /***************** Bit definition for DAC_DHR12L2 register ******************/ 5910 #define DAC_DHR12L2_DACC2DHR_Pos (4U) 5911 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */ 5912 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */ 5913 5914 /****************** Bit definition for DAC_DHR8R2 register ******************/ 5915 #define DAC_DHR8R2_DACC2DHR_Pos (0U) 5916 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */ 5917 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */ 5918 5919 /***************** Bit definition for DAC_DHR12RD register ******************/ 5920 #define DAC_DHR12RD_DACC1DHR_Pos (0U) 5921 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */ 5922 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */ 5923 #define DAC_DHR12RD_DACC2DHR_Pos (16U) 5924 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */ 5925 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */ 5926 5927 /***************** Bit definition for DAC_DHR12LD register ******************/ 5928 #define DAC_DHR12LD_DACC1DHR_Pos (4U) 5929 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */ 5930 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */ 5931 #define DAC_DHR12LD_DACC2DHR_Pos (20U) 5932 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */ 5933 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */ 5934 5935 /****************** Bit definition for DAC_DHR8RD register ******************/ 5936 #define DAC_DHR8RD_DACC1DHR_Pos (0U) 5937 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */ 5938 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */ 5939 #define DAC_DHR8RD_DACC2DHR_Pos (8U) 5940 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */ 5941 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */ 5942 5943 /******************* Bit definition for DAC_DOR1 register *******************/ 5944 #define DAC_DOR1_DACC1DOR_Pos (0U) 5945 #define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */ 5946 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */ 5947 5948 /******************* Bit definition for DAC_DOR2 register *******************/ 5949 #define DAC_DOR2_DACC2DOR_Pos (0U) 5950 #define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */ 5951 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */ 5952 5953 /******************** Bit definition for DAC_SR register ********************/ 5954 #define DAC_SR_DMAUDR1_Pos (13U) 5955 #define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */ 5956 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */ 5957 #define DAC_SR_CAL_FLAG1_Pos (14U) 5958 #define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */ 5959 #define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */ 5960 #define DAC_SR_BWST1_Pos (15U) 5961 #define DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos) /*!< 0x00008000 */ 5962 #define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */ 5963 5964 #define DAC_SR_DMAUDR2_Pos (29U) 5965 #define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */ 5966 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */ 5967 #define DAC_SR_CAL_FLAG2_Pos (30U) 5968 #define DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */ 5969 #define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!<DAC channel2 calibration offset status */ 5970 #define DAC_SR_BWST2_Pos (31U) 5971 #define DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos) /*!< 0x80000000 */ 5972 #define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!<DAC channel2 busy writing sample time flag */ 5973 5974 /******************* Bit definition for DAC_CCR register ********************/ 5975 #define DAC_CCR_OTRIM1_Pos (0U) 5976 #define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */ 5977 #define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */ 5978 #define DAC_CCR_OTRIM2_Pos (16U) 5979 #define DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */ 5980 #define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!<DAC channel2 offset trimming value */ 5981 5982 /******************* Bit definition for DAC_MCR register *******************/ 5983 #define DAC_MCR_MODE1_Pos (0U) 5984 #define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */ 5985 #define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */ 5986 #define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */ 5987 #define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */ 5988 #define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */ 5989 5990 #define DAC_MCR_MODE2_Pos (16U) 5991 #define DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */ 5992 #define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!<MODE2[2:0] (DAC channel2 mode) */ 5993 #define DAC_MCR_MODE2_0 (0x1UL << DAC_MCR_MODE2_Pos) /*!< 0x00010000 */ 5994 #define DAC_MCR_MODE2_1 (0x2UL << DAC_MCR_MODE2_Pos) /*!< 0x00020000 */ 5995 #define DAC_MCR_MODE2_2 (0x4UL << DAC_MCR_MODE2_Pos) /*!< 0x00040000 */ 5996 5997 /****************** Bit definition for DAC_SHSR1 register ******************/ 5998 #define DAC_SHSR1_TSAMPLE1_Pos (0U) 5999 #define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */ 6000 #define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */ 6001 6002 /****************** Bit definition for DAC_SHSR2 register ******************/ 6003 #define DAC_SHSR2_TSAMPLE2_Pos (0U) 6004 #define DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */ 6005 #define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk /*!<DAC channel2 sample time */ 6006 6007 /****************** Bit definition for DAC_SHHR register ******************/ 6008 #define DAC_SHHR_THOLD1_Pos (0U) 6009 #define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */ 6010 #define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */ 6011 #define DAC_SHHR_THOLD2_Pos (16U) 6012 #define DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */ 6013 #define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!<DAC channel2 hold time */ 6014 6015 /****************** Bit definition for DAC_SHRR register ******************/ 6016 #define DAC_SHRR_TREFRESH1_Pos (0U) 6017 #define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */ 6018 #define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */ 6019 #define DAC_SHRR_TREFRESH2_Pos (16U) 6020 #define DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */ 6021 #define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */ 6022 6023 /******************************************************************************/ 6024 /* */ 6025 /* DMA Controller (DMA) */ 6026 /* */ 6027 /******************************************************************************/ 6028 6029 /******************* Bit definition for DMA_ISR register ********************/ 6030 #define DMA_ISR_GIF1_Pos (0U) 6031 #define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ 6032 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ 6033 #define DMA_ISR_TCIF1_Pos (1U) 6034 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ 6035 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ 6036 #define DMA_ISR_HTIF1_Pos (2U) 6037 #define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ 6038 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ 6039 #define DMA_ISR_TEIF1_Pos (3U) 6040 #define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ 6041 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ 6042 #define DMA_ISR_GIF2_Pos (4U) 6043 #define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ 6044 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ 6045 #define DMA_ISR_TCIF2_Pos (5U) 6046 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ 6047 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ 6048 #define DMA_ISR_HTIF2_Pos (6U) 6049 #define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ 6050 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ 6051 #define DMA_ISR_TEIF2_Pos (7U) 6052 #define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ 6053 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ 6054 #define DMA_ISR_GIF3_Pos (8U) 6055 #define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ 6056 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ 6057 #define DMA_ISR_TCIF3_Pos (9U) 6058 #define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ 6059 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ 6060 #define DMA_ISR_HTIF3_Pos (10U) 6061 #define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ 6062 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ 6063 #define DMA_ISR_TEIF3_Pos (11U) 6064 #define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ 6065 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ 6066 #define DMA_ISR_GIF4_Pos (12U) 6067 #define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ 6068 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ 6069 #define DMA_ISR_TCIF4_Pos (13U) 6070 #define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ 6071 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ 6072 #define DMA_ISR_HTIF4_Pos (14U) 6073 #define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ 6074 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ 6075 #define DMA_ISR_TEIF4_Pos (15U) 6076 #define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ 6077 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ 6078 #define DMA_ISR_GIF5_Pos (16U) 6079 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ 6080 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ 6081 #define DMA_ISR_TCIF5_Pos (17U) 6082 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ 6083 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ 6084 #define DMA_ISR_HTIF5_Pos (18U) 6085 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ 6086 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ 6087 #define DMA_ISR_TEIF5_Pos (19U) 6088 #define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ 6089 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ 6090 #define DMA_ISR_GIF6_Pos (20U) 6091 #define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ 6092 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ 6093 #define DMA_ISR_TCIF6_Pos (21U) 6094 #define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ 6095 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ 6096 #define DMA_ISR_HTIF6_Pos (22U) 6097 #define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ 6098 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ 6099 #define DMA_ISR_TEIF6_Pos (23U) 6100 #define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ 6101 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ 6102 #define DMA_ISR_GIF7_Pos (24U) 6103 #define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ 6104 #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ 6105 #define DMA_ISR_TCIF7_Pos (25U) 6106 #define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ 6107 #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ 6108 #define DMA_ISR_HTIF7_Pos (26U) 6109 #define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ 6110 #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ 6111 #define DMA_ISR_TEIF7_Pos (27U) 6112 #define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ 6113 #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ 6114 6115 /******************* Bit definition for DMA_IFCR register *******************/ 6116 #define DMA_IFCR_CGIF1_Pos (0U) 6117 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ 6118 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */ 6119 #define DMA_IFCR_CTCIF1_Pos (1U) 6120 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ 6121 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ 6122 #define DMA_IFCR_CHTIF1_Pos (2U) 6123 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ 6124 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ 6125 #define DMA_IFCR_CTEIF1_Pos (3U) 6126 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ 6127 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ 6128 #define DMA_IFCR_CGIF2_Pos (4U) 6129 #define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ 6130 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ 6131 #define DMA_IFCR_CTCIF2_Pos (5U) 6132 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ 6133 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ 6134 #define DMA_IFCR_CHTIF2_Pos (6U) 6135 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ 6136 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ 6137 #define DMA_IFCR_CTEIF2_Pos (7U) 6138 #define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ 6139 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ 6140 #define DMA_IFCR_CGIF3_Pos (8U) 6141 #define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ 6142 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ 6143 #define DMA_IFCR_CTCIF3_Pos (9U) 6144 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ 6145 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ 6146 #define DMA_IFCR_CHTIF3_Pos (10U) 6147 #define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ 6148 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ 6149 #define DMA_IFCR_CTEIF3_Pos (11U) 6150 #define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ 6151 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ 6152 #define DMA_IFCR_CGIF4_Pos (12U) 6153 #define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ 6154 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ 6155 #define DMA_IFCR_CTCIF4_Pos (13U) 6156 #define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ 6157 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ 6158 #define DMA_IFCR_CHTIF4_Pos (14U) 6159 #define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ 6160 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ 6161 #define DMA_IFCR_CTEIF4_Pos (15U) 6162 #define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ 6163 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ 6164 #define DMA_IFCR_CGIF5_Pos (16U) 6165 #define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ 6166 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ 6167 #define DMA_IFCR_CTCIF5_Pos (17U) 6168 #define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ 6169 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ 6170 #define DMA_IFCR_CHTIF5_Pos (18U) 6171 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ 6172 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ 6173 #define DMA_IFCR_CTEIF5_Pos (19U) 6174 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ 6175 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ 6176 #define DMA_IFCR_CGIF6_Pos (20U) 6177 #define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ 6178 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ 6179 #define DMA_IFCR_CTCIF6_Pos (21U) 6180 #define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ 6181 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ 6182 #define DMA_IFCR_CHTIF6_Pos (22U) 6183 #define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ 6184 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ 6185 #define DMA_IFCR_CTEIF6_Pos (23U) 6186 #define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ 6187 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ 6188 #define DMA_IFCR_CGIF7_Pos (24U) 6189 #define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ 6190 #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ 6191 #define DMA_IFCR_CTCIF7_Pos (25U) 6192 #define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ 6193 #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ 6194 #define DMA_IFCR_CHTIF7_Pos (26U) 6195 #define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ 6196 #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ 6197 #define DMA_IFCR_CTEIF7_Pos (27U) 6198 #define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ 6199 #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ 6200 6201 /******************* Bit definition for DMA_CCR register ********************/ 6202 #define DMA_CCR_EN_Pos (0U) 6203 #define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ 6204 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ 6205 #define DMA_CCR_TCIE_Pos (1U) 6206 #define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ 6207 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ 6208 #define DMA_CCR_HTIE_Pos (2U) 6209 #define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ 6210 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ 6211 #define DMA_CCR_TEIE_Pos (3U) 6212 #define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ 6213 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ 6214 #define DMA_CCR_DIR_Pos (4U) 6215 #define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ 6216 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ 6217 #define DMA_CCR_CIRC_Pos (5U) 6218 #define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ 6219 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ 6220 #define DMA_CCR_PINC_Pos (6U) 6221 #define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ 6222 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ 6223 #define DMA_CCR_MINC_Pos (7U) 6224 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ 6225 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ 6226 6227 #define DMA_CCR_PSIZE_Pos (8U) 6228 #define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ 6229 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ 6230 #define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ 6231 #define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ 6232 6233 #define DMA_CCR_MSIZE_Pos (10U) 6234 #define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ 6235 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ 6236 #define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ 6237 #define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ 6238 6239 #define DMA_CCR_PL_Pos (12U) 6240 #define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ 6241 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ 6242 #define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ 6243 #define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ 6244 6245 #define DMA_CCR_MEM2MEM_Pos (14U) 6246 #define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ 6247 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ 6248 6249 /****************** Bit definition for DMA_CNDTR register *******************/ 6250 #define DMA_CNDTR_NDT_Pos (0U) 6251 #define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ 6252 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ 6253 6254 /****************** Bit definition for DMA_CPAR register ********************/ 6255 #define DMA_CPAR_PA_Pos (0U) 6256 #define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ 6257 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ 6258 6259 /****************** Bit definition for DMA_CMAR register ********************/ 6260 #define DMA_CMAR_MA_Pos (0U) 6261 #define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ 6262 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ 6263 6264 6265 /******************* Bit definition for DMA_CSELR register *******************/ 6266 #define DMA_CSELR_C1S_Pos (0U) 6267 #define DMA_CSELR_C1S_Msk (0xFUL << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */ 6268 #define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */ 6269 #define DMA_CSELR_C2S_Pos (4U) 6270 #define DMA_CSELR_C2S_Msk (0xFUL << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */ 6271 #define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */ 6272 #define DMA_CSELR_C3S_Pos (8U) 6273 #define DMA_CSELR_C3S_Msk (0xFUL << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */ 6274 #define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */ 6275 #define DMA_CSELR_C4S_Pos (12U) 6276 #define DMA_CSELR_C4S_Msk (0xFUL << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */ 6277 #define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */ 6278 #define DMA_CSELR_C5S_Pos (16U) 6279 #define DMA_CSELR_C5S_Msk (0xFUL << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */ 6280 #define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */ 6281 #define DMA_CSELR_C6S_Pos (20U) 6282 #define DMA_CSELR_C6S_Msk (0xFUL << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */ 6283 #define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */ 6284 #define DMA_CSELR_C7S_Pos (24U) 6285 #define DMA_CSELR_C7S_Msk (0xFUL << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */ 6286 #define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */ 6287 6288 /******************************************************************************/ 6289 /* */ 6290 /* External Interrupt/Event Controller */ 6291 /* */ 6292 /******************************************************************************/ 6293 /******************* Bit definition for EXTI_IMR1 register ******************/ 6294 #define EXTI_IMR1_IM0_Pos (0U) 6295 #define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ 6296 #define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */ 6297 #define EXTI_IMR1_IM1_Pos (1U) 6298 #define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */ 6299 #define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */ 6300 #define EXTI_IMR1_IM2_Pos (2U) 6301 #define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */ 6302 #define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */ 6303 #define EXTI_IMR1_IM3_Pos (3U) 6304 #define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */ 6305 #define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */ 6306 #define EXTI_IMR1_IM4_Pos (4U) 6307 #define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */ 6308 #define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */ 6309 #define EXTI_IMR1_IM5_Pos (5U) 6310 #define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */ 6311 #define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */ 6312 #define EXTI_IMR1_IM6_Pos (6U) 6313 #define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */ 6314 #define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */ 6315 #define EXTI_IMR1_IM7_Pos (7U) 6316 #define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */ 6317 #define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */ 6318 #define EXTI_IMR1_IM8_Pos (8U) 6319 #define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */ 6320 #define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */ 6321 #define EXTI_IMR1_IM9_Pos (9U) 6322 #define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */ 6323 #define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */ 6324 #define EXTI_IMR1_IM10_Pos (10U) 6325 #define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */ 6326 #define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */ 6327 #define EXTI_IMR1_IM11_Pos (11U) 6328 #define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */ 6329 #define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */ 6330 #define EXTI_IMR1_IM12_Pos (12U) 6331 #define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */ 6332 #define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */ 6333 #define EXTI_IMR1_IM13_Pos (13U) 6334 #define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */ 6335 #define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */ 6336 #define EXTI_IMR1_IM14_Pos (14U) 6337 #define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */ 6338 #define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */ 6339 #define EXTI_IMR1_IM15_Pos (15U) 6340 #define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */ 6341 #define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */ 6342 #define EXTI_IMR1_IM16_Pos (16U) 6343 #define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */ 6344 #define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */ 6345 #define EXTI_IMR1_IM17_Pos (17U) 6346 #define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */ 6347 #define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */ 6348 #define EXTI_IMR1_IM18_Pos (18U) 6349 #define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */ 6350 #define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */ 6351 #define EXTI_IMR1_IM19_Pos (19U) 6352 #define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */ 6353 #define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */ 6354 #define EXTI_IMR1_IM20_Pos (20U) 6355 #define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */ 6356 #define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */ 6357 #define EXTI_IMR1_IM21_Pos (21U) 6358 #define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */ 6359 #define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */ 6360 #define EXTI_IMR1_IM22_Pos (22U) 6361 #define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */ 6362 #define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */ 6363 #define EXTI_IMR1_IM23_Pos (23U) 6364 #define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */ 6365 #define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */ 6366 #define EXTI_IMR1_IM24_Pos (24U) 6367 #define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */ 6368 #define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */ 6369 #define EXTI_IMR1_IM25_Pos (25U) 6370 #define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */ 6371 #define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */ 6372 #define EXTI_IMR1_IM26_Pos (26U) 6373 #define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */ 6374 #define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */ 6375 #define EXTI_IMR1_IM27_Pos (27U) 6376 #define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */ 6377 #define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */ 6378 #define EXTI_IMR1_IM28_Pos (28U) 6379 #define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */ 6380 #define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */ 6381 #define EXTI_IMR1_IM31_Pos (31U) 6382 #define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */ 6383 #define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */ 6384 #define EXTI_IMR1_IM_Pos (0U) 6385 #define EXTI_IMR1_IM_Msk (0x9FFFFFFFUL << EXTI_IMR1_IM_Pos) /*!< 0x9FFFFFFF */ 6386 #define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */ 6387 6388 /******************* Bit definition for EXTI_EMR1 register ******************/ 6389 #define EXTI_EMR1_EM0_Pos (0U) 6390 #define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */ 6391 #define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */ 6392 #define EXTI_EMR1_EM1_Pos (1U) 6393 #define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */ 6394 #define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */ 6395 #define EXTI_EMR1_EM2_Pos (2U) 6396 #define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */ 6397 #define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */ 6398 #define EXTI_EMR1_EM3_Pos (3U) 6399 #define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */ 6400 #define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */ 6401 #define EXTI_EMR1_EM4_Pos (4U) 6402 #define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */ 6403 #define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */ 6404 #define EXTI_EMR1_EM5_Pos (5U) 6405 #define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */ 6406 #define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */ 6407 #define EXTI_EMR1_EM6_Pos (6U) 6408 #define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */ 6409 #define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */ 6410 #define EXTI_EMR1_EM7_Pos (7U) 6411 #define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */ 6412 #define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */ 6413 #define EXTI_EMR1_EM8_Pos (8U) 6414 #define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */ 6415 #define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */ 6416 #define EXTI_EMR1_EM9_Pos (9U) 6417 #define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */ 6418 #define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */ 6419 #define EXTI_EMR1_EM10_Pos (10U) 6420 #define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */ 6421 #define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */ 6422 #define EXTI_EMR1_EM11_Pos (11U) 6423 #define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */ 6424 #define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */ 6425 #define EXTI_EMR1_EM12_Pos (12U) 6426 #define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */ 6427 #define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */ 6428 #define EXTI_EMR1_EM13_Pos (13U) 6429 #define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */ 6430 #define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */ 6431 #define EXTI_EMR1_EM14_Pos (14U) 6432 #define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */ 6433 #define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */ 6434 #define EXTI_EMR1_EM15_Pos (15U) 6435 #define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */ 6436 #define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */ 6437 #define EXTI_EMR1_EM16_Pos (16U) 6438 #define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */ 6439 #define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */ 6440 #define EXTI_EMR1_EM17_Pos (17U) 6441 #define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */ 6442 #define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */ 6443 #define EXTI_EMR1_EM18_Pos (18U) 6444 #define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */ 6445 #define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */ 6446 #define EXTI_EMR1_EM19_Pos (19U) 6447 #define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */ 6448 #define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */ 6449 #define EXTI_EMR1_EM20_Pos (20U) 6450 #define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */ 6451 #define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< Event Mask on line 20 */ 6452 #define EXTI_EMR1_EM21_Pos (21U) 6453 #define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */ 6454 #define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */ 6455 #define EXTI_EMR1_EM22_Pos (22U) 6456 #define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */ 6457 #define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< Event Mask on line 22 */ 6458 #define EXTI_EMR1_EM23_Pos (23U) 6459 #define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */ 6460 #define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */ 6461 #define EXTI_EMR1_EM24_Pos (24U) 6462 #define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */ 6463 #define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */ 6464 #define EXTI_EMR1_EM25_Pos (25U) 6465 #define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */ 6466 #define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */ 6467 #define EXTI_EMR1_EM26_Pos (26U) 6468 #define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */ 6469 #define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */ 6470 #define EXTI_EMR1_EM27_Pos (27U) 6471 #define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */ 6472 #define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */ 6473 #define EXTI_EMR1_EM28_Pos (28U) 6474 #define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */ 6475 #define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */ 6476 #define EXTI_EMR1_EM31_Pos (31U) 6477 #define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */ 6478 #define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */ 6479 6480 /****************** Bit definition for EXTI_RTSR1 register ******************/ 6481 #define EXTI_RTSR1_RT0_Pos (0U) 6482 #define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */ 6483 #define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */ 6484 #define EXTI_RTSR1_RT1_Pos (1U) 6485 #define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */ 6486 #define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */ 6487 #define EXTI_RTSR1_RT2_Pos (2U) 6488 #define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */ 6489 #define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */ 6490 #define EXTI_RTSR1_RT3_Pos (3U) 6491 #define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */ 6492 #define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */ 6493 #define EXTI_RTSR1_RT4_Pos (4U) 6494 #define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */ 6495 #define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */ 6496 #define EXTI_RTSR1_RT5_Pos (5U) 6497 #define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */ 6498 #define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */ 6499 #define EXTI_RTSR1_RT6_Pos (6U) 6500 #define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */ 6501 #define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */ 6502 #define EXTI_RTSR1_RT7_Pos (7U) 6503 #define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */ 6504 #define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */ 6505 #define EXTI_RTSR1_RT8_Pos (8U) 6506 #define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */ 6507 #define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */ 6508 #define EXTI_RTSR1_RT9_Pos (9U) 6509 #define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */ 6510 #define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */ 6511 #define EXTI_RTSR1_RT10_Pos (10U) 6512 #define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */ 6513 #define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */ 6514 #define EXTI_RTSR1_RT11_Pos (11U) 6515 #define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */ 6516 #define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */ 6517 #define EXTI_RTSR1_RT12_Pos (12U) 6518 #define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */ 6519 #define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */ 6520 #define EXTI_RTSR1_RT13_Pos (13U) 6521 #define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */ 6522 #define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */ 6523 #define EXTI_RTSR1_RT14_Pos (14U) 6524 #define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */ 6525 #define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */ 6526 #define EXTI_RTSR1_RT15_Pos (15U) 6527 #define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */ 6528 #define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */ 6529 #define EXTI_RTSR1_RT16_Pos (16U) 6530 #define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */ 6531 #define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */ 6532 #define EXTI_RTSR1_RT18_Pos (18U) 6533 #define EXTI_RTSR1_RT18_Msk (0x1UL << EXTI_RTSR1_RT18_Pos) /*!< 0x00040000 */ 6534 #define EXTI_RTSR1_RT18 EXTI_RTSR1_RT18_Msk /*!< Rising trigger event configuration bit of line 18 */ 6535 #define EXTI_RTSR1_RT19_Pos (19U) 6536 #define EXTI_RTSR1_RT19_Msk (0x1UL << EXTI_RTSR1_RT19_Pos) /*!< 0x00080000 */ 6537 #define EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */ 6538 #define EXTI_RTSR1_RT20_Pos (20U) 6539 #define EXTI_RTSR1_RT20_Msk (0x1UL << EXTI_RTSR1_RT20_Pos) /*!< 0x00100000 */ 6540 #define EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */ 6541 #define EXTI_RTSR1_RT21_Pos (21U) 6542 #define EXTI_RTSR1_RT21_Msk (0x1UL << EXTI_RTSR1_RT21_Pos) /*!< 0x00200000 */ 6543 #define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */ 6544 #define EXTI_RTSR1_RT22_Pos (22U) 6545 #define EXTI_RTSR1_RT22_Msk (0x1UL << EXTI_RTSR1_RT22_Pos) /*!< 0x00400000 */ 6546 #define EXTI_RTSR1_RT22 EXTI_RTSR1_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */ 6547 6548 /****************** Bit definition for EXTI_FTSR1 register ******************/ 6549 #define EXTI_FTSR1_FT0_Pos (0U) 6550 #define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */ 6551 #define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */ 6552 #define EXTI_FTSR1_FT1_Pos (1U) 6553 #define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */ 6554 #define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */ 6555 #define EXTI_FTSR1_FT2_Pos (2U) 6556 #define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */ 6557 #define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */ 6558 #define EXTI_FTSR1_FT3_Pos (3U) 6559 #define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */ 6560 #define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */ 6561 #define EXTI_FTSR1_FT4_Pos (4U) 6562 #define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */ 6563 #define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */ 6564 #define EXTI_FTSR1_FT5_Pos (5U) 6565 #define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */ 6566 #define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */ 6567 #define EXTI_FTSR1_FT6_Pos (6U) 6568 #define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */ 6569 #define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */ 6570 #define EXTI_FTSR1_FT7_Pos (7U) 6571 #define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */ 6572 #define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */ 6573 #define EXTI_FTSR1_FT8_Pos (8U) 6574 #define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */ 6575 #define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */ 6576 #define EXTI_FTSR1_FT9_Pos (9U) 6577 #define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */ 6578 #define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */ 6579 #define EXTI_FTSR1_FT10_Pos (10U) 6580 #define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */ 6581 #define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */ 6582 #define EXTI_FTSR1_FT11_Pos (11U) 6583 #define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */ 6584 #define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */ 6585 #define EXTI_FTSR1_FT12_Pos (12U) 6586 #define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */ 6587 #define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */ 6588 #define EXTI_FTSR1_FT13_Pos (13U) 6589 #define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */ 6590 #define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */ 6591 #define EXTI_FTSR1_FT14_Pos (14U) 6592 #define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */ 6593 #define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */ 6594 #define EXTI_FTSR1_FT15_Pos (15U) 6595 #define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */ 6596 #define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */ 6597 #define EXTI_FTSR1_FT16_Pos (16U) 6598 #define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */ 6599 #define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */ 6600 #define EXTI_FTSR1_FT18_Pos (18U) 6601 #define EXTI_FTSR1_FT18_Msk (0x1UL << EXTI_FTSR1_FT18_Pos) /*!< 0x00040000 */ 6602 #define EXTI_FTSR1_FT18 EXTI_FTSR1_FT18_Msk /*!< Falling trigger event configuration bit of line 18 */ 6603 #define EXTI_FTSR1_FT19_Pos (19U) 6604 #define EXTI_FTSR1_FT19_Msk (0x1UL << EXTI_FTSR1_FT19_Pos) /*!< 0x00080000 */ 6605 #define EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */ 6606 #define EXTI_FTSR1_FT20_Pos (20U) 6607 #define EXTI_FTSR1_FT20_Msk (0x1UL << EXTI_FTSR1_FT20_Pos) /*!< 0x00100000 */ 6608 #define EXTI_FTSR1_FT20 EXTI_FTSR1_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */ 6609 #define EXTI_FTSR1_FT21_Pos (21U) 6610 #define EXTI_FTSR1_FT21_Msk (0x1UL << EXTI_FTSR1_FT21_Pos) /*!< 0x00200000 */ 6611 #define EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */ 6612 #define EXTI_FTSR1_FT22_Pos (22U) 6613 #define EXTI_FTSR1_FT22_Msk (0x1UL << EXTI_FTSR1_FT22_Pos) /*!< 0x00400000 */ 6614 #define EXTI_FTSR1_FT22 EXTI_FTSR1_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */ 6615 6616 /****************** Bit definition for EXTI_SWIER1 register *****************/ 6617 #define EXTI_SWIER1_SWI0_Pos (0U) 6618 #define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */ 6619 #define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */ 6620 #define EXTI_SWIER1_SWI1_Pos (1U) 6621 #define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */ 6622 #define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */ 6623 #define EXTI_SWIER1_SWI2_Pos (2U) 6624 #define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */ 6625 #define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */ 6626 #define EXTI_SWIER1_SWI3_Pos (3U) 6627 #define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */ 6628 #define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */ 6629 #define EXTI_SWIER1_SWI4_Pos (4U) 6630 #define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */ 6631 #define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */ 6632 #define EXTI_SWIER1_SWI5_Pos (5U) 6633 #define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */ 6634 #define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */ 6635 #define EXTI_SWIER1_SWI6_Pos (6U) 6636 #define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */ 6637 #define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */ 6638 #define EXTI_SWIER1_SWI7_Pos (7U) 6639 #define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */ 6640 #define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */ 6641 #define EXTI_SWIER1_SWI8_Pos (8U) 6642 #define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */ 6643 #define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */ 6644 #define EXTI_SWIER1_SWI9_Pos (9U) 6645 #define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */ 6646 #define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */ 6647 #define EXTI_SWIER1_SWI10_Pos (10U) 6648 #define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */ 6649 #define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */ 6650 #define EXTI_SWIER1_SWI11_Pos (11U) 6651 #define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */ 6652 #define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */ 6653 #define EXTI_SWIER1_SWI12_Pos (12U) 6654 #define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */ 6655 #define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */ 6656 #define EXTI_SWIER1_SWI13_Pos (13U) 6657 #define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */ 6658 #define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */ 6659 #define EXTI_SWIER1_SWI14_Pos (14U) 6660 #define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */ 6661 #define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */ 6662 #define EXTI_SWIER1_SWI15_Pos (15U) 6663 #define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */ 6664 #define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */ 6665 #define EXTI_SWIER1_SWI16_Pos (16U) 6666 #define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */ 6667 #define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */ 6668 #define EXTI_SWIER1_SWI18_Pos (18U) 6669 #define EXTI_SWIER1_SWI18_Msk (0x1UL << EXTI_SWIER1_SWI18_Pos) /*!< 0x00040000 */ 6670 #define EXTI_SWIER1_SWI18 EXTI_SWIER1_SWI18_Msk /*!< Software Interrupt on line 18 */ 6671 #define EXTI_SWIER1_SWI19_Pos (19U) 6672 #define EXTI_SWIER1_SWI19_Msk (0x1UL << EXTI_SWIER1_SWI19_Pos) /*!< 0x00080000 */ 6673 #define EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk /*!< Software Interrupt on line 19 */ 6674 #define EXTI_SWIER1_SWI20_Pos (20U) 6675 #define EXTI_SWIER1_SWI20_Msk (0x1UL << EXTI_SWIER1_SWI20_Pos) /*!< 0x00100000 */ 6676 #define EXTI_SWIER1_SWI20 EXTI_SWIER1_SWI20_Msk /*!< Software Interrupt on line 20 */ 6677 #define EXTI_SWIER1_SWI21_Pos (21U) 6678 #define EXTI_SWIER1_SWI21_Msk (0x1UL << EXTI_SWIER1_SWI21_Pos) /*!< 0x00200000 */ 6679 #define EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk /*!< Software Interrupt on line 21 */ 6680 #define EXTI_SWIER1_SWI22_Pos (22U) 6681 #define EXTI_SWIER1_SWI22_Msk (0x1UL << EXTI_SWIER1_SWI22_Pos) /*!< 0x00400000 */ 6682 #define EXTI_SWIER1_SWI22 EXTI_SWIER1_SWI22_Msk /*!< Software Interrupt on line 22 */ 6683 6684 /******************* Bit definition for EXTI_PR1 register *******************/ 6685 #define EXTI_PR1_PIF0_Pos (0U) 6686 #define EXTI_PR1_PIF0_Msk (0x1UL << EXTI_PR1_PIF0_Pos) /*!< 0x00000001 */ 6687 #define EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk /*!< Pending bit for line 0 */ 6688 #define EXTI_PR1_PIF1_Pos (1U) 6689 #define EXTI_PR1_PIF1_Msk (0x1UL << EXTI_PR1_PIF1_Pos) /*!< 0x00000002 */ 6690 #define EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk /*!< Pending bit for line 1 */ 6691 #define EXTI_PR1_PIF2_Pos (2U) 6692 #define EXTI_PR1_PIF2_Msk (0x1UL << EXTI_PR1_PIF2_Pos) /*!< 0x00000004 */ 6693 #define EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk /*!< Pending bit for line 2 */ 6694 #define EXTI_PR1_PIF3_Pos (3U) 6695 #define EXTI_PR1_PIF3_Msk (0x1UL << EXTI_PR1_PIF3_Pos) /*!< 0x00000008 */ 6696 #define EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk /*!< Pending bit for line 3 */ 6697 #define EXTI_PR1_PIF4_Pos (4U) 6698 #define EXTI_PR1_PIF4_Msk (0x1UL << EXTI_PR1_PIF4_Pos) /*!< 0x00000010 */ 6699 #define EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk /*!< Pending bit for line 4 */ 6700 #define EXTI_PR1_PIF5_Pos (5U) 6701 #define EXTI_PR1_PIF5_Msk (0x1UL << EXTI_PR1_PIF5_Pos) /*!< 0x00000020 */ 6702 #define EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk /*!< Pending bit for line 5 */ 6703 #define EXTI_PR1_PIF6_Pos (6U) 6704 #define EXTI_PR1_PIF6_Msk (0x1UL << EXTI_PR1_PIF6_Pos) /*!< 0x00000040 */ 6705 #define EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk /*!< Pending bit for line 6 */ 6706 #define EXTI_PR1_PIF7_Pos (7U) 6707 #define EXTI_PR1_PIF7_Msk (0x1UL << EXTI_PR1_PIF7_Pos) /*!< 0x00000080 */ 6708 #define EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk /*!< Pending bit for line 7 */ 6709 #define EXTI_PR1_PIF8_Pos (8U) 6710 #define EXTI_PR1_PIF8_Msk (0x1UL << EXTI_PR1_PIF8_Pos) /*!< 0x00000100 */ 6711 #define EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk /*!< Pending bit for line 8 */ 6712 #define EXTI_PR1_PIF9_Pos (9U) 6713 #define EXTI_PR1_PIF9_Msk (0x1UL << EXTI_PR1_PIF9_Pos) /*!< 0x00000200 */ 6714 #define EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk /*!< Pending bit for line 9 */ 6715 #define EXTI_PR1_PIF10_Pos (10U) 6716 #define EXTI_PR1_PIF10_Msk (0x1UL << EXTI_PR1_PIF10_Pos) /*!< 0x00000400 */ 6717 #define EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk /*!< Pending bit for line 10 */ 6718 #define EXTI_PR1_PIF11_Pos (11U) 6719 #define EXTI_PR1_PIF11_Msk (0x1UL << EXTI_PR1_PIF11_Pos) /*!< 0x00000800 */ 6720 #define EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk /*!< Pending bit for line 11 */ 6721 #define EXTI_PR1_PIF12_Pos (12U) 6722 #define EXTI_PR1_PIF12_Msk (0x1UL << EXTI_PR1_PIF12_Pos) /*!< 0x00001000 */ 6723 #define EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk /*!< Pending bit for line 12 */ 6724 #define EXTI_PR1_PIF13_Pos (13U) 6725 #define EXTI_PR1_PIF13_Msk (0x1UL << EXTI_PR1_PIF13_Pos) /*!< 0x00002000 */ 6726 #define EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk /*!< Pending bit for line 13 */ 6727 #define EXTI_PR1_PIF14_Pos (14U) 6728 #define EXTI_PR1_PIF14_Msk (0x1UL << EXTI_PR1_PIF14_Pos) /*!< 0x00004000 */ 6729 #define EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk /*!< Pending bit for line 14 */ 6730 #define EXTI_PR1_PIF15_Pos (15U) 6731 #define EXTI_PR1_PIF15_Msk (0x1UL << EXTI_PR1_PIF15_Pos) /*!< 0x00008000 */ 6732 #define EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk /*!< Pending bit for line 15 */ 6733 #define EXTI_PR1_PIF16_Pos (16U) 6734 #define EXTI_PR1_PIF16_Msk (0x1UL << EXTI_PR1_PIF16_Pos) /*!< 0x00010000 */ 6735 #define EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk /*!< Pending bit for line 16 */ 6736 #define EXTI_PR1_PIF18_Pos (18U) 6737 #define EXTI_PR1_PIF18_Msk (0x1UL << EXTI_PR1_PIF18_Pos) /*!< 0x00040000 */ 6738 #define EXTI_PR1_PIF18 EXTI_PR1_PIF18_Msk /*!< Pending bit for line 18 */ 6739 #define EXTI_PR1_PIF19_Pos (19U) 6740 #define EXTI_PR1_PIF19_Msk (0x1UL << EXTI_PR1_PIF19_Pos) /*!< 0x00080000 */ 6741 #define EXTI_PR1_PIF19 EXTI_PR1_PIF19_Msk /*!< Pending bit for line 19 */ 6742 #define EXTI_PR1_PIF20_Pos (20U) 6743 #define EXTI_PR1_PIF20_Msk (0x1UL << EXTI_PR1_PIF20_Pos) /*!< 0x00100000 */ 6744 #define EXTI_PR1_PIF20 EXTI_PR1_PIF20_Msk /*!< Pending bit for line 20 */ 6745 #define EXTI_PR1_PIF21_Pos (21U) 6746 #define EXTI_PR1_PIF21_Msk (0x1UL << EXTI_PR1_PIF21_Pos) /*!< 0x00200000 */ 6747 #define EXTI_PR1_PIF21 EXTI_PR1_PIF21_Msk /*!< Pending bit for line 21 */ 6748 #define EXTI_PR1_PIF22_Pos (22U) 6749 #define EXTI_PR1_PIF22_Msk (0x1UL << EXTI_PR1_PIF22_Pos) /*!< 0x00400000 */ 6750 #define EXTI_PR1_PIF22 EXTI_PR1_PIF22_Msk /*!< Pending bit for line 22 */ 6751 6752 /******************* Bit definition for EXTI_IMR2 register ******************/ 6753 #define EXTI_IMR2_IM32_Pos (0U) 6754 #define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */ 6755 #define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< Interrupt Mask on line 32 */ 6756 #define EXTI_IMR2_IM33_Pos (1U) 6757 #define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */ 6758 #define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */ 6759 #define EXTI_IMR2_IM34_Pos (2U) 6760 #define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */ 6761 #define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */ 6762 #define EXTI_IMR2_IM35_Pos (3U) 6763 #define EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */ 6764 #define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */ 6765 #define EXTI_IMR2_IM37_Pos (5U) 6766 #define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */ 6767 #define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */ 6768 #define EXTI_IMR2_IM38_Pos (6U) 6769 #define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */ 6770 #define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */ 6771 #define EXTI_IMR2_IM_Pos (0U) 6772 #define EXTI_IMR2_IM_Msk (0x6FUL << EXTI_IMR2_IM_Pos) /*!< 0x0000006F */ 6773 #define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */ 6774 6775 /******************* Bit definition for EXTI_EMR2 register ******************/ 6776 #define EXTI_EMR2_EM32_Pos (0U) 6777 #define EXTI_EMR2_EM32_Msk (0x1UL << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */ 6778 #define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< Event Mask on line 32 */ 6779 #define EXTI_EMR2_EM33_Pos (1U) 6780 #define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */ 6781 #define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33 */ 6782 #define EXTI_EMR2_EM34_Pos (2U) 6783 #define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */ 6784 #define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34 */ 6785 #define EXTI_EMR2_EM35_Pos (3U) 6786 #define EXTI_EMR2_EM35_Msk (0x1UL << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */ 6787 #define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35 */ 6788 #define EXTI_EMR2_EM37_Pos (5U) 6789 #define EXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */ 6790 #define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37 */ 6791 #define EXTI_EMR2_EM38_Pos (6U) 6792 #define EXTI_EMR2_EM38_Msk (0x1UL << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */ 6793 #define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */ 6794 #define EXTI_EMR2_EM_Pos (0U) 6795 #define EXTI_EMR2_EM_Msk (0x6FUL << EXTI_EMR2_EM_Pos) /*!< 0x0000006F */ 6796 #define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */ 6797 6798 /****************** Bit definition for EXTI_RTSR2 register ******************/ 6799 #define EXTI_RTSR2_RT35_Pos (3U) 6800 #define EXTI_RTSR2_RT35_Msk (0x1UL << EXTI_RTSR2_RT35_Pos) /*!< 0x00000008 */ 6801 #define EXTI_RTSR2_RT35 EXTI_RTSR2_RT35_Msk /*!< Rising trigger event configuration bit of line 35 */ 6802 #define EXTI_RTSR2_RT37_Pos (5U) 6803 #define EXTI_RTSR2_RT37_Msk (0x1UL << EXTI_RTSR2_RT37_Pos) /*!< 0x00000020 */ 6804 #define EXTI_RTSR2_RT37 EXTI_RTSR2_RT37_Msk /*!< Rising trigger event configuration bit of line 37 */ 6805 #define EXTI_RTSR2_RT38_Pos (6U) 6806 #define EXTI_RTSR2_RT38_Msk (0x1UL << EXTI_RTSR2_RT38_Pos) /*!< 0x00000040 */ 6807 #define EXTI_RTSR2_RT38 EXTI_RTSR2_RT38_Msk /*!< Rising trigger event configuration bit of line 38 */ 6808 6809 /****************** Bit definition for EXTI_FTSR2 register ******************/ 6810 #define EXTI_FTSR2_FT35_Pos (3U) 6811 #define EXTI_FTSR2_FT35_Msk (0x1UL << EXTI_FTSR2_FT35_Pos) /*!< 0x00000008 */ 6812 #define EXTI_FTSR2_FT35 EXTI_FTSR2_FT35_Msk /*!< Falling trigger event configuration bit of line 35 */ 6813 #define EXTI_FTSR2_FT37_Pos (5U) 6814 #define EXTI_FTSR2_FT37_Msk (0x1UL << EXTI_FTSR2_FT37_Pos) /*!< 0x00000020 */ 6815 #define EXTI_FTSR2_FT37 EXTI_FTSR2_FT37_Msk /*!< Falling trigger event configuration bit of line 37 */ 6816 #define EXTI_FTSR2_FT38_Pos (6U) 6817 #define EXTI_FTSR2_FT38_Msk (0x1UL << EXTI_FTSR2_FT38_Pos) /*!< 0x00000040 */ 6818 #define EXTI_FTSR2_FT38 EXTI_FTSR2_FT38_Msk /*!< Falling trigger event configuration bit of line 38 */ 6819 6820 /****************** Bit definition for EXTI_SWIER2 register *****************/ 6821 #define EXTI_SWIER2_SWI35_Pos (3U) 6822 #define EXTI_SWIER2_SWI35_Msk (0x1UL << EXTI_SWIER2_SWI35_Pos) /*!< 0x00000008 */ 6823 #define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWI35_Msk /*!< Software Interrupt on line 35 */ 6824 #define EXTI_SWIER2_SWI37_Pos (5U) 6825 #define EXTI_SWIER2_SWI37_Msk (0x1UL << EXTI_SWIER2_SWI37_Pos) /*!< 0x00000020 */ 6826 #define EXTI_SWIER2_SWI37 EXTI_SWIER2_SWI37_Msk /*!< Software Interrupt on line 37 */ 6827 #define EXTI_SWIER2_SWI38_Pos (6U) 6828 #define EXTI_SWIER2_SWI38_Msk (0x1UL << EXTI_SWIER2_SWI38_Pos) /*!< 0x00000040 */ 6829 #define EXTI_SWIER2_SWI38 EXTI_SWIER2_SWI38_Msk /*!< Software Interrupt on line 38 */ 6830 6831 /******************* Bit definition for EXTI_PR2 register *******************/ 6832 #define EXTI_PR2_PIF35_Pos (3U) 6833 #define EXTI_PR2_PIF35_Msk (0x1UL << EXTI_PR2_PIF35_Pos) /*!< 0x00000008 */ 6834 #define EXTI_PR2_PIF35 EXTI_PR2_PIF35_Msk /*!< Pending bit for line 35 */ 6835 #define EXTI_PR2_PIF37_Pos (5U) 6836 #define EXTI_PR2_PIF37_Msk (0x1UL << EXTI_PR2_PIF37_Pos) /*!< 0x00000020 */ 6837 #define EXTI_PR2_PIF37 EXTI_PR2_PIF37_Msk /*!< Pending bit for line 37 */ 6838 #define EXTI_PR2_PIF38_Pos (6U) 6839 #define EXTI_PR2_PIF38_Msk (0x1UL << EXTI_PR2_PIF38_Pos) /*!< 0x00000040 */ 6840 #define EXTI_PR2_PIF38 EXTI_PR2_PIF38_Msk /*!< Pending bit for line 38 */ 6841 6842 6843 /******************************************************************************/ 6844 /* */ 6845 /* FLASH */ 6846 /* */ 6847 /******************************************************************************/ 6848 /******************* Bits definition for FLASH_ACR register *****************/ 6849 #define FLASH_ACR_LATENCY_Pos (0U) 6850 #define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */ 6851 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk 6852 #define FLASH_ACR_LATENCY_0WS (0x00000000UL) 6853 #define FLASH_ACR_LATENCY_1WS (0x00000001UL) 6854 #define FLASH_ACR_LATENCY_2WS (0x00000002UL) 6855 #define FLASH_ACR_LATENCY_3WS (0x00000003UL) 6856 #define FLASH_ACR_LATENCY_4WS (0x00000004UL) 6857 #define FLASH_ACR_PRFTEN_Pos (8U) 6858 #define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ 6859 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk 6860 #define FLASH_ACR_ICEN_Pos (9U) 6861 #define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */ 6862 #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk 6863 #define FLASH_ACR_DCEN_Pos (10U) 6864 #define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */ 6865 #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk 6866 #define FLASH_ACR_ICRST_Pos (11U) 6867 #define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */ 6868 #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk 6869 #define FLASH_ACR_DCRST_Pos (12U) 6870 #define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */ 6871 #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk 6872 #define FLASH_ACR_RUN_PD_Pos (13U) 6873 #define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos) /*!< 0x00002000 */ 6874 #define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash power down mode during run */ 6875 #define FLASH_ACR_SLEEP_PD_Pos (14U) 6876 #define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */ 6877 #define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power down mode during sleep */ 6878 6879 /******************* Bits definition for FLASH_SR register ******************/ 6880 #define FLASH_SR_EOP_Pos (0U) 6881 #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */ 6882 #define FLASH_SR_EOP FLASH_SR_EOP_Msk 6883 #define FLASH_SR_OPERR_Pos (1U) 6884 #define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */ 6885 #define FLASH_SR_OPERR FLASH_SR_OPERR_Msk 6886 #define FLASH_SR_PROGERR_Pos (3U) 6887 #define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */ 6888 #define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk 6889 #define FLASH_SR_WRPERR_Pos (4U) 6890 #define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */ 6891 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk 6892 #define FLASH_SR_PGAERR_Pos (5U) 6893 #define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */ 6894 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk 6895 #define FLASH_SR_SIZERR_Pos (6U) 6896 #define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */ 6897 #define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk 6898 #define FLASH_SR_PGSERR_Pos (7U) 6899 #define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */ 6900 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk 6901 #define FLASH_SR_MISERR_Pos (8U) 6902 #define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */ 6903 #define FLASH_SR_MISERR FLASH_SR_MISERR_Msk 6904 #define FLASH_SR_FASTERR_Pos (9U) 6905 #define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */ 6906 #define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk 6907 #define FLASH_SR_RDERR_Pos (14U) 6908 #define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */ 6909 #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk 6910 #define FLASH_SR_OPTVERR_Pos (15U) 6911 #define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */ 6912 #define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk 6913 #define FLASH_SR_BSY_Pos (16U) 6914 #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00010000 */ 6915 #define FLASH_SR_BSY FLASH_SR_BSY_Msk 6916 #define FLASH_SR_PEMPTY_Pos (17U) 6917 #define FLASH_SR_PEMPTY_Msk (0x1UL << FLASH_SR_PEMPTY_Pos) /*!< 0x00020000 */ 6918 #define FLASH_SR_PEMPTY FLASH_SR_PEMPTY_Msk 6919 6920 /******************* Bits definition for FLASH_CR register ******************/ 6921 #define FLASH_CR_PG_Pos (0U) 6922 #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */ 6923 #define FLASH_CR_PG FLASH_CR_PG_Msk 6924 #define FLASH_CR_PER_Pos (1U) 6925 #define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */ 6926 #define FLASH_CR_PER FLASH_CR_PER_Msk 6927 #define FLASH_CR_MER1_Pos (2U) 6928 #define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */ 6929 #define FLASH_CR_MER1 FLASH_CR_MER1_Msk 6930 #define FLASH_CR_PNB_Pos (3U) 6931 #define FLASH_CR_PNB_Msk (0x7FUL << FLASH_CR_PNB_Pos) /*!< 0x000003F8 */ 6932 #define FLASH_CR_PNB FLASH_CR_PNB_Msk 6933 #define FLASH_CR_STRT_Pos (16U) 6934 #define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */ 6935 #define FLASH_CR_STRT FLASH_CR_STRT_Msk 6936 #define FLASH_CR_OPTSTRT_Pos (17U) 6937 #define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */ 6938 #define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk 6939 #define FLASH_CR_FSTPG_Pos (18U) 6940 #define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */ 6941 #define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk 6942 #define FLASH_CR_EOPIE_Pos (24U) 6943 #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ 6944 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk 6945 #define FLASH_CR_ERRIE_Pos (25U) 6946 #define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */ 6947 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk 6948 #define FLASH_CR_RDERRIE_Pos (26U) 6949 #define FLASH_CR_RDERRIE_Msk (0x1UL << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */ 6950 #define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk 6951 #define FLASH_CR_OBL_LAUNCH_Pos (27U) 6952 #define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ 6953 #define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk 6954 #define FLASH_CR_OPTLOCK_Pos (30U) 6955 #define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */ 6956 #define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk 6957 #define FLASH_CR_LOCK_Pos (31U) 6958 #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ 6959 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk 6960 6961 /******************* Bits definition for FLASH_ECCR register ***************/ 6962 #define FLASH_ECCR_ADDR_ECC_Pos (0U) 6963 #define FLASH_ECCR_ADDR_ECC_Msk (0x7FFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0007FFFF */ 6964 #define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk 6965 #define FLASH_ECCR_SYSF_ECC_Pos (20U) 6966 #define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */ 6967 #define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk 6968 #define FLASH_ECCR_ECCIE_Pos (24U) 6969 #define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */ 6970 #define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk 6971 #define FLASH_ECCR_ECCC_Pos (30U) 6972 #define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ 6973 #define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk 6974 #define FLASH_ECCR_ECCD_Pos (31U) 6975 #define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ 6976 #define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk 6977 6978 /******************* Bits definition for FLASH_OPTR register ***************/ 6979 #define FLASH_OPTR_RDP_Pos (0U) 6980 #define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ 6981 #define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk 6982 #define FLASH_OPTR_BOR_LEV_Pos (8U) 6983 #define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */ 6984 #define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk 6985 #define FLASH_OPTR_BOR_LEV_0 (0x0UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000000 */ 6986 #define FLASH_OPTR_BOR_LEV_1 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */ 6987 #define FLASH_OPTR_BOR_LEV_2 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */ 6988 #define FLASH_OPTR_BOR_LEV_3 (0x3UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000300 */ 6989 #define FLASH_OPTR_BOR_LEV_4 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */ 6990 #define FLASH_OPTR_nRST_STOP_Pos (12U) 6991 #define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */ 6992 #define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk 6993 #define FLASH_OPTR_nRST_STDBY_Pos (13U) 6994 #define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */ 6995 #define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk 6996 #define FLASH_OPTR_nRST_SHDW_Pos (14U) 6997 #define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */ 6998 #define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk 6999 #define FLASH_OPTR_IWDG_SW_Pos (16U) 7000 #define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ 7001 #define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk 7002 #define FLASH_OPTR_IWDG_STOP_Pos (17U) 7003 #define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ 7004 #define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk 7005 #define FLASH_OPTR_IWDG_STDBY_Pos (18U) 7006 #define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ 7007 #define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk 7008 #define FLASH_OPTR_WWDG_SW_Pos (19U) 7009 #define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ 7010 #define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk 7011 #define FLASH_OPTR_nBOOT1_Pos (23U) 7012 #define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x00800000 */ 7013 #define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk 7014 #define FLASH_OPTR_SRAM2_PE_Pos (24U) 7015 #define FLASH_OPTR_SRAM2_PE_Msk (0x1UL << FLASH_OPTR_SRAM2_PE_Pos) /*!< 0x01000000 */ 7016 #define FLASH_OPTR_SRAM2_PE FLASH_OPTR_SRAM2_PE_Msk 7017 #define FLASH_OPTR_SRAM2_RST_Pos (25U) 7018 #define FLASH_OPTR_SRAM2_RST_Msk (0x1UL << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */ 7019 #define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk 7020 #define FLASH_OPTR_nSWBOOT0_Pos (26U) 7021 #define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */ 7022 #define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk 7023 #define FLASH_OPTR_nBOOT0_Pos (27U) 7024 #define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */ 7025 #define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk 7026 7027 /****************** Bits definition for FLASH_PCROP1SR register **********/ 7028 #define FLASH_PCROP1SR_PCROP1_STRT_Pos (0U) 7029 #define FLASH_PCROP1SR_PCROP1_STRT_Msk (0x7FFFUL << FLASH_PCROP1SR_PCROP1_STRT_Pos) /*!< 0x00007FFF */ 7030 #define FLASH_PCROP1SR_PCROP1_STRT FLASH_PCROP1SR_PCROP1_STRT_Msk 7031 7032 /****************** Bits definition for FLASH_PCROP1ER register ***********/ 7033 #define FLASH_PCROP1ER_PCROP1_END_Pos (0U) 7034 #define FLASH_PCROP1ER_PCROP1_END_Msk (0x7FFFUL << FLASH_PCROP1ER_PCROP1_END_Pos) /*!< 0x00007FFF */ 7035 #define FLASH_PCROP1ER_PCROP1_END FLASH_PCROP1ER_PCROP1_END_Msk 7036 #define FLASH_PCROP1ER_PCROP_RDP_Pos (31U) 7037 #define FLASH_PCROP1ER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1ER_PCROP_RDP_Pos) /*!< 0x80000000 */ 7038 #define FLASH_PCROP1ER_PCROP_RDP FLASH_PCROP1ER_PCROP_RDP_Msk 7039 7040 /****************** Bits definition for FLASH_WRP1AR register ***************/ 7041 #define FLASH_WRP1AR_WRP1A_STRT_Pos (0U) 7042 #define FLASH_WRP1AR_WRP1A_STRT_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x0000007F */ 7043 #define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk 7044 #define FLASH_WRP1AR_WRP1A_END_Pos (16U) 7045 #define FLASH_WRP1AR_WRP1A_END_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x007F0000 */ 7046 #define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk 7047 7048 /****************** Bits definition for FLASH_WRPB1R register ***************/ 7049 #define FLASH_WRP1BR_WRP1B_STRT_Pos (0U) 7050 #define FLASH_WRP1BR_WRP1B_STRT_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x0000007F */ 7051 #define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk 7052 #define FLASH_WRP1BR_WRP1B_END_Pos (16U) 7053 #define FLASH_WRP1BR_WRP1B_END_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x007F0000 */ 7054 #define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk 7055 7056 7057 7058 7059 /******************************************************************************/ 7060 /* */ 7061 /* General Purpose IOs (GPIO) */ 7062 /* */ 7063 /******************************************************************************/ 7064 /****************** Bits definition for GPIO_MODER register *****************/ 7065 #define GPIO_MODER_MODE0_Pos (0U) 7066 #define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ 7067 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk 7068 #define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ 7069 #define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ 7070 #define GPIO_MODER_MODE1_Pos (2U) 7071 #define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ 7072 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk 7073 #define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ 7074 #define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ 7075 #define GPIO_MODER_MODE2_Pos (4U) 7076 #define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ 7077 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk 7078 #define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ 7079 #define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ 7080 #define GPIO_MODER_MODE3_Pos (6U) 7081 #define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ 7082 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk 7083 #define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ 7084 #define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ 7085 #define GPIO_MODER_MODE4_Pos (8U) 7086 #define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ 7087 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk 7088 #define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ 7089 #define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ 7090 #define GPIO_MODER_MODE5_Pos (10U) 7091 #define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ 7092 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk 7093 #define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ 7094 #define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ 7095 #define GPIO_MODER_MODE6_Pos (12U) 7096 #define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ 7097 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk 7098 #define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ 7099 #define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ 7100 #define GPIO_MODER_MODE7_Pos (14U) 7101 #define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ 7102 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk 7103 #define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ 7104 #define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ 7105 #define GPIO_MODER_MODE8_Pos (16U) 7106 #define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ 7107 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk 7108 #define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ 7109 #define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ 7110 #define GPIO_MODER_MODE9_Pos (18U) 7111 #define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ 7112 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk 7113 #define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ 7114 #define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ 7115 #define GPIO_MODER_MODE10_Pos (20U) 7116 #define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ 7117 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk 7118 #define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ 7119 #define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ 7120 #define GPIO_MODER_MODE11_Pos (22U) 7121 #define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ 7122 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk 7123 #define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ 7124 #define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ 7125 #define GPIO_MODER_MODE12_Pos (24U) 7126 #define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ 7127 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk 7128 #define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ 7129 #define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ 7130 #define GPIO_MODER_MODE13_Pos (26U) 7131 #define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ 7132 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk 7133 #define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ 7134 #define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ 7135 #define GPIO_MODER_MODE14_Pos (28U) 7136 #define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ 7137 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk 7138 #define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ 7139 #define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ 7140 #define GPIO_MODER_MODE15_Pos (30U) 7141 #define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ 7142 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk 7143 #define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ 7144 #define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ 7145 7146 /* Legacy defines */ 7147 #define GPIO_MODER_MODER0 GPIO_MODER_MODE0 7148 #define GPIO_MODER_MODER0_0 GPIO_MODER_MODE0_0 7149 #define GPIO_MODER_MODER0_1 GPIO_MODER_MODE0_1 7150 #define GPIO_MODER_MODER1 GPIO_MODER_MODE1 7151 #define GPIO_MODER_MODER1_0 GPIO_MODER_MODE1_0 7152 #define GPIO_MODER_MODER1_1 GPIO_MODER_MODE1_1 7153 #define GPIO_MODER_MODER2 GPIO_MODER_MODE2 7154 #define GPIO_MODER_MODER2_0 GPIO_MODER_MODE2_0 7155 #define GPIO_MODER_MODER2_1 GPIO_MODER_MODE2_1 7156 #define GPIO_MODER_MODER3 GPIO_MODER_MODE3 7157 #define GPIO_MODER_MODER3_0 GPIO_MODER_MODE3_0 7158 #define GPIO_MODER_MODER3_1 GPIO_MODER_MODE3_1 7159 #define GPIO_MODER_MODER4 GPIO_MODER_MODE4 7160 #define GPIO_MODER_MODER4_0 GPIO_MODER_MODE4_0 7161 #define GPIO_MODER_MODER4_1 GPIO_MODER_MODE4_1 7162 #define GPIO_MODER_MODER5 GPIO_MODER_MODE5 7163 #define GPIO_MODER_MODER5_0 GPIO_MODER_MODE5_0 7164 #define GPIO_MODER_MODER5_1 GPIO_MODER_MODE5_1 7165 #define GPIO_MODER_MODER6 GPIO_MODER_MODE6 7166 #define GPIO_MODER_MODER6_0 GPIO_MODER_MODE6_0 7167 #define GPIO_MODER_MODER6_1 GPIO_MODER_MODE6_1 7168 #define GPIO_MODER_MODER7 GPIO_MODER_MODE7 7169 #define GPIO_MODER_MODER7_0 GPIO_MODER_MODE7_0 7170 #define GPIO_MODER_MODER7_1 GPIO_MODER_MODE7_1 7171 #define GPIO_MODER_MODER8 GPIO_MODER_MODE8 7172 #define GPIO_MODER_MODER8_0 GPIO_MODER_MODE8_0 7173 #define GPIO_MODER_MODER8_1 GPIO_MODER_MODE8_1 7174 #define GPIO_MODER_MODER9 GPIO_MODER_MODE9 7175 #define GPIO_MODER_MODER9_0 GPIO_MODER_MODE9_0 7176 #define GPIO_MODER_MODER9_1 GPIO_MODER_MODE9_1 7177 #define GPIO_MODER_MODER10 GPIO_MODER_MODE10 7178 #define GPIO_MODER_MODER10_0 GPIO_MODER_MODE10_0 7179 #define GPIO_MODER_MODER10_1 GPIO_MODER_MODE10_1 7180 #define GPIO_MODER_MODER11 GPIO_MODER_MODE11 7181 #define GPIO_MODER_MODER11_0 GPIO_MODER_MODE11_0 7182 #define GPIO_MODER_MODER11_1 GPIO_MODER_MODE11_1 7183 #define GPIO_MODER_MODER12 GPIO_MODER_MODE12 7184 #define GPIO_MODER_MODER12_0 GPIO_MODER_MODE12_0 7185 #define GPIO_MODER_MODER12_1 GPIO_MODER_MODE12_1 7186 #define GPIO_MODER_MODER13 GPIO_MODER_MODE13 7187 #define GPIO_MODER_MODER13_0 GPIO_MODER_MODE13_0 7188 #define GPIO_MODER_MODER13_1 GPIO_MODER_MODE13_1 7189 #define GPIO_MODER_MODER14 GPIO_MODER_MODE14 7190 #define GPIO_MODER_MODER14_0 GPIO_MODER_MODE14_0 7191 #define GPIO_MODER_MODER14_1 GPIO_MODER_MODE14_1 7192 #define GPIO_MODER_MODER15 GPIO_MODER_MODE15 7193 #define GPIO_MODER_MODER15_0 GPIO_MODER_MODE15_0 7194 #define GPIO_MODER_MODER15_1 GPIO_MODER_MODE15_1 7195 7196 /****************** Bits definition for GPIO_OTYPER register ****************/ 7197 #define GPIO_OTYPER_OT0_Pos (0U) 7198 #define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ 7199 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk 7200 #define GPIO_OTYPER_OT1_Pos (1U) 7201 #define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ 7202 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk 7203 #define GPIO_OTYPER_OT2_Pos (2U) 7204 #define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ 7205 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk 7206 #define GPIO_OTYPER_OT3_Pos (3U) 7207 #define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ 7208 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk 7209 #define GPIO_OTYPER_OT4_Pos (4U) 7210 #define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ 7211 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk 7212 #define GPIO_OTYPER_OT5_Pos (5U) 7213 #define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ 7214 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk 7215 #define GPIO_OTYPER_OT6_Pos (6U) 7216 #define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ 7217 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk 7218 #define GPIO_OTYPER_OT7_Pos (7U) 7219 #define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ 7220 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk 7221 #define GPIO_OTYPER_OT8_Pos (8U) 7222 #define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ 7223 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk 7224 #define GPIO_OTYPER_OT9_Pos (9U) 7225 #define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ 7226 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk 7227 #define GPIO_OTYPER_OT10_Pos (10U) 7228 #define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ 7229 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk 7230 #define GPIO_OTYPER_OT11_Pos (11U) 7231 #define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ 7232 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk 7233 #define GPIO_OTYPER_OT12_Pos (12U) 7234 #define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ 7235 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk 7236 #define GPIO_OTYPER_OT13_Pos (13U) 7237 #define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ 7238 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk 7239 #define GPIO_OTYPER_OT14_Pos (14U) 7240 #define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ 7241 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk 7242 #define GPIO_OTYPER_OT15_Pos (15U) 7243 #define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ 7244 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk 7245 7246 /* Legacy defines */ 7247 #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0 7248 #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1 7249 #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2 7250 #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3 7251 #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4 7252 #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5 7253 #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6 7254 #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7 7255 #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8 7256 #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9 7257 #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10 7258 #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11 7259 #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12 7260 #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13 7261 #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14 7262 #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15 7263 7264 /****************** Bits definition for GPIO_OSPEEDR register ***************/ 7265 #define GPIO_OSPEEDR_OSPEED0_Pos (0U) 7266 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ 7267 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk 7268 #define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ 7269 #define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ 7270 #define GPIO_OSPEEDR_OSPEED1_Pos (2U) 7271 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ 7272 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk 7273 #define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ 7274 #define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ 7275 #define GPIO_OSPEEDR_OSPEED2_Pos (4U) 7276 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ 7277 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk 7278 #define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ 7279 #define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ 7280 #define GPIO_OSPEEDR_OSPEED3_Pos (6U) 7281 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ 7282 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk 7283 #define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ 7284 #define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ 7285 #define GPIO_OSPEEDR_OSPEED4_Pos (8U) 7286 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ 7287 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk 7288 #define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ 7289 #define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ 7290 #define GPIO_OSPEEDR_OSPEED5_Pos (10U) 7291 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ 7292 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk 7293 #define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ 7294 #define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ 7295 #define GPIO_OSPEEDR_OSPEED6_Pos (12U) 7296 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ 7297 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk 7298 #define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ 7299 #define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ 7300 #define GPIO_OSPEEDR_OSPEED7_Pos (14U) 7301 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ 7302 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk 7303 #define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ 7304 #define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ 7305 #define GPIO_OSPEEDR_OSPEED8_Pos (16U) 7306 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ 7307 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk 7308 #define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ 7309 #define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ 7310 #define GPIO_OSPEEDR_OSPEED9_Pos (18U) 7311 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ 7312 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk 7313 #define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ 7314 #define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ 7315 #define GPIO_OSPEEDR_OSPEED10_Pos (20U) 7316 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ 7317 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk 7318 #define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ 7319 #define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ 7320 #define GPIO_OSPEEDR_OSPEED11_Pos (22U) 7321 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ 7322 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk 7323 #define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ 7324 #define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ 7325 #define GPIO_OSPEEDR_OSPEED12_Pos (24U) 7326 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ 7327 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk 7328 #define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ 7329 #define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ 7330 #define GPIO_OSPEEDR_OSPEED13_Pos (26U) 7331 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ 7332 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk 7333 #define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ 7334 #define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ 7335 #define GPIO_OSPEEDR_OSPEED14_Pos (28U) 7336 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ 7337 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk 7338 #define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ 7339 #define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ 7340 #define GPIO_OSPEEDR_OSPEED15_Pos (30U) 7341 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ 7342 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk 7343 #define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ 7344 #define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ 7345 7346 /* Legacy defines */ 7347 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0 7348 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0 7349 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1 7350 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1 7351 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0 7352 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1 7353 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2 7354 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0 7355 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1 7356 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3 7357 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0 7358 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1 7359 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4 7360 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0 7361 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1 7362 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5 7363 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0 7364 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1 7365 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6 7366 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0 7367 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1 7368 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7 7369 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0 7370 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1 7371 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8 7372 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0 7373 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1 7374 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9 7375 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0 7376 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1 7377 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10 7378 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0 7379 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1 7380 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11 7381 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0 7382 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1 7383 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12 7384 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0 7385 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1 7386 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13 7387 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0 7388 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1 7389 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14 7390 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0 7391 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1 7392 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15 7393 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0 7394 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1 7395 7396 /****************** Bits definition for GPIO_PUPDR register *****************/ 7397 #define GPIO_PUPDR_PUPD0_Pos (0U) 7398 #define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ 7399 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk 7400 #define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ 7401 #define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ 7402 #define GPIO_PUPDR_PUPD1_Pos (2U) 7403 #define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ 7404 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk 7405 #define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ 7406 #define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ 7407 #define GPIO_PUPDR_PUPD2_Pos (4U) 7408 #define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ 7409 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk 7410 #define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ 7411 #define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ 7412 #define GPIO_PUPDR_PUPD3_Pos (6U) 7413 #define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ 7414 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk 7415 #define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ 7416 #define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ 7417 #define GPIO_PUPDR_PUPD4_Pos (8U) 7418 #define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ 7419 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk 7420 #define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ 7421 #define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ 7422 #define GPIO_PUPDR_PUPD5_Pos (10U) 7423 #define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ 7424 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk 7425 #define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ 7426 #define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ 7427 #define GPIO_PUPDR_PUPD6_Pos (12U) 7428 #define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ 7429 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk 7430 #define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ 7431 #define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ 7432 #define GPIO_PUPDR_PUPD7_Pos (14U) 7433 #define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ 7434 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk 7435 #define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ 7436 #define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ 7437 #define GPIO_PUPDR_PUPD8_Pos (16U) 7438 #define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ 7439 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk 7440 #define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ 7441 #define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ 7442 #define GPIO_PUPDR_PUPD9_Pos (18U) 7443 #define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ 7444 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk 7445 #define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ 7446 #define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ 7447 #define GPIO_PUPDR_PUPD10_Pos (20U) 7448 #define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ 7449 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk 7450 #define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ 7451 #define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ 7452 #define GPIO_PUPDR_PUPD11_Pos (22U) 7453 #define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ 7454 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk 7455 #define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ 7456 #define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ 7457 #define GPIO_PUPDR_PUPD12_Pos (24U) 7458 #define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ 7459 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk 7460 #define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ 7461 #define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ 7462 #define GPIO_PUPDR_PUPD13_Pos (26U) 7463 #define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ 7464 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk 7465 #define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ 7466 #define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ 7467 #define GPIO_PUPDR_PUPD14_Pos (28U) 7468 #define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ 7469 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk 7470 #define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ 7471 #define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ 7472 #define GPIO_PUPDR_PUPD15_Pos (30U) 7473 #define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ 7474 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk 7475 #define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ 7476 #define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ 7477 7478 /* Legacy defines */ 7479 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0 7480 #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0 7481 #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1 7482 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1 7483 #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0 7484 #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1 7485 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2 7486 #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0 7487 #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1 7488 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3 7489 #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0 7490 #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1 7491 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4 7492 #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0 7493 #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1 7494 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5 7495 #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0 7496 #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1 7497 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6 7498 #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0 7499 #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1 7500 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7 7501 #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0 7502 #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1 7503 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8 7504 #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0 7505 #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1 7506 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9 7507 #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0 7508 #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1 7509 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10 7510 #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0 7511 #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1 7512 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11 7513 #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0 7514 #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1 7515 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12 7516 #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0 7517 #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1 7518 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13 7519 #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0 7520 #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1 7521 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14 7522 #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0 7523 #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1 7524 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15 7525 #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0 7526 #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1 7527 7528 /****************** Bits definition for GPIO_IDR register *******************/ 7529 #define GPIO_IDR_ID0_Pos (0U) 7530 #define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ 7531 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk 7532 #define GPIO_IDR_ID1_Pos (1U) 7533 #define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ 7534 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk 7535 #define GPIO_IDR_ID2_Pos (2U) 7536 #define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ 7537 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk 7538 #define GPIO_IDR_ID3_Pos (3U) 7539 #define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ 7540 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk 7541 #define GPIO_IDR_ID4_Pos (4U) 7542 #define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ 7543 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk 7544 #define GPIO_IDR_ID5_Pos (5U) 7545 #define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ 7546 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk 7547 #define GPIO_IDR_ID6_Pos (6U) 7548 #define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ 7549 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk 7550 #define GPIO_IDR_ID7_Pos (7U) 7551 #define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ 7552 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk 7553 #define GPIO_IDR_ID8_Pos (8U) 7554 #define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ 7555 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk 7556 #define GPIO_IDR_ID9_Pos (9U) 7557 #define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ 7558 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk 7559 #define GPIO_IDR_ID10_Pos (10U) 7560 #define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ 7561 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk 7562 #define GPIO_IDR_ID11_Pos (11U) 7563 #define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ 7564 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk 7565 #define GPIO_IDR_ID12_Pos (12U) 7566 #define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ 7567 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk 7568 #define GPIO_IDR_ID13_Pos (13U) 7569 #define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ 7570 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk 7571 #define GPIO_IDR_ID14_Pos (14U) 7572 #define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ 7573 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk 7574 #define GPIO_IDR_ID15_Pos (15U) 7575 #define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ 7576 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk 7577 7578 /* Legacy defines */ 7579 #define GPIO_IDR_IDR_0 GPIO_IDR_ID0 7580 #define GPIO_IDR_IDR_1 GPIO_IDR_ID1 7581 #define GPIO_IDR_IDR_2 GPIO_IDR_ID2 7582 #define GPIO_IDR_IDR_3 GPIO_IDR_ID3 7583 #define GPIO_IDR_IDR_4 GPIO_IDR_ID4 7584 #define GPIO_IDR_IDR_5 GPIO_IDR_ID5 7585 #define GPIO_IDR_IDR_6 GPIO_IDR_ID6 7586 #define GPIO_IDR_IDR_7 GPIO_IDR_ID7 7587 #define GPIO_IDR_IDR_8 GPIO_IDR_ID8 7588 #define GPIO_IDR_IDR_9 GPIO_IDR_ID9 7589 #define GPIO_IDR_IDR_10 GPIO_IDR_ID10 7590 #define GPIO_IDR_IDR_11 GPIO_IDR_ID11 7591 #define GPIO_IDR_IDR_12 GPIO_IDR_ID12 7592 #define GPIO_IDR_IDR_13 GPIO_IDR_ID13 7593 #define GPIO_IDR_IDR_14 GPIO_IDR_ID14 7594 #define GPIO_IDR_IDR_15 GPIO_IDR_ID15 7595 7596 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */ 7597 #define GPIO_OTYPER_IDR_0 GPIO_IDR_ID0 7598 #define GPIO_OTYPER_IDR_1 GPIO_IDR_ID1 7599 #define GPIO_OTYPER_IDR_2 GPIO_IDR_ID2 7600 #define GPIO_OTYPER_IDR_3 GPIO_IDR_ID3 7601 #define GPIO_OTYPER_IDR_4 GPIO_IDR_ID4 7602 #define GPIO_OTYPER_IDR_5 GPIO_IDR_ID5 7603 #define GPIO_OTYPER_IDR_6 GPIO_IDR_ID6 7604 #define GPIO_OTYPER_IDR_7 GPIO_IDR_ID7 7605 #define GPIO_OTYPER_IDR_8 GPIO_IDR_ID8 7606 #define GPIO_OTYPER_IDR_9 GPIO_IDR_ID9 7607 #define GPIO_OTYPER_IDR_10 GPIO_IDR_ID10 7608 #define GPIO_OTYPER_IDR_11 GPIO_IDR_ID11 7609 #define GPIO_OTYPER_IDR_12 GPIO_IDR_ID12 7610 #define GPIO_OTYPER_IDR_13 GPIO_IDR_ID13 7611 #define GPIO_OTYPER_IDR_14 GPIO_IDR_ID14 7612 #define GPIO_OTYPER_IDR_15 GPIO_IDR_ID15 7613 7614 /****************** Bits definition for GPIO_ODR register *******************/ 7615 #define GPIO_ODR_OD0_Pos (0U) 7616 #define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ 7617 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk 7618 #define GPIO_ODR_OD1_Pos (1U) 7619 #define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ 7620 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk 7621 #define GPIO_ODR_OD2_Pos (2U) 7622 #define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ 7623 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk 7624 #define GPIO_ODR_OD3_Pos (3U) 7625 #define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ 7626 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk 7627 #define GPIO_ODR_OD4_Pos (4U) 7628 #define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ 7629 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk 7630 #define GPIO_ODR_OD5_Pos (5U) 7631 #define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ 7632 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk 7633 #define GPIO_ODR_OD6_Pos (6U) 7634 #define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ 7635 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk 7636 #define GPIO_ODR_OD7_Pos (7U) 7637 #define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ 7638 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk 7639 #define GPIO_ODR_OD8_Pos (8U) 7640 #define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ 7641 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk 7642 #define GPIO_ODR_OD9_Pos (9U) 7643 #define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ 7644 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk 7645 #define GPIO_ODR_OD10_Pos (10U) 7646 #define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ 7647 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk 7648 #define GPIO_ODR_OD11_Pos (11U) 7649 #define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ 7650 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk 7651 #define GPIO_ODR_OD12_Pos (12U) 7652 #define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ 7653 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk 7654 #define GPIO_ODR_OD13_Pos (13U) 7655 #define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ 7656 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk 7657 #define GPIO_ODR_OD14_Pos (14U) 7658 #define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ 7659 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk 7660 #define GPIO_ODR_OD15_Pos (15U) 7661 #define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ 7662 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk 7663 7664 /* Legacy defines */ 7665 #define GPIO_ODR_ODR_0 GPIO_ODR_OD0 7666 #define GPIO_ODR_ODR_1 GPIO_ODR_OD1 7667 #define GPIO_ODR_ODR_2 GPIO_ODR_OD2 7668 #define GPIO_ODR_ODR_3 GPIO_ODR_OD3 7669 #define GPIO_ODR_ODR_4 GPIO_ODR_OD4 7670 #define GPIO_ODR_ODR_5 GPIO_ODR_OD5 7671 #define GPIO_ODR_ODR_6 GPIO_ODR_OD6 7672 #define GPIO_ODR_ODR_7 GPIO_ODR_OD7 7673 #define GPIO_ODR_ODR_8 GPIO_ODR_OD8 7674 #define GPIO_ODR_ODR_9 GPIO_ODR_OD9 7675 #define GPIO_ODR_ODR_10 GPIO_ODR_OD10 7676 #define GPIO_ODR_ODR_11 GPIO_ODR_OD11 7677 #define GPIO_ODR_ODR_12 GPIO_ODR_OD12 7678 #define GPIO_ODR_ODR_13 GPIO_ODR_OD13 7679 #define GPIO_ODR_ODR_14 GPIO_ODR_OD14 7680 #define GPIO_ODR_ODR_15 GPIO_ODR_OD15 7681 7682 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */ 7683 #define GPIO_OTYPER_ODR_0 GPIO_ODR_OD0 7684 #define GPIO_OTYPER_ODR_1 GPIO_ODR_OD1 7685 #define GPIO_OTYPER_ODR_2 GPIO_ODR_OD2 7686 #define GPIO_OTYPER_ODR_3 GPIO_ODR_OD3 7687 #define GPIO_OTYPER_ODR_4 GPIO_ODR_OD4 7688 #define GPIO_OTYPER_ODR_5 GPIO_ODR_OD5 7689 #define GPIO_OTYPER_ODR_6 GPIO_ODR_OD6 7690 #define GPIO_OTYPER_ODR_7 GPIO_ODR_OD7 7691 #define GPIO_OTYPER_ODR_8 GPIO_ODR_OD8 7692 #define GPIO_OTYPER_ODR_9 GPIO_ODR_OD9 7693 #define GPIO_OTYPER_ODR_10 GPIO_ODR_OD10 7694 #define GPIO_OTYPER_ODR_11 GPIO_ODR_OD11 7695 #define GPIO_OTYPER_ODR_12 GPIO_ODR_OD12 7696 #define GPIO_OTYPER_ODR_13 GPIO_ODR_OD13 7697 #define GPIO_OTYPER_ODR_14 GPIO_ODR_OD14 7698 #define GPIO_OTYPER_ODR_15 GPIO_ODR_OD15 7699 7700 /****************** Bits definition for GPIO_BSRR register ******************/ 7701 #define GPIO_BSRR_BS0_Pos (0U) 7702 #define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ 7703 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk 7704 #define GPIO_BSRR_BS1_Pos (1U) 7705 #define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ 7706 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk 7707 #define GPIO_BSRR_BS2_Pos (2U) 7708 #define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ 7709 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk 7710 #define GPIO_BSRR_BS3_Pos (3U) 7711 #define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ 7712 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk 7713 #define GPIO_BSRR_BS4_Pos (4U) 7714 #define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ 7715 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk 7716 #define GPIO_BSRR_BS5_Pos (5U) 7717 #define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ 7718 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk 7719 #define GPIO_BSRR_BS6_Pos (6U) 7720 #define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ 7721 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk 7722 #define GPIO_BSRR_BS7_Pos (7U) 7723 #define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ 7724 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk 7725 #define GPIO_BSRR_BS8_Pos (8U) 7726 #define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ 7727 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk 7728 #define GPIO_BSRR_BS9_Pos (9U) 7729 #define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ 7730 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk 7731 #define GPIO_BSRR_BS10_Pos (10U) 7732 #define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ 7733 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk 7734 #define GPIO_BSRR_BS11_Pos (11U) 7735 #define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ 7736 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk 7737 #define GPIO_BSRR_BS12_Pos (12U) 7738 #define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ 7739 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk 7740 #define GPIO_BSRR_BS13_Pos (13U) 7741 #define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ 7742 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk 7743 #define GPIO_BSRR_BS14_Pos (14U) 7744 #define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ 7745 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk 7746 #define GPIO_BSRR_BS15_Pos (15U) 7747 #define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ 7748 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk 7749 #define GPIO_BSRR_BR0_Pos (16U) 7750 #define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ 7751 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk 7752 #define GPIO_BSRR_BR1_Pos (17U) 7753 #define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ 7754 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk 7755 #define GPIO_BSRR_BR2_Pos (18U) 7756 #define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ 7757 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk 7758 #define GPIO_BSRR_BR3_Pos (19U) 7759 #define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ 7760 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk 7761 #define GPIO_BSRR_BR4_Pos (20U) 7762 #define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ 7763 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk 7764 #define GPIO_BSRR_BR5_Pos (21U) 7765 #define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ 7766 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk 7767 #define GPIO_BSRR_BR6_Pos (22U) 7768 #define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ 7769 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk 7770 #define GPIO_BSRR_BR7_Pos (23U) 7771 #define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ 7772 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk 7773 #define GPIO_BSRR_BR8_Pos (24U) 7774 #define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ 7775 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk 7776 #define GPIO_BSRR_BR9_Pos (25U) 7777 #define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ 7778 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk 7779 #define GPIO_BSRR_BR10_Pos (26U) 7780 #define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ 7781 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk 7782 #define GPIO_BSRR_BR11_Pos (27U) 7783 #define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ 7784 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk 7785 #define GPIO_BSRR_BR12_Pos (28U) 7786 #define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ 7787 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk 7788 #define GPIO_BSRR_BR13_Pos (29U) 7789 #define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ 7790 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk 7791 #define GPIO_BSRR_BR14_Pos (30U) 7792 #define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ 7793 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk 7794 #define GPIO_BSRR_BR15_Pos (31U) 7795 #define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ 7796 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk 7797 7798 /* Legacy defines */ 7799 #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0 7800 #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1 7801 #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2 7802 #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3 7803 #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4 7804 #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5 7805 #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6 7806 #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7 7807 #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8 7808 #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9 7809 #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10 7810 #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11 7811 #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12 7812 #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13 7813 #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14 7814 #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15 7815 #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0 7816 #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1 7817 #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2 7818 #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3 7819 #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4 7820 #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5 7821 #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6 7822 #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7 7823 #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8 7824 #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9 7825 #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10 7826 #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11 7827 #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12 7828 #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13 7829 #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14 7830 #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15 7831 7832 /****************** Bit definition for GPIO_LCKR register *********************/ 7833 #define GPIO_LCKR_LCK0_Pos (0U) 7834 #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ 7835 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk 7836 #define GPIO_LCKR_LCK1_Pos (1U) 7837 #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ 7838 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk 7839 #define GPIO_LCKR_LCK2_Pos (2U) 7840 #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ 7841 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk 7842 #define GPIO_LCKR_LCK3_Pos (3U) 7843 #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ 7844 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk 7845 #define GPIO_LCKR_LCK4_Pos (4U) 7846 #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ 7847 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk 7848 #define GPIO_LCKR_LCK5_Pos (5U) 7849 #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ 7850 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk 7851 #define GPIO_LCKR_LCK6_Pos (6U) 7852 #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ 7853 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk 7854 #define GPIO_LCKR_LCK7_Pos (7U) 7855 #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ 7856 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk 7857 #define GPIO_LCKR_LCK8_Pos (8U) 7858 #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ 7859 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk 7860 #define GPIO_LCKR_LCK9_Pos (9U) 7861 #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ 7862 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk 7863 #define GPIO_LCKR_LCK10_Pos (10U) 7864 #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ 7865 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk 7866 #define GPIO_LCKR_LCK11_Pos (11U) 7867 #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ 7868 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk 7869 #define GPIO_LCKR_LCK12_Pos (12U) 7870 #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ 7871 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk 7872 #define GPIO_LCKR_LCK13_Pos (13U) 7873 #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ 7874 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk 7875 #define GPIO_LCKR_LCK14_Pos (14U) 7876 #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ 7877 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk 7878 #define GPIO_LCKR_LCK15_Pos (15U) 7879 #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ 7880 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk 7881 #define GPIO_LCKR_LCKK_Pos (16U) 7882 #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ 7883 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk 7884 7885 /****************** Bit definition for GPIO_AFRL register *********************/ 7886 #define GPIO_AFRL_AFSEL0_Pos (0U) 7887 #define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ 7888 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk 7889 #define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ 7890 #define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ 7891 #define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ 7892 #define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ 7893 #define GPIO_AFRL_AFSEL1_Pos (4U) 7894 #define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ 7895 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk 7896 #define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ 7897 #define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ 7898 #define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ 7899 #define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ 7900 #define GPIO_AFRL_AFSEL2_Pos (8U) 7901 #define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ 7902 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk 7903 #define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ 7904 #define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ 7905 #define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ 7906 #define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ 7907 #define GPIO_AFRL_AFSEL3_Pos (12U) 7908 #define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ 7909 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk 7910 #define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ 7911 #define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ 7912 #define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ 7913 #define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ 7914 #define GPIO_AFRL_AFSEL4_Pos (16U) 7915 #define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ 7916 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk 7917 #define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ 7918 #define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ 7919 #define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ 7920 #define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ 7921 #define GPIO_AFRL_AFSEL5_Pos (20U) 7922 #define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ 7923 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk 7924 #define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ 7925 #define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ 7926 #define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ 7927 #define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ 7928 #define GPIO_AFRL_AFSEL6_Pos (24U) 7929 #define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ 7930 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk 7931 #define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ 7932 #define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ 7933 #define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ 7934 #define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ 7935 #define GPIO_AFRL_AFSEL7_Pos (28U) 7936 #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ 7937 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk 7938 #define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ 7939 #define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ 7940 #define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ 7941 #define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ 7942 7943 /* Legacy defines */ 7944 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 7945 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1 7946 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2 7947 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3 7948 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4 7949 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5 7950 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6 7951 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7 7952 7953 /****************** Bit definition for GPIO_AFRH register *********************/ 7954 #define GPIO_AFRH_AFSEL8_Pos (0U) 7955 #define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ 7956 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk 7957 #define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ 7958 #define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ 7959 #define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ 7960 #define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ 7961 #define GPIO_AFRH_AFSEL9_Pos (4U) 7962 #define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ 7963 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk 7964 #define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ 7965 #define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ 7966 #define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ 7967 #define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ 7968 #define GPIO_AFRH_AFSEL10_Pos (8U) 7969 #define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ 7970 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk 7971 #define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ 7972 #define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ 7973 #define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ 7974 #define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ 7975 #define GPIO_AFRH_AFSEL11_Pos (12U) 7976 #define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ 7977 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk 7978 #define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ 7979 #define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ 7980 #define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ 7981 #define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ 7982 #define GPIO_AFRH_AFSEL12_Pos (16U) 7983 #define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ 7984 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk 7985 #define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ 7986 #define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ 7987 #define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ 7988 #define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ 7989 #define GPIO_AFRH_AFSEL13_Pos (20U) 7990 #define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ 7991 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk 7992 #define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ 7993 #define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ 7994 #define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ 7995 #define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ 7996 #define GPIO_AFRH_AFSEL14_Pos (24U) 7997 #define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ 7998 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk 7999 #define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ 8000 #define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ 8001 #define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ 8002 #define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ 8003 #define GPIO_AFRH_AFSEL15_Pos (28U) 8004 #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ 8005 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk 8006 #define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ 8007 #define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ 8008 #define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ 8009 #define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ 8010 8011 /* Legacy defines */ 8012 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8 8013 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9 8014 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10 8015 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11 8016 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12 8017 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13 8018 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14 8019 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15 8020 8021 /****************** Bits definition for GPIO_BRR register ******************/ 8022 #define GPIO_BRR_BR0_Pos (0U) 8023 #define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ 8024 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk 8025 #define GPIO_BRR_BR1_Pos (1U) 8026 #define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ 8027 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk 8028 #define GPIO_BRR_BR2_Pos (2U) 8029 #define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ 8030 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk 8031 #define GPIO_BRR_BR3_Pos (3U) 8032 #define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ 8033 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk 8034 #define GPIO_BRR_BR4_Pos (4U) 8035 #define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ 8036 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk 8037 #define GPIO_BRR_BR5_Pos (5U) 8038 #define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ 8039 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk 8040 #define GPIO_BRR_BR6_Pos (6U) 8041 #define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ 8042 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk 8043 #define GPIO_BRR_BR7_Pos (7U) 8044 #define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ 8045 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk 8046 #define GPIO_BRR_BR8_Pos (8U) 8047 #define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ 8048 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk 8049 #define GPIO_BRR_BR9_Pos (9U) 8050 #define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ 8051 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk 8052 #define GPIO_BRR_BR10_Pos (10U) 8053 #define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ 8054 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk 8055 #define GPIO_BRR_BR11_Pos (11U) 8056 #define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ 8057 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk 8058 #define GPIO_BRR_BR12_Pos (12U) 8059 #define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ 8060 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk 8061 #define GPIO_BRR_BR13_Pos (13U) 8062 #define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ 8063 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk 8064 #define GPIO_BRR_BR14_Pos (14U) 8065 #define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ 8066 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk 8067 #define GPIO_BRR_BR15_Pos (15U) 8068 #define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ 8069 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk 8070 8071 /* Legacy defines */ 8072 #define GPIO_BRR_BR_0 GPIO_BRR_BR0 8073 #define GPIO_BRR_BR_1 GPIO_BRR_BR1 8074 #define GPIO_BRR_BR_2 GPIO_BRR_BR2 8075 #define GPIO_BRR_BR_3 GPIO_BRR_BR3 8076 #define GPIO_BRR_BR_4 GPIO_BRR_BR4 8077 #define GPIO_BRR_BR_5 GPIO_BRR_BR5 8078 #define GPIO_BRR_BR_6 GPIO_BRR_BR6 8079 #define GPIO_BRR_BR_7 GPIO_BRR_BR7 8080 #define GPIO_BRR_BR_8 GPIO_BRR_BR8 8081 #define GPIO_BRR_BR_9 GPIO_BRR_BR9 8082 #define GPIO_BRR_BR_10 GPIO_BRR_BR10 8083 #define GPIO_BRR_BR_11 GPIO_BRR_BR11 8084 #define GPIO_BRR_BR_12 GPIO_BRR_BR12 8085 #define GPIO_BRR_BR_13 GPIO_BRR_BR13 8086 #define GPIO_BRR_BR_14 GPIO_BRR_BR14 8087 #define GPIO_BRR_BR_15 GPIO_BRR_BR15 8088 8089 8090 8091 /******************************************************************************/ 8092 /* */ 8093 /* Inter-integrated Circuit Interface (I2C) */ 8094 /* */ 8095 /******************************************************************************/ 8096 /******************* Bit definition for I2C_CR1 register *******************/ 8097 #define I2C_CR1_PE_Pos (0U) 8098 #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ 8099 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ 8100 #define I2C_CR1_TXIE_Pos (1U) 8101 #define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ 8102 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ 8103 #define I2C_CR1_RXIE_Pos (2U) 8104 #define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ 8105 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ 8106 #define I2C_CR1_ADDRIE_Pos (3U) 8107 #define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ 8108 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ 8109 #define I2C_CR1_NACKIE_Pos (4U) 8110 #define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ 8111 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ 8112 #define I2C_CR1_STOPIE_Pos (5U) 8113 #define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ 8114 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ 8115 #define I2C_CR1_TCIE_Pos (6U) 8116 #define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ 8117 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ 8118 #define I2C_CR1_ERRIE_Pos (7U) 8119 #define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ 8120 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ 8121 #define I2C_CR1_DNF_Pos (8U) 8122 #define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ 8123 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ 8124 #define I2C_CR1_ANFOFF_Pos (12U) 8125 #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ 8126 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ 8127 #define I2C_CR1_SWRST_Pos (13U) 8128 #define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ 8129 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ 8130 #define I2C_CR1_TXDMAEN_Pos (14U) 8131 #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ 8132 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ 8133 #define I2C_CR1_RXDMAEN_Pos (15U) 8134 #define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ 8135 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ 8136 #define I2C_CR1_SBC_Pos (16U) 8137 #define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ 8138 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ 8139 #define I2C_CR1_NOSTRETCH_Pos (17U) 8140 #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ 8141 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ 8142 #define I2C_CR1_WUPEN_Pos (18U) 8143 #define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ 8144 #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ 8145 #define I2C_CR1_GCEN_Pos (19U) 8146 #define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ 8147 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ 8148 #define I2C_CR1_SMBHEN_Pos (20U) 8149 #define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ 8150 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ 8151 #define I2C_CR1_SMBDEN_Pos (21U) 8152 #define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ 8153 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ 8154 #define I2C_CR1_ALERTEN_Pos (22U) 8155 #define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ 8156 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ 8157 #define I2C_CR1_PECEN_Pos (23U) 8158 #define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ 8159 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ 8160 8161 /****************** Bit definition for I2C_CR2 register ********************/ 8162 #define I2C_CR2_SADD_Pos (0U) 8163 #define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ 8164 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ 8165 #define I2C_CR2_RD_WRN_Pos (10U) 8166 #define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ 8167 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ 8168 #define I2C_CR2_ADD10_Pos (11U) 8169 #define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ 8170 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ 8171 #define I2C_CR2_HEAD10R_Pos (12U) 8172 #define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ 8173 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ 8174 #define I2C_CR2_START_Pos (13U) 8175 #define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ 8176 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ 8177 #define I2C_CR2_STOP_Pos (14U) 8178 #define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ 8179 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ 8180 #define I2C_CR2_NACK_Pos (15U) 8181 #define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ 8182 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ 8183 #define I2C_CR2_NBYTES_Pos (16U) 8184 #define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ 8185 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ 8186 #define I2C_CR2_RELOAD_Pos (24U) 8187 #define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ 8188 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ 8189 #define I2C_CR2_AUTOEND_Pos (25U) 8190 #define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ 8191 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ 8192 #define I2C_CR2_PECBYTE_Pos (26U) 8193 #define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ 8194 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ 8195 8196 /******************* Bit definition for I2C_OAR1 register ******************/ 8197 #define I2C_OAR1_OA1_Pos (0U) 8198 #define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ 8199 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ 8200 #define I2C_OAR1_OA1MODE_Pos (10U) 8201 #define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ 8202 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ 8203 #define I2C_OAR1_OA1EN_Pos (15U) 8204 #define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ 8205 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ 8206 8207 /******************* Bit definition for I2C_OAR2 register ******************/ 8208 #define I2C_OAR2_OA2_Pos (1U) 8209 #define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ 8210 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ 8211 #define I2C_OAR2_OA2MSK_Pos (8U) 8212 #define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ 8213 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ 8214 #define I2C_OAR2_OA2NOMASK (0x00000000UL) /*!< No mask */ 8215 #define I2C_OAR2_OA2MASK01_Pos (8U) 8216 #define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ 8217 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ 8218 #define I2C_OAR2_OA2MASK02_Pos (9U) 8219 #define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ 8220 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ 8221 #define I2C_OAR2_OA2MASK03_Pos (8U) 8222 #define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ 8223 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ 8224 #define I2C_OAR2_OA2MASK04_Pos (10U) 8225 #define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ 8226 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ 8227 #define I2C_OAR2_OA2MASK05_Pos (8U) 8228 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ 8229 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ 8230 #define I2C_OAR2_OA2MASK06_Pos (9U) 8231 #define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ 8232 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ 8233 #define I2C_OAR2_OA2MASK07_Pos (8U) 8234 #define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ 8235 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ 8236 #define I2C_OAR2_OA2EN_Pos (15U) 8237 #define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ 8238 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ 8239 8240 /******************* Bit definition for I2C_TIMINGR register *******************/ 8241 #define I2C_TIMINGR_SCLL_Pos (0U) 8242 #define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ 8243 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ 8244 #define I2C_TIMINGR_SCLH_Pos (8U) 8245 #define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ 8246 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ 8247 #define I2C_TIMINGR_SDADEL_Pos (16U) 8248 #define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ 8249 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ 8250 #define I2C_TIMINGR_SCLDEL_Pos (20U) 8251 #define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ 8252 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ 8253 #define I2C_TIMINGR_PRESC_Pos (28U) 8254 #define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ 8255 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ 8256 8257 /******************* Bit definition for I2C_TIMEOUTR register *******************/ 8258 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) 8259 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ 8260 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ 8261 #define I2C_TIMEOUTR_TIDLE_Pos (12U) 8262 #define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ 8263 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ 8264 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) 8265 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ 8266 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ 8267 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) 8268 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ 8269 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */ 8270 #define I2C_TIMEOUTR_TEXTEN_Pos (31U) 8271 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ 8272 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ 8273 8274 /****************** Bit definition for I2C_ISR register *********************/ 8275 #define I2C_ISR_TXE_Pos (0U) 8276 #define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ 8277 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ 8278 #define I2C_ISR_TXIS_Pos (1U) 8279 #define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ 8280 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ 8281 #define I2C_ISR_RXNE_Pos (2U) 8282 #define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ 8283 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ 8284 #define I2C_ISR_ADDR_Pos (3U) 8285 #define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ 8286 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */ 8287 #define I2C_ISR_NACKF_Pos (4U) 8288 #define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ 8289 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ 8290 #define I2C_ISR_STOPF_Pos (5U) 8291 #define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ 8292 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ 8293 #define I2C_ISR_TC_Pos (6U) 8294 #define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */ 8295 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ 8296 #define I2C_ISR_TCR_Pos (7U) 8297 #define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ 8298 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ 8299 #define I2C_ISR_BERR_Pos (8U) 8300 #define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ 8301 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ 8302 #define I2C_ISR_ARLO_Pos (9U) 8303 #define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ 8304 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ 8305 #define I2C_ISR_OVR_Pos (10U) 8306 #define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ 8307 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ 8308 #define I2C_ISR_PECERR_Pos (11U) 8309 #define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ 8310 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ 8311 #define I2C_ISR_TIMEOUT_Pos (12U) 8312 #define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ 8313 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ 8314 #define I2C_ISR_ALERT_Pos (13U) 8315 #define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ 8316 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ 8317 #define I2C_ISR_BUSY_Pos (15U) 8318 #define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ 8319 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ 8320 #define I2C_ISR_DIR_Pos (16U) 8321 #define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ 8322 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ 8323 #define I2C_ISR_ADDCODE_Pos (17U) 8324 #define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ 8325 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ 8326 8327 /****************** Bit definition for I2C_ICR register *********************/ 8328 #define I2C_ICR_ADDRCF_Pos (3U) 8329 #define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ 8330 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ 8331 #define I2C_ICR_NACKCF_Pos (4U) 8332 #define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ 8333 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ 8334 #define I2C_ICR_STOPCF_Pos (5U) 8335 #define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ 8336 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ 8337 #define I2C_ICR_BERRCF_Pos (8U) 8338 #define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ 8339 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ 8340 #define I2C_ICR_ARLOCF_Pos (9U) 8341 #define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ 8342 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ 8343 #define I2C_ICR_OVRCF_Pos (10U) 8344 #define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ 8345 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ 8346 #define I2C_ICR_PECCF_Pos (11U) 8347 #define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ 8348 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ 8349 #define I2C_ICR_TIMOUTCF_Pos (12U) 8350 #define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ 8351 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ 8352 #define I2C_ICR_ALERTCF_Pos (13U) 8353 #define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ 8354 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ 8355 8356 /****************** Bit definition for I2C_PECR register *********************/ 8357 #define I2C_PECR_PEC_Pos (0U) 8358 #define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ 8359 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ 8360 8361 /****************** Bit definition for I2C_RXDR register *********************/ 8362 #define I2C_RXDR_RXDATA_Pos (0U) 8363 #define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ 8364 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ 8365 8366 /****************** Bit definition for I2C_TXDR register *********************/ 8367 #define I2C_TXDR_TXDATA_Pos (0U) 8368 #define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ 8369 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ 8370 8371 /******************************************************************************/ 8372 /* */ 8373 /* Independent WATCHDOG */ 8374 /* */ 8375 /******************************************************************************/ 8376 /******************* Bit definition for IWDG_KR register ********************/ 8377 #define IWDG_KR_KEY_Pos (0U) 8378 #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ 8379 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */ 8380 8381 /******************* Bit definition for IWDG_PR register ********************/ 8382 #define IWDG_PR_PR_Pos (0U) 8383 #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */ 8384 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */ 8385 #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */ 8386 #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */ 8387 #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */ 8388 8389 /******************* Bit definition for IWDG_RLR register *******************/ 8390 #define IWDG_RLR_RL_Pos (0U) 8391 #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ 8392 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */ 8393 8394 /******************* Bit definition for IWDG_SR register ********************/ 8395 #define IWDG_SR_PVU_Pos (0U) 8396 #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ 8397 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */ 8398 #define IWDG_SR_RVU_Pos (1U) 8399 #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ 8400 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */ 8401 #define IWDG_SR_WVU_Pos (2U) 8402 #define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */ 8403 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */ 8404 8405 /******************* Bit definition for IWDG_KR register ********************/ 8406 #define IWDG_WINR_WIN_Pos (0U) 8407 #define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */ 8408 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */ 8409 8410 /******************************************************************************/ 8411 /* */ 8412 /* Firewall */ 8413 /* */ 8414 /******************************************************************************/ 8415 8416 /*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */ 8417 #define FW_CSSA_ADD_Pos (8U) 8418 #define FW_CSSA_ADD_Msk (0xFFFFUL << FW_CSSA_ADD_Pos) /*!< 0x00FFFF00 */ 8419 #define FW_CSSA_ADD FW_CSSA_ADD_Msk /*!< Code Segment Start Address */ 8420 #define FW_CSL_LENG_Pos (8U) 8421 #define FW_CSL_LENG_Msk (0x3FFFUL << FW_CSL_LENG_Pos) /*!< 0x003FFF00 */ 8422 #define FW_CSL_LENG FW_CSL_LENG_Msk /*!< Code Segment Length */ 8423 #define FW_NVDSSA_ADD_Pos (8U) 8424 #define FW_NVDSSA_ADD_Msk (0xFFFFUL << FW_NVDSSA_ADD_Pos) /*!< 0x00FFFF00 */ 8425 #define FW_NVDSSA_ADD FW_NVDSSA_ADD_Msk /*!< Non Volatile Dat Segment Start Address */ 8426 #define FW_NVDSL_LENG_Pos (8U) 8427 #define FW_NVDSL_LENG_Msk (0x3FFFUL << FW_NVDSL_LENG_Pos) /*!< 0x003FFF00 */ 8428 #define FW_NVDSL_LENG FW_NVDSL_LENG_Msk /*!< Non Volatile Data Segment Length */ 8429 #define FW_VDSSA_ADD_Pos (6U) 8430 #define FW_VDSSA_ADD_Msk (0x7FFUL << FW_VDSSA_ADD_Pos) /*!< 0x0001FFC0 */ 8431 #define FW_VDSSA_ADD FW_VDSSA_ADD_Msk /*!< Volatile Data Segment Start Address */ 8432 #define FW_VDSL_LENG_Pos (6U) 8433 #define FW_VDSL_LENG_Msk (0x7FFUL << FW_VDSL_LENG_Pos) /*!< 0x0001FFC0 */ 8434 #define FW_VDSL_LENG FW_VDSL_LENG_Msk /*!< Volatile Data Segment Length */ 8435 8436 /**************************Bit definition for CR register *********************/ 8437 #define FW_CR_FPA_Pos (0U) 8438 #define FW_CR_FPA_Msk (0x1UL << FW_CR_FPA_Pos) /*!< 0x00000001 */ 8439 #define FW_CR_FPA FW_CR_FPA_Msk /*!< Firewall Pre Arm*/ 8440 #define FW_CR_VDS_Pos (1U) 8441 #define FW_CR_VDS_Msk (0x1UL << FW_CR_VDS_Pos) /*!< 0x00000002 */ 8442 #define FW_CR_VDS FW_CR_VDS_Msk /*!< Volatile Data Sharing*/ 8443 #define FW_CR_VDE_Pos (2U) 8444 #define FW_CR_VDE_Msk (0x1UL << FW_CR_VDE_Pos) /*!< 0x00000004 */ 8445 #define FW_CR_VDE FW_CR_VDE_Msk /*!< Volatile Data Execution*/ 8446 8447 /******************************************************************************/ 8448 /* */ 8449 /* Power Control */ 8450 /* */ 8451 /******************************************************************************/ 8452 8453 /******************** Bit definition for PWR_CR1 register ********************/ 8454 8455 #define PWR_CR1_LPR_Pos (14U) 8456 #define PWR_CR1_LPR_Msk (0x1UL << PWR_CR1_LPR_Pos) /*!< 0x00004000 */ 8457 #define PWR_CR1_LPR PWR_CR1_LPR_Msk /*!< Regulator low-power mode */ 8458 #define PWR_CR1_VOS_Pos (9U) 8459 #define PWR_CR1_VOS_Msk (0x3UL << PWR_CR1_VOS_Pos) /*!< 0x00000600 */ 8460 #define PWR_CR1_VOS PWR_CR1_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */ 8461 #define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_Pos) /*!< 0x00000200 */ 8462 #define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_Pos) /*!< 0x00000400 */ 8463 #define PWR_CR1_DBP_Pos (8U) 8464 #define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos) /*!< 0x00000100 */ 8465 #define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up domain Protection */ 8466 #define PWR_CR1_LPMS_Pos (0U) 8467 #define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */ 8468 #define PWR_CR1_LPMS PWR_CR1_LPMS_Msk /*!< Low-power mode selection field */ 8469 #define PWR_CR1_LPMS_STOP0 (0x00000000UL) /*!< Stop 0 mode */ 8470 #define PWR_CR1_LPMS_STOP1_Pos (0U) 8471 #define PWR_CR1_LPMS_STOP1_Msk (0x1UL << PWR_CR1_LPMS_STOP1_Pos) /*!< 0x00000001 */ 8472 #define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_Msk /*!< Stop 1 mode */ 8473 #define PWR_CR1_LPMS_STOP2_Pos (1U) 8474 #define PWR_CR1_LPMS_STOP2_Msk (0x1UL << PWR_CR1_LPMS_STOP2_Pos) /*!< 0x00000002 */ 8475 #define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_Msk /*!< Stop 2 mode */ 8476 #define PWR_CR1_LPMS_STANDBY_Pos (0U) 8477 #define PWR_CR1_LPMS_STANDBY_Msk (0x3UL << PWR_CR1_LPMS_STANDBY_Pos) /*!< 0x00000003 */ 8478 #define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_Msk /*!< Stand-by mode */ 8479 #define PWR_CR1_LPMS_SHUTDOWN_Pos (2U) 8480 #define PWR_CR1_LPMS_SHUTDOWN_Msk (0x1UL << PWR_CR1_LPMS_SHUTDOWN_Pos) /*!< 0x00000004 */ 8481 #define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_Msk /*!< Shut-down mode */ 8482 8483 8484 /******************** Bit definition for PWR_CR2 register ********************/ 8485 #define PWR_CR2_USV_Pos (10U) 8486 #define PWR_CR2_USV_Msk (0x1UL << PWR_CR2_USV_Pos) /*!< 0x00000400 */ 8487 #define PWR_CR2_USV PWR_CR2_USV_Msk /*!< VDD USB Supply Valid */ 8488 /*!< PVME Peripheral Voltage Monitor Enable */ 8489 #define PWR_CR2_PVME_Pos (4U) 8490 #define PWR_CR2_PVME_Msk (0xDUL << PWR_CR2_PVME_Pos) /*!< 0x000000D0 */ 8491 #define PWR_CR2_PVME PWR_CR2_PVME_Msk /*!< PVM bits field */ 8492 #define PWR_CR2_PVME4_Pos (7U) 8493 #define PWR_CR2_PVME4_Msk (0x1UL << PWR_CR2_PVME4_Pos) /*!< 0x00000080 */ 8494 #define PWR_CR2_PVME4 PWR_CR2_PVME4_Msk /*!< PVM 4 Enable */ 8495 #define PWR_CR2_PVME3_Pos (6U) 8496 #define PWR_CR2_PVME3_Msk (0x1UL << PWR_CR2_PVME3_Pos) /*!< 0x00000040 */ 8497 #define PWR_CR2_PVME3 PWR_CR2_PVME3_Msk /*!< PVM 3 Enable */ 8498 #define PWR_CR2_PVME1_Pos (4U) 8499 #define PWR_CR2_PVME1_Msk (0x1UL << PWR_CR2_PVME1_Pos) /*!< 0x00000010 */ 8500 #define PWR_CR2_PVME1 PWR_CR2_PVME1_Msk /*!< PVM 1 Enable */ 8501 /*!< PVD level configuration */ 8502 #define PWR_CR2_PLS_Pos (1U) 8503 #define PWR_CR2_PLS_Msk (0x7UL << PWR_CR2_PLS_Pos) /*!< 0x0000000E */ 8504 #define PWR_CR2_PLS PWR_CR2_PLS_Msk /*!< PVD level selection */ 8505 #define PWR_CR2_PLS_LEV0 (0x00000000UL) /*!< PVD level 0 */ 8506 #define PWR_CR2_PLS_LEV1_Pos (1U) 8507 #define PWR_CR2_PLS_LEV1_Msk (0x1UL << PWR_CR2_PLS_LEV1_Pos) /*!< 0x00000002 */ 8508 #define PWR_CR2_PLS_LEV1 PWR_CR2_PLS_LEV1_Msk /*!< PVD level 1 */ 8509 #define PWR_CR2_PLS_LEV2_Pos (2U) 8510 #define PWR_CR2_PLS_LEV2_Msk (0x1UL << PWR_CR2_PLS_LEV2_Pos) /*!< 0x00000004 */ 8511 #define PWR_CR2_PLS_LEV2 PWR_CR2_PLS_LEV2_Msk /*!< PVD level 2 */ 8512 #define PWR_CR2_PLS_LEV3_Pos (1U) 8513 #define PWR_CR2_PLS_LEV3_Msk (0x3UL << PWR_CR2_PLS_LEV3_Pos) /*!< 0x00000006 */ 8514 #define PWR_CR2_PLS_LEV3 PWR_CR2_PLS_LEV3_Msk /*!< PVD level 3 */ 8515 #define PWR_CR2_PLS_LEV4_Pos (3U) 8516 #define PWR_CR2_PLS_LEV4_Msk (0x1UL << PWR_CR2_PLS_LEV4_Pos) /*!< 0x00000008 */ 8517 #define PWR_CR2_PLS_LEV4 PWR_CR2_PLS_LEV4_Msk /*!< PVD level 4 */ 8518 #define PWR_CR2_PLS_LEV5_Pos (1U) 8519 #define PWR_CR2_PLS_LEV5_Msk (0x5UL << PWR_CR2_PLS_LEV5_Pos) /*!< 0x0000000A */ 8520 #define PWR_CR2_PLS_LEV5 PWR_CR2_PLS_LEV5_Msk /*!< PVD level 5 */ 8521 #define PWR_CR2_PLS_LEV6_Pos (2U) 8522 #define PWR_CR2_PLS_LEV6_Msk (0x3UL << PWR_CR2_PLS_LEV6_Pos) /*!< 0x0000000C */ 8523 #define PWR_CR2_PLS_LEV6 PWR_CR2_PLS_LEV6_Msk /*!< PVD level 6 */ 8524 #define PWR_CR2_PLS_LEV7_Pos (1U) 8525 #define PWR_CR2_PLS_LEV7_Msk (0x7UL << PWR_CR2_PLS_LEV7_Pos) /*!< 0x0000000E */ 8526 #define PWR_CR2_PLS_LEV7 PWR_CR2_PLS_LEV7_Msk /*!< PVD level 7 */ 8527 #define PWR_CR2_PVDE_Pos (0U) 8528 #define PWR_CR2_PVDE_Msk (0x1UL << PWR_CR2_PVDE_Pos) /*!< 0x00000001 */ 8529 #define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power Voltage Detector Enable */ 8530 8531 /******************** Bit definition for PWR_CR3 register ********************/ 8532 #define PWR_CR3_EIWUL_Pos (15U) 8533 #define PWR_CR3_EIWUL_Msk (0x1UL << PWR_CR3_EIWUL_Pos) /*!< 0x00008000 */ 8534 #define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Enable Internal Wake-up line */ 8535 #define PWR_CR3_APC_Pos (10U) 8536 #define PWR_CR3_APC_Msk (0x1UL << PWR_CR3_APC_Pos) /*!< 0x00000400 */ 8537 #define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */ 8538 #define PWR_CR3_RRS_Pos (8U) 8539 #define PWR_CR3_RRS_Msk (0x1UL << PWR_CR3_RRS_Pos) /*!< 0x00000100 */ 8540 #define PWR_CR3_RRS PWR_CR3_RRS_Msk /*!< SRAM2 Retention in Stand-by mode */ 8541 #define PWR_CR3_EWUP5_Pos (4U) 8542 #define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */ 8543 #define PWR_CR3_EWUP5 PWR_CR3_EWUP5_Msk /*!< Enable Wake-Up Pin 5 */ 8544 #define PWR_CR3_EWUP4_Pos (3U) 8545 #define PWR_CR3_EWUP4_Msk (0x1UL << PWR_CR3_EWUP4_Pos) /*!< 0x00000008 */ 8546 #define PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk /*!< Enable Wake-Up Pin 4 */ 8547 #define PWR_CR3_EWUP3_Pos (2U) 8548 #define PWR_CR3_EWUP3_Msk (0x1UL << PWR_CR3_EWUP3_Pos) /*!< 0x00000004 */ 8549 #define PWR_CR3_EWUP3 PWR_CR3_EWUP3_Msk /*!< Enable Wake-Up Pin 3 */ 8550 #define PWR_CR3_EWUP2_Pos (1U) 8551 #define PWR_CR3_EWUP2_Msk (0x1UL << PWR_CR3_EWUP2_Pos) /*!< 0x00000002 */ 8552 #define PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk /*!< Enable Wake-Up Pin 2 */ 8553 #define PWR_CR3_EWUP1_Pos (0U) 8554 #define PWR_CR3_EWUP1_Msk (0x1UL << PWR_CR3_EWUP1_Pos) /*!< 0x00000001 */ 8555 #define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk /*!< Enable Wake-Up Pin 1 */ 8556 #define PWR_CR3_EWUP_Pos (0U) 8557 #define PWR_CR3_EWUP_Msk (0x1FUL << PWR_CR3_EWUP_Pos) /*!< 0x0000001F */ 8558 #define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable Wake-Up Pins */ 8559 8560 /* Legacy defines */ 8561 #define PWR_CR3_EIWF_Pos PWR_CR3_EIWUL_Pos 8562 #define PWR_CR3_EIWF_Msk PWR_CR3_EIWUL_Msk 8563 #define PWR_CR3_EIWF PWR_CR3_EIWUL 8564 8565 8566 /******************** Bit definition for PWR_CR4 register ********************/ 8567 #define PWR_CR4_VBRS_Pos (9U) 8568 #define PWR_CR4_VBRS_Msk (0x1UL << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */ 8569 #define PWR_CR4_VBRS PWR_CR4_VBRS_Msk /*!< VBAT Battery charging Resistor Selection */ 8570 #define PWR_CR4_VBE_Pos (8U) 8571 #define PWR_CR4_VBE_Msk (0x1UL << PWR_CR4_VBE_Pos) /*!< 0x00000100 */ 8572 #define PWR_CR4_VBE PWR_CR4_VBE_Msk /*!< VBAT Battery charging Enable */ 8573 #define PWR_CR4_WP5_Pos (4U) 8574 #define PWR_CR4_WP5_Msk (0x1UL << PWR_CR4_WP5_Pos) /*!< 0x00000010 */ 8575 #define PWR_CR4_WP5 PWR_CR4_WP5_Msk /*!< Wake-Up Pin 5 polarity */ 8576 #define PWR_CR4_WP4_Pos (3U) 8577 #define PWR_CR4_WP4_Msk (0x1UL << PWR_CR4_WP4_Pos) /*!< 0x00000008 */ 8578 #define PWR_CR4_WP4 PWR_CR4_WP4_Msk /*!< Wake-Up Pin 4 polarity */ 8579 #define PWR_CR4_WP3_Pos (2U) 8580 #define PWR_CR4_WP3_Msk (0x1UL << PWR_CR4_WP3_Pos) /*!< 0x00000004 */ 8581 #define PWR_CR4_WP3 PWR_CR4_WP3_Msk /*!< Wake-Up Pin 3 polarity */ 8582 #define PWR_CR4_WP2_Pos (1U) 8583 #define PWR_CR4_WP2_Msk (0x1UL << PWR_CR4_WP2_Pos) /*!< 0x00000002 */ 8584 #define PWR_CR4_WP2 PWR_CR4_WP2_Msk /*!< Wake-Up Pin 2 polarity */ 8585 #define PWR_CR4_WP1_Pos (0U) 8586 #define PWR_CR4_WP1_Msk (0x1UL << PWR_CR4_WP1_Pos) /*!< 0x00000001 */ 8587 #define PWR_CR4_WP1 PWR_CR4_WP1_Msk /*!< Wake-Up Pin 1 polarity */ 8588 8589 /******************** Bit definition for PWR_SR1 register ********************/ 8590 #define PWR_SR1_WUFI_Pos (15U) 8591 #define PWR_SR1_WUFI_Msk (0x1UL << PWR_SR1_WUFI_Pos) /*!< 0x00008000 */ 8592 #define PWR_SR1_WUFI PWR_SR1_WUFI_Msk /*!< Wake-Up Flag Internal */ 8593 #define PWR_SR1_SBF_Pos (8U) 8594 #define PWR_SR1_SBF_Msk (0x1UL << PWR_SR1_SBF_Pos) /*!< 0x00000100 */ 8595 #define PWR_SR1_SBF PWR_SR1_SBF_Msk /*!< Stand-By Flag */ 8596 #define PWR_SR1_WUF_Pos (0U) 8597 #define PWR_SR1_WUF_Msk (0x1FUL << PWR_SR1_WUF_Pos) /*!< 0x0000001F */ 8598 #define PWR_SR1_WUF PWR_SR1_WUF_Msk /*!< Wake-up Flags */ 8599 #define PWR_SR1_WUF5_Pos (4U) 8600 #define PWR_SR1_WUF5_Msk (0x1UL << PWR_SR1_WUF5_Pos) /*!< 0x00000010 */ 8601 #define PWR_SR1_WUF5 PWR_SR1_WUF5_Msk /*!< Wake-up Flag 5 */ 8602 #define PWR_SR1_WUF4_Pos (3U) 8603 #define PWR_SR1_WUF4_Msk (0x1UL << PWR_SR1_WUF4_Pos) /*!< 0x00000008 */ 8604 #define PWR_SR1_WUF4 PWR_SR1_WUF4_Msk /*!< Wake-up Flag 4 */ 8605 #define PWR_SR1_WUF3_Pos (2U) 8606 #define PWR_SR1_WUF3_Msk (0x1UL << PWR_SR1_WUF3_Pos) /*!< 0x00000004 */ 8607 #define PWR_SR1_WUF3 PWR_SR1_WUF3_Msk /*!< Wake-up Flag 3 */ 8608 #define PWR_SR1_WUF2_Pos (1U) 8609 #define PWR_SR1_WUF2_Msk (0x1UL << PWR_SR1_WUF2_Pos) /*!< 0x00000002 */ 8610 #define PWR_SR1_WUF2 PWR_SR1_WUF2_Msk /*!< Wake-up Flag 2 */ 8611 #define PWR_SR1_WUF1_Pos (0U) 8612 #define PWR_SR1_WUF1_Msk (0x1UL << PWR_SR1_WUF1_Pos) /*!< 0x00000001 */ 8613 #define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk /*!< Wake-up Flag 1 */ 8614 8615 /******************** Bit definition for PWR_SR2 register ********************/ 8616 #define PWR_SR2_PVMO4_Pos (15U) 8617 #define PWR_SR2_PVMO4_Msk (0x1UL << PWR_SR2_PVMO4_Pos) /*!< 0x00008000 */ 8618 #define PWR_SR2_PVMO4 PWR_SR2_PVMO4_Msk /*!< Peripheral Voltage Monitoring Output 4 */ 8619 #define PWR_SR2_PVMO3_Pos (14U) 8620 #define PWR_SR2_PVMO3_Msk (0x1UL << PWR_SR2_PVMO3_Pos) /*!< 0x00004000 */ 8621 #define PWR_SR2_PVMO3 PWR_SR2_PVMO3_Msk /*!< Peripheral Voltage Monitoring Output 3 */ 8622 #define PWR_SR2_PVDO_Pos (11U) 8623 #define PWR_SR2_PVDO_Msk (0x1UL << PWR_SR2_PVDO_Pos) /*!< 0x00000800 */ 8624 #define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power Voltage Detector Output */ 8625 #define PWR_SR2_VOSF_Pos (10U) 8626 #define PWR_SR2_VOSF_Msk (0x1UL << PWR_SR2_VOSF_Pos) /*!< 0x00000400 */ 8627 #define PWR_SR2_VOSF PWR_SR2_VOSF_Msk /*!< Voltage Scaling Flag */ 8628 #define PWR_SR2_REGLPF_Pos (9U) 8629 #define PWR_SR2_REGLPF_Msk (0x1UL << PWR_SR2_REGLPF_Pos) /*!< 0x00000200 */ 8630 #define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk /*!< Low-power Regulator Flag */ 8631 #define PWR_SR2_REGLPS_Pos (8U) 8632 #define PWR_SR2_REGLPS_Msk (0x1UL << PWR_SR2_REGLPS_Pos) /*!< 0x00000100 */ 8633 #define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk /*!< Low-power Regulator Started */ 8634 8635 /******************** Bit definition for PWR_SCR register ********************/ 8636 #define PWR_SCR_CSBF_Pos (8U) 8637 #define PWR_SCR_CSBF_Msk (0x1UL << PWR_SCR_CSBF_Pos) /*!< 0x00000100 */ 8638 #define PWR_SCR_CSBF PWR_SCR_CSBF_Msk /*!< Clear Stand-By Flag */ 8639 #define PWR_SCR_CWUF_Pos (0U) 8640 #define PWR_SCR_CWUF_Msk (0x1FUL << PWR_SCR_CWUF_Pos) /*!< 0x0000001F */ 8641 #define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up Flags */ 8642 #define PWR_SCR_CWUF5_Pos (4U) 8643 #define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */ 8644 #define PWR_SCR_CWUF5 PWR_SCR_CWUF5_Msk /*!< Clear Wake-up Flag 5 */ 8645 #define PWR_SCR_CWUF4_Pos (3U) 8646 #define PWR_SCR_CWUF4_Msk (0x1UL << PWR_SCR_CWUF4_Pos) /*!< 0x00000008 */ 8647 #define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk /*!< Clear Wake-up Flag 4 */ 8648 #define PWR_SCR_CWUF3_Pos (2U) 8649 #define PWR_SCR_CWUF3_Msk (0x1UL << PWR_SCR_CWUF3_Pos) /*!< 0x00000004 */ 8650 #define PWR_SCR_CWUF3 PWR_SCR_CWUF3_Msk /*!< Clear Wake-up Flag 3 */ 8651 #define PWR_SCR_CWUF2_Pos (1U) 8652 #define PWR_SCR_CWUF2_Msk (0x1UL << PWR_SCR_CWUF2_Pos) /*!< 0x00000002 */ 8653 #define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk /*!< Clear Wake-up Flag 2 */ 8654 #define PWR_SCR_CWUF1_Pos (0U) 8655 #define PWR_SCR_CWUF1_Msk (0x1UL << PWR_SCR_CWUF1_Pos) /*!< 0x00000001 */ 8656 #define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk /*!< Clear Wake-up Flag 1 */ 8657 8658 /******************** Bit definition for PWR_PUCRA register ********************/ 8659 #define PWR_PUCRA_PA15_Pos (15U) 8660 #define PWR_PUCRA_PA15_Msk (0x1UL << PWR_PUCRA_PA15_Pos) /*!< 0x00008000 */ 8661 #define PWR_PUCRA_PA15 PWR_PUCRA_PA15_Msk /*!< Port PA15 Pull-Up set */ 8662 #define PWR_PUCRA_PA13_Pos (13U) 8663 #define PWR_PUCRA_PA13_Msk (0x1UL << PWR_PUCRA_PA13_Pos) /*!< 0x00002000 */ 8664 #define PWR_PUCRA_PA13 PWR_PUCRA_PA13_Msk /*!< Port PA13 Pull-Up set */ 8665 #define PWR_PUCRA_PA12_Pos (12U) 8666 #define PWR_PUCRA_PA12_Msk (0x1UL << PWR_PUCRA_PA12_Pos) /*!< 0x00001000 */ 8667 #define PWR_PUCRA_PA12 PWR_PUCRA_PA12_Msk /*!< Port PA12 Pull-Up set */ 8668 #define PWR_PUCRA_PA11_Pos (11U) 8669 #define PWR_PUCRA_PA11_Msk (0x1UL << PWR_PUCRA_PA11_Pos) /*!< 0x00000800 */ 8670 #define PWR_PUCRA_PA11 PWR_PUCRA_PA11_Msk /*!< Port PA11 Pull-Up set */ 8671 #define PWR_PUCRA_PA10_Pos (10U) 8672 #define PWR_PUCRA_PA10_Msk (0x1UL << PWR_PUCRA_PA10_Pos) /*!< 0x00000400 */ 8673 #define PWR_PUCRA_PA10 PWR_PUCRA_PA10_Msk /*!< Port PA10 Pull-Up set */ 8674 #define PWR_PUCRA_PA9_Pos (9U) 8675 #define PWR_PUCRA_PA9_Msk (0x1UL << PWR_PUCRA_PA9_Pos) /*!< 0x00000200 */ 8676 #define PWR_PUCRA_PA9 PWR_PUCRA_PA9_Msk /*!< Port PA9 Pull-Up set */ 8677 #define PWR_PUCRA_PA8_Pos (8U) 8678 #define PWR_PUCRA_PA8_Msk (0x1UL << PWR_PUCRA_PA8_Pos) /*!< 0x00000100 */ 8679 #define PWR_PUCRA_PA8 PWR_PUCRA_PA8_Msk /*!< Port PA8 Pull-Up set */ 8680 #define PWR_PUCRA_PA7_Pos (7U) 8681 #define PWR_PUCRA_PA7_Msk (0x1UL << PWR_PUCRA_PA7_Pos) /*!< 0x00000080 */ 8682 #define PWR_PUCRA_PA7 PWR_PUCRA_PA7_Msk /*!< Port PA7 Pull-Up set */ 8683 #define PWR_PUCRA_PA6_Pos (6U) 8684 #define PWR_PUCRA_PA6_Msk (0x1UL << PWR_PUCRA_PA6_Pos) /*!< 0x00000040 */ 8685 #define PWR_PUCRA_PA6 PWR_PUCRA_PA6_Msk /*!< Port PA6 Pull-Up set */ 8686 #define PWR_PUCRA_PA5_Pos (5U) 8687 #define PWR_PUCRA_PA5_Msk (0x1UL << PWR_PUCRA_PA5_Pos) /*!< 0x00000020 */ 8688 #define PWR_PUCRA_PA5 PWR_PUCRA_PA5_Msk /*!< Port PA5 Pull-Up set */ 8689 #define PWR_PUCRA_PA4_Pos (4U) 8690 #define PWR_PUCRA_PA4_Msk (0x1UL << PWR_PUCRA_PA4_Pos) /*!< 0x00000010 */ 8691 #define PWR_PUCRA_PA4 PWR_PUCRA_PA4_Msk /*!< Port PA4 Pull-Up set */ 8692 #define PWR_PUCRA_PA3_Pos (3U) 8693 #define PWR_PUCRA_PA3_Msk (0x1UL << PWR_PUCRA_PA3_Pos) /*!< 0x00000008 */ 8694 #define PWR_PUCRA_PA3 PWR_PUCRA_PA3_Msk /*!< Port PA3 Pull-Up set */ 8695 #define PWR_PUCRA_PA2_Pos (2U) 8696 #define PWR_PUCRA_PA2_Msk (0x1UL << PWR_PUCRA_PA2_Pos) /*!< 0x00000004 */ 8697 #define PWR_PUCRA_PA2 PWR_PUCRA_PA2_Msk /*!< Port PA2 Pull-Up set */ 8698 #define PWR_PUCRA_PA1_Pos (1U) 8699 #define PWR_PUCRA_PA1_Msk (0x1UL << PWR_PUCRA_PA1_Pos) /*!< 0x00000002 */ 8700 #define PWR_PUCRA_PA1 PWR_PUCRA_PA1_Msk /*!< Port PA1 Pull-Up set */ 8701 #define PWR_PUCRA_PA0_Pos (0U) 8702 #define PWR_PUCRA_PA0_Msk (0x1UL << PWR_PUCRA_PA0_Pos) /*!< 0x00000001 */ 8703 #define PWR_PUCRA_PA0 PWR_PUCRA_PA0_Msk /*!< Port PA0 Pull-Up set */ 8704 8705 /******************** Bit definition for PWR_PDCRA register ********************/ 8706 #define PWR_PDCRA_PA14_Pos (14U) 8707 #define PWR_PDCRA_PA14_Msk (0x1UL << PWR_PDCRA_PA14_Pos) /*!< 0x00004000 */ 8708 #define PWR_PDCRA_PA14 PWR_PDCRA_PA14_Msk /*!< Port PA14 Pull-Down set */ 8709 #define PWR_PDCRA_PA12_Pos (12U) 8710 #define PWR_PDCRA_PA12_Msk (0x1UL << PWR_PDCRA_PA12_Pos) /*!< 0x00001000 */ 8711 #define PWR_PDCRA_PA12 PWR_PDCRA_PA12_Msk /*!< Port PA12 Pull-Down set */ 8712 #define PWR_PDCRA_PA11_Pos (11U) 8713 #define PWR_PDCRA_PA11_Msk (0x1UL << PWR_PDCRA_PA11_Pos) /*!< 0x00000800 */ 8714 #define PWR_PDCRA_PA11 PWR_PDCRA_PA11_Msk /*!< Port PA11 Pull-Down set */ 8715 #define PWR_PDCRA_PA10_Pos (10U) 8716 #define PWR_PDCRA_PA10_Msk (0x1UL << PWR_PDCRA_PA10_Pos) /*!< 0x00000400 */ 8717 #define PWR_PDCRA_PA10 PWR_PDCRA_PA10_Msk /*!< Port PA10 Pull-Down set */ 8718 #define PWR_PDCRA_PA9_Pos (9U) 8719 #define PWR_PDCRA_PA9_Msk (0x1UL << PWR_PDCRA_PA9_Pos) /*!< 0x00000200 */ 8720 #define PWR_PDCRA_PA9 PWR_PDCRA_PA9_Msk /*!< Port PA9 Pull-Down set */ 8721 #define PWR_PDCRA_PA8_Pos (8U) 8722 #define PWR_PDCRA_PA8_Msk (0x1UL << PWR_PDCRA_PA8_Pos) /*!< 0x00000100 */ 8723 #define PWR_PDCRA_PA8 PWR_PDCRA_PA8_Msk /*!< Port PA8 Pull-Down set */ 8724 #define PWR_PDCRA_PA7_Pos (7U) 8725 #define PWR_PDCRA_PA7_Msk (0x1UL << PWR_PDCRA_PA7_Pos) /*!< 0x00000080 */ 8726 #define PWR_PDCRA_PA7 PWR_PDCRA_PA7_Msk /*!< Port PA7 Pull-Down set */ 8727 #define PWR_PDCRA_PA6_Pos (6U) 8728 #define PWR_PDCRA_PA6_Msk (0x1UL << PWR_PDCRA_PA6_Pos) /*!< 0x00000040 */ 8729 #define PWR_PDCRA_PA6 PWR_PDCRA_PA6_Msk /*!< Port PA6 Pull-Down set */ 8730 #define PWR_PDCRA_PA5_Pos (5U) 8731 #define PWR_PDCRA_PA5_Msk (0x1UL << PWR_PDCRA_PA5_Pos) /*!< 0x00000020 */ 8732 #define PWR_PDCRA_PA5 PWR_PDCRA_PA5_Msk /*!< Port PA5 Pull-Down set */ 8733 #define PWR_PDCRA_PA4_Pos (4U) 8734 #define PWR_PDCRA_PA4_Msk (0x1UL << PWR_PDCRA_PA4_Pos) /*!< 0x00000010 */ 8735 #define PWR_PDCRA_PA4 PWR_PDCRA_PA4_Msk /*!< Port PA4 Pull-Down set */ 8736 #define PWR_PDCRA_PA3_Pos (3U) 8737 #define PWR_PDCRA_PA3_Msk (0x1UL << PWR_PDCRA_PA3_Pos) /*!< 0x00000008 */ 8738 #define PWR_PDCRA_PA3 PWR_PDCRA_PA3_Msk /*!< Port PA3 Pull-Down set */ 8739 #define PWR_PDCRA_PA2_Pos (2U) 8740 #define PWR_PDCRA_PA2_Msk (0x1UL << PWR_PDCRA_PA2_Pos) /*!< 0x00000004 */ 8741 #define PWR_PDCRA_PA2 PWR_PDCRA_PA2_Msk /*!< Port PA2 Pull-Down set */ 8742 #define PWR_PDCRA_PA1_Pos (1U) 8743 #define PWR_PDCRA_PA1_Msk (0x1UL << PWR_PDCRA_PA1_Pos) /*!< 0x00000002 */ 8744 #define PWR_PDCRA_PA1 PWR_PDCRA_PA1_Msk /*!< Port PA1 Pull-Down set */ 8745 #define PWR_PDCRA_PA0_Pos (0U) 8746 #define PWR_PDCRA_PA0_Msk (0x1UL << PWR_PDCRA_PA0_Pos) /*!< 0x00000001 */ 8747 #define PWR_PDCRA_PA0 PWR_PDCRA_PA0_Msk /*!< Port PA0 Pull-Down set */ 8748 8749 /******************** Bit definition for PWR_PUCRB register ********************/ 8750 #define PWR_PUCRB_PB7_Pos (7U) 8751 #define PWR_PUCRB_PB7_Msk (0x1UL << PWR_PUCRB_PB7_Pos) /*!< 0x00000080 */ 8752 #define PWR_PUCRB_PB7 PWR_PUCRB_PB7_Msk /*!< Port PB7 Pull-Up set */ 8753 #define PWR_PUCRB_PB6_Pos (6U) 8754 #define PWR_PUCRB_PB6_Msk (0x1UL << PWR_PUCRB_PB6_Pos) /*!< 0x00000040 */ 8755 #define PWR_PUCRB_PB6 PWR_PUCRB_PB6_Msk /*!< Port PB6 Pull-Up set */ 8756 #define PWR_PUCRB_PB5_Pos (5U) 8757 #define PWR_PUCRB_PB5_Msk (0x1UL << PWR_PUCRB_PB5_Pos) /*!< 0x00000020 */ 8758 #define PWR_PUCRB_PB5 PWR_PUCRB_PB5_Msk /*!< Port PB5 Pull-Up set */ 8759 #define PWR_PUCRB_PB4_Pos (4U) 8760 #define PWR_PUCRB_PB4_Msk (0x1UL << PWR_PUCRB_PB4_Pos) /*!< 0x00000010 */ 8761 #define PWR_PUCRB_PB4 PWR_PUCRB_PB4_Msk /*!< Port PB4 Pull-Up set */ 8762 #define PWR_PUCRB_PB3_Pos (3U) 8763 #define PWR_PUCRB_PB3_Msk (0x1UL << PWR_PUCRB_PB3_Pos) /*!< 0x00000008 */ 8764 #define PWR_PUCRB_PB3 PWR_PUCRB_PB3_Msk /*!< Port PB3 Pull-Up set */ 8765 #define PWR_PUCRB_PB1_Pos (1U) 8766 #define PWR_PUCRB_PB1_Msk (0x1UL << PWR_PUCRB_PB1_Pos) /*!< 0x00000002 */ 8767 #define PWR_PUCRB_PB1 PWR_PUCRB_PB1_Msk /*!< Port PB1 Pull-Up set */ 8768 #define PWR_PUCRB_PB0_Pos (0U) 8769 #define PWR_PUCRB_PB0_Msk (0x1UL << PWR_PUCRB_PB0_Pos) /*!< 0x00000001 */ 8770 #define PWR_PUCRB_PB0 PWR_PUCRB_PB0_Msk /*!< Port PB0 Pull-Up set */ 8771 8772 /******************** Bit definition for PWR_PDCRB register ********************/ 8773 #define PWR_PDCRB_PB7_Pos (7U) 8774 #define PWR_PDCRB_PB7_Msk (0x1UL << PWR_PDCRB_PB7_Pos) /*!< 0x00000080 */ 8775 #define PWR_PDCRB_PB7 PWR_PDCRB_PB7_Msk /*!< Port PB7 Pull-Down set */ 8776 #define PWR_PDCRB_PB6_Pos (6U) 8777 #define PWR_PDCRB_PB6_Msk (0x1UL << PWR_PDCRB_PB6_Pos) /*!< 0x00000040 */ 8778 #define PWR_PDCRB_PB6 PWR_PDCRB_PB6_Msk /*!< Port PB6 Pull-Down set */ 8779 #define PWR_PDCRB_PB5_Pos (5U) 8780 #define PWR_PDCRB_PB5_Msk (0x1UL << PWR_PDCRB_PB5_Pos) /*!< 0x00000020 */ 8781 #define PWR_PDCRB_PB5 PWR_PDCRB_PB5_Msk /*!< Port PB5 Pull-Down set */ 8782 #define PWR_PDCRB_PB3_Pos (3U) 8783 #define PWR_PDCRB_PB3_Msk (0x1UL << PWR_PDCRB_PB3_Pos) /*!< 0x00000008 */ 8784 #define PWR_PDCRB_PB3 PWR_PDCRB_PB3_Msk /*!< Port PB3 Pull-Down set */ 8785 #define PWR_PDCRB_PB1_Pos (1U) 8786 #define PWR_PDCRB_PB1_Msk (0x1UL << PWR_PDCRB_PB1_Pos) /*!< 0x00000002 */ 8787 #define PWR_PDCRB_PB1 PWR_PDCRB_PB1_Msk /*!< Port PB1 Pull-Down set */ 8788 #define PWR_PDCRB_PB0_Pos (0U) 8789 #define PWR_PDCRB_PB0_Msk (0x1UL << PWR_PDCRB_PB0_Pos) /*!< 0x00000001 */ 8790 #define PWR_PDCRB_PB0 PWR_PDCRB_PB0_Msk /*!< Port PB0 Pull-Down set */ 8791 8792 /******************** Bit definition for PWR_PUCRC register ********************/ 8793 #define PWR_PUCRC_PC15_Pos (15U) 8794 #define PWR_PUCRC_PC15_Msk (0x1UL << PWR_PUCRC_PC15_Pos) /*!< 0x00008000 */ 8795 #define PWR_PUCRC_PC15 PWR_PUCRC_PC15_Msk /*!< Port PC15 Pull-Up set */ 8796 #define PWR_PUCRC_PC14_Pos (14U) 8797 #define PWR_PUCRC_PC14_Msk (0x1UL << PWR_PUCRC_PC14_Pos) /*!< 0x00004000 */ 8798 #define PWR_PUCRC_PC14 PWR_PUCRC_PC14_Msk /*!< Port PC14 Pull-Up set */ 8799 8800 /******************** Bit definition for PWR_PDCRC register ********************/ 8801 #define PWR_PDCRC_PC15_Pos (15U) 8802 #define PWR_PDCRC_PC15_Msk (0x1UL << PWR_PDCRC_PC15_Pos) /*!< 0x00008000 */ 8803 #define PWR_PDCRC_PC15 PWR_PDCRC_PC15_Msk /*!< Port PC15 Pull-Down set */ 8804 #define PWR_PDCRC_PC14_Pos (14U) 8805 #define PWR_PDCRC_PC14_Msk (0x1UL << PWR_PDCRC_PC14_Pos) /*!< 0x00004000 */ 8806 #define PWR_PDCRC_PC14 PWR_PDCRC_PC14_Msk /*!< Port PC14 Pull-Down set */ 8807 8808 8809 8810 8811 /******************** Bit definition for PWR_PUCRH register ********************/ 8812 #define PWR_PUCRH_PH3_Pos (3U) 8813 #define PWR_PUCRH_PH3_Msk (0x1UL << PWR_PUCRH_PH3_Pos) /*!< 0x00000008 */ 8814 #define PWR_PUCRH_PH3 PWR_PUCRH_PH3_Msk /*!< Port PH3 Pull-Up set */ 8815 8816 /******************** Bit definition for PWR_PDCRH register ********************/ 8817 #define PWR_PDCRH_PH3_Pos (3U) 8818 #define PWR_PDCRH_PH3_Msk (0x1UL << PWR_PDCRH_PH3_Pos) /*!< 0x00000008 */ 8819 #define PWR_PDCRH_PH3 PWR_PDCRH_PH3_Msk /*!< Port PH3 Pull-Down set */ 8820 8821 8822 /******************************************************************************/ 8823 /* */ 8824 /* Reset and Clock Control */ 8825 /* */ 8826 /******************************************************************************/ 8827 /* 8828 * @brief Specific device feature definitions (not present on all devices in the STM32L4 series) 8829 */ 8830 #define RCC_PLLSAI1_SUPPORT 8831 #define RCC_PLLP_SUPPORT 8832 #define RCC_HSI48_SUPPORT 8833 #define RCC_PLLP_DIV_2_31_SUPPORT 8834 #define RCC_PLLSAI1P_DIV_2_31_SUPPORT 8835 8836 /******************** Bit definition for RCC_CR register ********************/ 8837 #define RCC_CR_MSION_Pos (0U) 8838 #define RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos) /*!< 0x00000001 */ 8839 #define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed oscillator (MSI) clock enable */ 8840 #define RCC_CR_MSIRDY_Pos (1U) 8841 #define RCC_CR_MSIRDY_Msk (0x1UL << RCC_CR_MSIRDY_Pos) /*!< 0x00000002 */ 8842 #define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed oscillator (MSI) clock ready flag */ 8843 #define RCC_CR_MSIPLLEN_Pos (2U) 8844 #define RCC_CR_MSIPLLEN_Msk (0x1UL << RCC_CR_MSIPLLEN_Pos) /*!< 0x00000004 */ 8845 #define RCC_CR_MSIPLLEN RCC_CR_MSIPLLEN_Msk /*!< Internal Multi Speed oscillator (MSI) PLL enable */ 8846 #define RCC_CR_MSIRGSEL_Pos (3U) 8847 #define RCC_CR_MSIRGSEL_Msk (0x1UL << RCC_CR_MSIRGSEL_Pos) /*!< 0x00000008 */ 8848 #define RCC_CR_MSIRGSEL RCC_CR_MSIRGSEL_Msk /*!< Internal Multi Speed oscillator (MSI) range selection */ 8849 8850 /*!< MSIRANGE configuration : 12 frequency ranges available */ 8851 #define RCC_CR_MSIRANGE_Pos (4U) 8852 #define RCC_CR_MSIRANGE_Msk (0xFUL << RCC_CR_MSIRANGE_Pos) /*!< 0x000000F0 */ 8853 #define RCC_CR_MSIRANGE RCC_CR_MSIRANGE_Msk /*!< Internal Multi Speed oscillator (MSI) clock Range */ 8854 #define RCC_CR_MSIRANGE_0 (0x0UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000000 */ 8855 #define RCC_CR_MSIRANGE_1 (0x1UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000010 */ 8856 #define RCC_CR_MSIRANGE_2 (0x2UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000020 */ 8857 #define RCC_CR_MSIRANGE_3 (0x3UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000030 */ 8858 #define RCC_CR_MSIRANGE_4 (0x4UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000040 */ 8859 #define RCC_CR_MSIRANGE_5 (0x5UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000050 */ 8860 #define RCC_CR_MSIRANGE_6 (0x6UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000060 */ 8861 #define RCC_CR_MSIRANGE_7 (0x7UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000070 */ 8862 #define RCC_CR_MSIRANGE_8 (0x8UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000080 */ 8863 #define RCC_CR_MSIRANGE_9 (0x9UL << RCC_CR_MSIRANGE_Pos) /*!< 0x00000090 */ 8864 #define RCC_CR_MSIRANGE_10 (0xAUL << RCC_CR_MSIRANGE_Pos) /*!< 0x000000A0 */ 8865 #define RCC_CR_MSIRANGE_11 (0xBUL << RCC_CR_MSIRANGE_Pos) /*!< 0x000000B0 */ 8866 8867 #define RCC_CR_HSION_Pos (8U) 8868 #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000100 */ 8869 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed oscillator (HSI16) clock enable */ 8870 #define RCC_CR_HSIKERON_Pos (9U) 8871 #define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000200 */ 8872 #define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */ 8873 #define RCC_CR_HSIRDY_Pos (10U) 8874 #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */ 8875 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed oscillator (HSI16) clock ready flag */ 8876 #define RCC_CR_HSIASFS_Pos (11U) 8877 #define RCC_CR_HSIASFS_Msk (0x1UL << RCC_CR_HSIASFS_Pos) /*!< 0x00000800 */ 8878 #define RCC_CR_HSIASFS RCC_CR_HSIASFS_Msk /*!< HSI16 Automatic Start from Stop */ 8879 8880 #define RCC_CR_HSEON_Pos (16U) 8881 #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ 8882 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed oscillator (HSE) clock enable */ 8883 #define RCC_CR_HSERDY_Pos (17U) 8884 #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ 8885 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed oscillator (HSE) clock ready */ 8886 #define RCC_CR_HSEBYP_Pos (18U) 8887 #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ 8888 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed oscillator (HSE) clock bypass */ 8889 #define RCC_CR_CSSON_Pos (19U) 8890 #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ 8891 #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< HSE Clock Security System enable */ 8892 8893 #define RCC_CR_PLLON_Pos (24U) 8894 #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ 8895 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */ 8896 #define RCC_CR_PLLRDY_Pos (25U) 8897 #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ 8898 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */ 8899 #define RCC_CR_PLLSAI1ON_Pos (26U) 8900 #define RCC_CR_PLLSAI1ON_Msk (0x1UL << RCC_CR_PLLSAI1ON_Pos) /*!< 0x04000000 */ 8901 #define RCC_CR_PLLSAI1ON RCC_CR_PLLSAI1ON_Msk /*!< SAI1 PLL enable */ 8902 #define RCC_CR_PLLSAI1RDY_Pos (27U) 8903 #define RCC_CR_PLLSAI1RDY_Msk (0x1UL << RCC_CR_PLLSAI1RDY_Pos) /*!< 0x08000000 */ 8904 #define RCC_CR_PLLSAI1RDY RCC_CR_PLLSAI1RDY_Msk /*!< SAI1 PLL ready */ 8905 8906 /******************** Bit definition for RCC_ICSCR register ***************/ 8907 /*!< MSICAL configuration */ 8908 #define RCC_ICSCR_MSICAL_Pos (0U) 8909 #define RCC_ICSCR_MSICAL_Msk (0xFFUL << RCC_ICSCR_MSICAL_Pos) /*!< 0x000000FF */ 8910 #define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< MSICAL[7:0] bits */ 8911 #define RCC_ICSCR_MSICAL_0 (0x01UL << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000001 */ 8912 #define RCC_ICSCR_MSICAL_1 (0x02UL << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000002 */ 8913 #define RCC_ICSCR_MSICAL_2 (0x04UL << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000004 */ 8914 #define RCC_ICSCR_MSICAL_3 (0x08UL << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000008 */ 8915 #define RCC_ICSCR_MSICAL_4 (0x10UL << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000010 */ 8916 #define RCC_ICSCR_MSICAL_5 (0x20UL << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000020 */ 8917 #define RCC_ICSCR_MSICAL_6 (0x40UL << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000040 */ 8918 #define RCC_ICSCR_MSICAL_7 (0x80UL << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000080 */ 8919 8920 /*!< MSITRIM configuration */ 8921 #define RCC_ICSCR_MSITRIM_Pos (8U) 8922 #define RCC_ICSCR_MSITRIM_Msk (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x0000FF00 */ 8923 #define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< MSITRIM[7:0] bits */ 8924 #define RCC_ICSCR_MSITRIM_0 (0x01UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000100 */ 8925 #define RCC_ICSCR_MSITRIM_1 (0x02UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000200 */ 8926 #define RCC_ICSCR_MSITRIM_2 (0x04UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000400 */ 8927 #define RCC_ICSCR_MSITRIM_3 (0x08UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000800 */ 8928 #define RCC_ICSCR_MSITRIM_4 (0x10UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00001000 */ 8929 #define RCC_ICSCR_MSITRIM_5 (0x20UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00002000 */ 8930 #define RCC_ICSCR_MSITRIM_6 (0x40UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00004000 */ 8931 #define RCC_ICSCR_MSITRIM_7 (0x80UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00008000 */ 8932 8933 /*!< HSICAL configuration */ 8934 #define RCC_ICSCR_HSICAL_Pos (16U) 8935 #define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00FF0000 */ 8936 #define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< HSICAL[7:0] bits */ 8937 #define RCC_ICSCR_HSICAL_0 (0x01UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00010000 */ 8938 #define RCC_ICSCR_HSICAL_1 (0x02UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00020000 */ 8939 #define RCC_ICSCR_HSICAL_2 (0x04UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00040000 */ 8940 #define RCC_ICSCR_HSICAL_3 (0x08UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00080000 */ 8941 #define RCC_ICSCR_HSICAL_4 (0x10UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00100000 */ 8942 #define RCC_ICSCR_HSICAL_5 (0x20UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00200000 */ 8943 #define RCC_ICSCR_HSICAL_6 (0x40UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00400000 */ 8944 #define RCC_ICSCR_HSICAL_7 (0x80UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00800000 */ 8945 8946 /*!< HSITRIM configuration */ 8947 #define RCC_ICSCR_HSITRIM_Pos (24U) 8948 #define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x1F000000 */ 8949 #define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[4:0] bits */ 8950 #define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */ 8951 #define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */ 8952 #define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */ 8953 #define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */ 8954 #define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */ 8955 8956 /******************** Bit definition for RCC_CFGR register ******************/ 8957 /*!< SW configuration */ 8958 #define RCC_CFGR_SW_Pos (0U) 8959 #define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ 8960 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ 8961 #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ 8962 #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ 8963 8964 #define RCC_CFGR_SW_MSI (0x00000000UL) /*!< MSI oscillator selection as system clock */ 8965 #define RCC_CFGR_SW_HSI (0x00000001UL) /*!< HSI16 oscillator selection as system clock */ 8966 #define RCC_CFGR_SW_HSE (0x00000002UL) /*!< HSE oscillator selection as system clock */ 8967 #define RCC_CFGR_SW_PLL (0x00000003UL) /*!< PLL selection as system clock */ 8968 8969 /*!< SWS configuration */ 8970 #define RCC_CFGR_SWS_Pos (2U) 8971 #define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ 8972 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ 8973 #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ 8974 #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ 8975 8976 #define RCC_CFGR_SWS_MSI (0x00000000UL) /*!< MSI oscillator used as system clock */ 8977 #define RCC_CFGR_SWS_HSI (0x00000004UL) /*!< HSI16 oscillator used as system clock */ 8978 #define RCC_CFGR_SWS_HSE (0x00000008UL) /*!< HSE oscillator used as system clock */ 8979 #define RCC_CFGR_SWS_PLL (0x0000000CUL) /*!< PLL used as system clock */ 8980 8981 /*!< HPRE configuration */ 8982 #define RCC_CFGR_HPRE_Pos (4U) 8983 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ 8984 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ 8985 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ 8986 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ 8987 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ 8988 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ 8989 8990 #define RCC_CFGR_HPRE_DIV1 (0x00000000UL) /*!< SYSCLK not divided */ 8991 #define RCC_CFGR_HPRE_DIV2 (0x00000080UL) /*!< SYSCLK divided by 2 */ 8992 #define RCC_CFGR_HPRE_DIV4 (0x00000090UL) /*!< SYSCLK divided by 4 */ 8993 #define RCC_CFGR_HPRE_DIV8 (0x000000A0UL) /*!< SYSCLK divided by 8 */ 8994 #define RCC_CFGR_HPRE_DIV16 (0x000000B0UL) /*!< SYSCLK divided by 16 */ 8995 #define RCC_CFGR_HPRE_DIV64 (0x000000C0UL) /*!< SYSCLK divided by 64 */ 8996 #define RCC_CFGR_HPRE_DIV128 (0x000000D0UL) /*!< SYSCLK divided by 128 */ 8997 #define RCC_CFGR_HPRE_DIV256 (0x000000E0UL) /*!< SYSCLK divided by 256 */ 8998 #define RCC_CFGR_HPRE_DIV512 (0x000000F0UL) /*!< SYSCLK divided by 512 */ 8999 9000 /*!< PPRE1 configuration */ 9001 #define RCC_CFGR_PPRE1_Pos (8U) 9002 #define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ 9003 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB2 prescaler) */ 9004 #define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ 9005 #define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ 9006 #define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ 9007 9008 #define RCC_CFGR_PPRE1_DIV1 (0x00000000UL) /*!< HCLK not divided */ 9009 #define RCC_CFGR_PPRE1_DIV2 (0x00000400UL) /*!< HCLK divided by 2 */ 9010 #define RCC_CFGR_PPRE1_DIV4 (0x00000500UL) /*!< HCLK divided by 4 */ 9011 #define RCC_CFGR_PPRE1_DIV8 (0x00000600UL) /*!< HCLK divided by 8 */ 9012 #define RCC_CFGR_PPRE1_DIV16 (0x00000700UL) /*!< HCLK divided by 16 */ 9013 9014 /*!< PPRE2 configuration */ 9015 #define RCC_CFGR_PPRE2_Pos (11U) 9016 #define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ 9017 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ 9018 #define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ 9019 #define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ 9020 #define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ 9021 9022 #define RCC_CFGR_PPRE2_DIV1 (0x00000000UL) /*!< HCLK not divided */ 9023 #define RCC_CFGR_PPRE2_DIV2 (0x00002000UL) /*!< HCLK divided by 2 */ 9024 #define RCC_CFGR_PPRE2_DIV4 (0x00002800UL) /*!< HCLK divided by 4 */ 9025 #define RCC_CFGR_PPRE2_DIV8 (0x00003000UL) /*!< HCLK divided by 8 */ 9026 #define RCC_CFGR_PPRE2_DIV16 (0x00003800UL) /*!< HCLK divided by 16 */ 9027 9028 #define RCC_CFGR_STOPWUCK_Pos (15U) 9029 #define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */ 9030 #define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from stop and CSS backup clock selection */ 9031 9032 /*!< MCOSEL configuration */ 9033 #define RCC_CFGR_MCOSEL_Pos (24U) 9034 #define RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */ 9035 #define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCOSEL [3:0] bits (Clock output selection) */ 9036 #define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */ 9037 #define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */ 9038 #define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */ 9039 #define RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */ 9040 9041 #define RCC_CFGR_MCOPRE_Pos (28U) 9042 #define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */ 9043 #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */ 9044 #define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */ 9045 #define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */ 9046 #define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */ 9047 9048 #define RCC_CFGR_MCOPRE_DIV1 (0x00000000UL) /*!< MCO is divided by 1 */ 9049 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000UL) /*!< MCO is divided by 2 */ 9050 #define RCC_CFGR_MCOPRE_DIV4 (0x20000000UL) /*!< MCO is divided by 4 */ 9051 #define RCC_CFGR_MCOPRE_DIV8 (0x30000000UL) /*!< MCO is divided by 8 */ 9052 #define RCC_CFGR_MCOPRE_DIV16 (0x40000000UL) /*!< MCO is divided by 16 */ 9053 9054 /* Legacy aliases */ 9055 #define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE 9056 #define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1 9057 #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 9058 #define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4 9059 #define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8 9060 #define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16 9061 9062 /******************** Bit definition for RCC_PLLCFGR register ***************/ 9063 #define RCC_PLLCFGR_PLLSRC_Pos (0U) 9064 #define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */ 9065 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk 9066 9067 #define RCC_PLLCFGR_PLLSRC_MSI_Pos (0U) 9068 #define RCC_PLLCFGR_PLLSRC_MSI_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_MSI_Pos) /*!< 0x00000001 */ 9069 #define RCC_PLLCFGR_PLLSRC_MSI RCC_PLLCFGR_PLLSRC_MSI_Msk /*!< MSI oscillator source clock selected */ 9070 #define RCC_PLLCFGR_PLLSRC_HSI_Pos (1U) 9071 #define RCC_PLLCFGR_PLLSRC_HSI_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSI_Pos) /*!< 0x00000002 */ 9072 #define RCC_PLLCFGR_PLLSRC_HSI RCC_PLLCFGR_PLLSRC_HSI_Msk /*!< HSI16 oscillator source clock selected */ 9073 #define RCC_PLLCFGR_PLLSRC_HSE_Pos (0U) 9074 #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00000003 */ 9075 #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk /*!< HSE oscillator source clock selected */ 9076 9077 #define RCC_PLLCFGR_PLLM_Pos (4U) 9078 #define RCC_PLLCFGR_PLLM_Msk (0x7UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000070 */ 9079 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk 9080 #define RCC_PLLCFGR_PLLM_0 (0x1UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */ 9081 #define RCC_PLLCFGR_PLLM_1 (0x2UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */ 9082 #define RCC_PLLCFGR_PLLM_2 (0x4UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000040 */ 9083 9084 #define RCC_PLLCFGR_PLLN_Pos (8U) 9085 #define RCC_PLLCFGR_PLLN_Msk (0x7FUL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007F00 */ 9086 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk 9087 #define RCC_PLLCFGR_PLLN_0 (0x01UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */ 9088 #define RCC_PLLCFGR_PLLN_1 (0x02UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */ 9089 #define RCC_PLLCFGR_PLLN_2 (0x04UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */ 9090 #define RCC_PLLCFGR_PLLN_3 (0x08UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */ 9091 #define RCC_PLLCFGR_PLLN_4 (0x10UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */ 9092 #define RCC_PLLCFGR_PLLN_5 (0x20UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */ 9093 #define RCC_PLLCFGR_PLLN_6 (0x40UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */ 9094 9095 #define RCC_PLLCFGR_PLLPEN_Pos (16U) 9096 #define RCC_PLLCFGR_PLLPEN_Msk (0x1UL << RCC_PLLCFGR_PLLPEN_Pos) /*!< 0x00010000 */ 9097 #define RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk 9098 #define RCC_PLLCFGR_PLLP_Pos (17U) 9099 #define RCC_PLLCFGR_PLLP_Msk (0x1UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */ 9100 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk 9101 #define RCC_PLLCFGR_PLLQEN_Pos (20U) 9102 #define RCC_PLLCFGR_PLLQEN_Msk (0x1UL << RCC_PLLCFGR_PLLQEN_Pos) /*!< 0x00100000 */ 9103 #define RCC_PLLCFGR_PLLQEN RCC_PLLCFGR_PLLQEN_Msk 9104 9105 #define RCC_PLLCFGR_PLLQ_Pos (21U) 9106 #define RCC_PLLCFGR_PLLQ_Msk (0x3UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00600000 */ 9107 #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk 9108 #define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00200000 */ 9109 #define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00400000 */ 9110 9111 #define RCC_PLLCFGR_PLLREN_Pos (24U) 9112 #define RCC_PLLCFGR_PLLREN_Msk (0x1UL << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x01000000 */ 9113 #define RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk 9114 #define RCC_PLLCFGR_PLLR_Pos (25U) 9115 #define RCC_PLLCFGR_PLLR_Msk (0x3UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x06000000 */ 9116 #define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk 9117 #define RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x02000000 */ 9118 #define RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x04000000 */ 9119 9120 #define RCC_PLLCFGR_PLLPDIV_Pos (27U) 9121 #define RCC_PLLCFGR_PLLPDIV_Msk (0x1FUL << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0xF8000000 */ 9122 #define RCC_PLLCFGR_PLLPDIV RCC_PLLCFGR_PLLPDIV_Msk 9123 #define RCC_PLLCFGR_PLLPDIV_0 (0x01UL << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x08000000 */ 9124 #define RCC_PLLCFGR_PLLPDIV_1 (0x02UL << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x10000000 */ 9125 #define RCC_PLLCFGR_PLLPDIV_2 (0x04UL << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x20000000 */ 9126 #define RCC_PLLCFGR_PLLPDIV_3 (0x08UL << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x40000000 */ 9127 #define RCC_PLLCFGR_PLLPDIV_4 (0x10UL << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x80000000 */ 9128 9129 /******************** Bit definition for RCC_PLLSAI1CFGR register ************/ 9130 #define RCC_PLLSAI1CFGR_PLLSAI1N_Pos (8U) 9131 #define RCC_PLLSAI1CFGR_PLLSAI1N_Msk (0x7FUL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00007F00 */ 9132 #define RCC_PLLSAI1CFGR_PLLSAI1N RCC_PLLSAI1CFGR_PLLSAI1N_Msk 9133 #define RCC_PLLSAI1CFGR_PLLSAI1N_0 (0x01UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000100 */ 9134 #define RCC_PLLSAI1CFGR_PLLSAI1N_1 (0x02UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000200 */ 9135 #define RCC_PLLSAI1CFGR_PLLSAI1N_2 (0x04UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000400 */ 9136 #define RCC_PLLSAI1CFGR_PLLSAI1N_3 (0x08UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000800 */ 9137 #define RCC_PLLSAI1CFGR_PLLSAI1N_4 (0x10UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00001000 */ 9138 #define RCC_PLLSAI1CFGR_PLLSAI1N_5 (0x20UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00002000 */ 9139 #define RCC_PLLSAI1CFGR_PLLSAI1N_6 (0x40UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00004000 */ 9140 9141 #define RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos (16U) 9142 #define RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos) /*!< 0x00010000 */ 9143 #define RCC_PLLSAI1CFGR_PLLSAI1PEN RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk 9144 #define RCC_PLLSAI1CFGR_PLLSAI1P_Pos (17U) 9145 #define RCC_PLLSAI1CFGR_PLLSAI1P_Msk (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) /*!< 0x00020000 */ 9146 #define RCC_PLLSAI1CFGR_PLLSAI1P RCC_PLLSAI1CFGR_PLLSAI1P_Msk 9147 9148 #define RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos (20U) 9149 #define RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos) /*!< 0x00100000 */ 9150 #define RCC_PLLSAI1CFGR_PLLSAI1QEN RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk 9151 #define RCC_PLLSAI1CFGR_PLLSAI1Q_Pos (21U) 9152 #define RCC_PLLSAI1CFGR_PLLSAI1Q_Msk (0x3UL << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00600000 */ 9153 #define RCC_PLLSAI1CFGR_PLLSAI1Q RCC_PLLSAI1CFGR_PLLSAI1Q_Msk 9154 #define RCC_PLLSAI1CFGR_PLLSAI1Q_0 (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00200000 */ 9155 #define RCC_PLLSAI1CFGR_PLLSAI1Q_1 (0x2UL << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00400000 */ 9156 9157 #define RCC_PLLSAI1CFGR_PLLSAI1REN_Pos (24U) 9158 #define RCC_PLLSAI1CFGR_PLLSAI1REN_Msk (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1REN_Pos) /*!< 0x01000000 */ 9159 #define RCC_PLLSAI1CFGR_PLLSAI1REN RCC_PLLSAI1CFGR_PLLSAI1REN_Msk 9160 #define RCC_PLLSAI1CFGR_PLLSAI1R_Pos (25U) 9161 #define RCC_PLLSAI1CFGR_PLLSAI1R_Msk (0x3UL << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x06000000 */ 9162 #define RCC_PLLSAI1CFGR_PLLSAI1R RCC_PLLSAI1CFGR_PLLSAI1R_Msk 9163 #define RCC_PLLSAI1CFGR_PLLSAI1R_0 (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x02000000 */ 9164 #define RCC_PLLSAI1CFGR_PLLSAI1R_1 (0x2UL << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x04000000 */ 9165 9166 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos (27U) 9167 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_Msk (0x1FUL << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0xF8000000 */ 9168 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV RCC_PLLSAI1CFGR_PLLSAI1PDIV_Msk 9169 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_0 (0x01UL << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x08000000 */ 9170 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_1 (0x02UL << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x10000000 */ 9171 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_2 (0x04UL << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x20000000 */ 9172 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_3 (0x08UL << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x40000000 */ 9173 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_4 (0x10UL << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x80000000 */ 9174 9175 /******************** Bit definition for RCC_CIER register ******************/ 9176 #define RCC_CIER_LSIRDYIE_Pos (0U) 9177 #define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ 9178 #define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk 9179 #define RCC_CIER_LSERDYIE_Pos (1U) 9180 #define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ 9181 #define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk 9182 #define RCC_CIER_MSIRDYIE_Pos (2U) 9183 #define RCC_CIER_MSIRDYIE_Msk (0x1UL << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000004 */ 9184 #define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk 9185 #define RCC_CIER_HSIRDYIE_Pos (3U) 9186 #define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */ 9187 #define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk 9188 #define RCC_CIER_HSERDYIE_Pos (4U) 9189 #define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */ 9190 #define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk 9191 #define RCC_CIER_PLLRDYIE_Pos (5U) 9192 #define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000020 */ 9193 #define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk 9194 #define RCC_CIER_PLLSAI1RDYIE_Pos (6U) 9195 #define RCC_CIER_PLLSAI1RDYIE_Msk (0x1UL << RCC_CIER_PLLSAI1RDYIE_Pos) /*!< 0x00000040 */ 9196 #define RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE_Msk 9197 #define RCC_CIER_LSECSSIE_Pos (9U) 9198 #define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */ 9199 #define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk 9200 #define RCC_CIER_HSI48RDYIE_Pos (10U) 9201 #define RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000400 */ 9202 #define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk 9203 9204 /******************** Bit definition for RCC_CIFR register ******************/ 9205 #define RCC_CIFR_LSIRDYF_Pos (0U) 9206 #define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ 9207 #define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk 9208 #define RCC_CIFR_LSERDYF_Pos (1U) 9209 #define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ 9210 #define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk 9211 #define RCC_CIFR_MSIRDYF_Pos (2U) 9212 #define RCC_CIFR_MSIRDYF_Msk (0x1UL << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000004 */ 9213 #define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk 9214 #define RCC_CIFR_HSIRDYF_Pos (3U) 9215 #define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */ 9216 #define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk 9217 #define RCC_CIFR_HSERDYF_Pos (4U) 9218 #define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */ 9219 #define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk 9220 #define RCC_CIFR_PLLRDYF_Pos (5U) 9221 #define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000020 */ 9222 #define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk 9223 #define RCC_CIFR_PLLSAI1RDYF_Pos (6U) 9224 #define RCC_CIFR_PLLSAI1RDYF_Msk (0x1UL << RCC_CIFR_PLLSAI1RDYF_Pos) /*!< 0x00000040 */ 9225 #define RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF_Msk 9226 #define RCC_CIFR_CSSF_Pos (8U) 9227 #define RCC_CIFR_CSSF_Msk (0x1UL << RCC_CIFR_CSSF_Pos) /*!< 0x00000100 */ 9228 #define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk 9229 #define RCC_CIFR_LSECSSF_Pos (9U) 9230 #define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */ 9231 #define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk 9232 #define RCC_CIFR_HSI48RDYF_Pos (10U) 9233 #define RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000400 */ 9234 #define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk 9235 9236 /******************** Bit definition for RCC_CICR register ******************/ 9237 #define RCC_CICR_LSIRDYC_Pos (0U) 9238 #define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */ 9239 #define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk 9240 #define RCC_CICR_LSERDYC_Pos (1U) 9241 #define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ 9242 #define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk 9243 #define RCC_CICR_MSIRDYC_Pos (2U) 9244 #define RCC_CICR_MSIRDYC_Msk (0x1UL << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000004 */ 9245 #define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk 9246 #define RCC_CICR_HSIRDYC_Pos (3U) 9247 #define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */ 9248 #define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk 9249 #define RCC_CICR_HSERDYC_Pos (4U) 9250 #define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */ 9251 #define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk 9252 #define RCC_CICR_PLLRDYC_Pos (5U) 9253 #define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000020 */ 9254 #define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk 9255 #define RCC_CICR_PLLSAI1RDYC_Pos (6U) 9256 #define RCC_CICR_PLLSAI1RDYC_Msk (0x1UL << RCC_CICR_PLLSAI1RDYC_Pos) /*!< 0x00000040 */ 9257 #define RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC_Msk 9258 #define RCC_CICR_CSSC_Pos (8U) 9259 #define RCC_CICR_CSSC_Msk (0x1UL << RCC_CICR_CSSC_Pos) /*!< 0x00000100 */ 9260 #define RCC_CICR_CSSC RCC_CICR_CSSC_Msk 9261 #define RCC_CICR_LSECSSC_Pos (9U) 9262 #define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */ 9263 #define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk 9264 #define RCC_CICR_HSI48RDYC_Pos (10U) 9265 #define RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000400 */ 9266 #define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk 9267 9268 /******************** Bit definition for RCC_AHB1RSTR register **************/ 9269 #define RCC_AHB1RSTR_DMA1RST_Pos (0U) 9270 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00000001 */ 9271 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk 9272 #define RCC_AHB1RSTR_DMA2RST_Pos (1U) 9273 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00000002 */ 9274 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk 9275 #define RCC_AHB1RSTR_FLASHRST_Pos (8U) 9276 #define RCC_AHB1RSTR_FLASHRST_Msk (0x1UL << RCC_AHB1RSTR_FLASHRST_Pos) /*!< 0x00000100 */ 9277 #define RCC_AHB1RSTR_FLASHRST RCC_AHB1RSTR_FLASHRST_Msk 9278 #define RCC_AHB1RSTR_CRCRST_Pos (12U) 9279 #define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */ 9280 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk 9281 #define RCC_AHB1RSTR_TSCRST_Pos (16U) 9282 #define RCC_AHB1RSTR_TSCRST_Msk (0x1UL << RCC_AHB1RSTR_TSCRST_Pos) /*!< 0x00010000 */ 9283 #define RCC_AHB1RSTR_TSCRST RCC_AHB1RSTR_TSCRST_Msk 9284 9285 /******************** Bit definition for RCC_AHB2RSTR register **************/ 9286 #define RCC_AHB2RSTR_GPIOARST_Pos (0U) 9287 #define RCC_AHB2RSTR_GPIOARST_Msk (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */ 9288 #define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk 9289 #define RCC_AHB2RSTR_GPIOBRST_Pos (1U) 9290 #define RCC_AHB2RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */ 9291 #define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk 9292 #define RCC_AHB2RSTR_GPIOCRST_Pos (2U) 9293 #define RCC_AHB2RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */ 9294 #define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk 9295 #define RCC_AHB2RSTR_GPIOHRST_Pos (7U) 9296 #define RCC_AHB2RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */ 9297 #define RCC_AHB2RSTR_GPIOHRST RCC_AHB2RSTR_GPIOHRST_Msk 9298 #define RCC_AHB2RSTR_ADCRST_Pos (13U) 9299 #define RCC_AHB2RSTR_ADCRST_Msk (0x1UL << RCC_AHB2RSTR_ADCRST_Pos) /*!< 0x00002000 */ 9300 #define RCC_AHB2RSTR_ADCRST RCC_AHB2RSTR_ADCRST_Msk 9301 #define RCC_AHB2RSTR_RNGRST_Pos (18U) 9302 #define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */ 9303 #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk 9304 9305 /******************** Bit definition for RCC_AHB3RSTR register **************/ 9306 #define RCC_AHB3RSTR_QSPIRST_Pos (8U) 9307 #define RCC_AHB3RSTR_QSPIRST_Msk (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000100 */ 9308 #define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk 9309 9310 /******************** Bit definition for RCC_APB1RSTR1 register **************/ 9311 #define RCC_APB1RSTR1_TIM2RST_Pos (0U) 9312 #define RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */ 9313 #define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk 9314 #define RCC_APB1RSTR1_TIM6RST_Pos (4U) 9315 #define RCC_APB1RSTR1_TIM6RST_Msk (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos) /*!< 0x00000010 */ 9316 #define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk 9317 #define RCC_APB1RSTR1_TIM7RST_Pos (5U) 9318 #define RCC_APB1RSTR1_TIM7RST_Msk (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos) /*!< 0x00000020 */ 9319 #define RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk 9320 #define RCC_APB1RSTR1_SPI3RST_Pos (15U) 9321 #define RCC_APB1RSTR1_SPI3RST_Msk (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos) /*!< 0x00008000 */ 9322 #define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk 9323 #define RCC_APB1RSTR1_USART2RST_Pos (17U) 9324 #define RCC_APB1RSTR1_USART2RST_Msk (0x1UL << RCC_APB1RSTR1_USART2RST_Pos) /*!< 0x00020000 */ 9325 #define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk 9326 #define RCC_APB1RSTR1_I2C1RST_Pos (21U) 9327 #define RCC_APB1RSTR1_I2C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos) /*!< 0x00200000 */ 9328 #define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk 9329 #define RCC_APB1RSTR1_I2C3RST_Pos (23U) 9330 #define RCC_APB1RSTR1_I2C3RST_Msk (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos) /*!< 0x00800000 */ 9331 #define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk 9332 #define RCC_APB1RSTR1_CRSRST_Pos (24U) 9333 #define RCC_APB1RSTR1_CRSRST_Msk (0x1UL << RCC_APB1RSTR1_CRSRST_Pos) /*!< 0x01000000 */ 9334 #define RCC_APB1RSTR1_CRSRST RCC_APB1RSTR1_CRSRST_Msk 9335 #define RCC_APB1RSTR1_CAN1RST_Pos (25U) 9336 #define RCC_APB1RSTR1_CAN1RST_Msk (0x1UL << RCC_APB1RSTR1_CAN1RST_Pos) /*!< 0x02000000 */ 9337 #define RCC_APB1RSTR1_CAN1RST RCC_APB1RSTR1_CAN1RST_Msk 9338 #define RCC_APB1RSTR1_USBFSRST_Pos (26U) 9339 #define RCC_APB1RSTR1_USBFSRST_Msk (0x1UL << RCC_APB1RSTR1_USBFSRST_Pos) /*!< 0x04000000 */ 9340 #define RCC_APB1RSTR1_USBFSRST RCC_APB1RSTR1_USBFSRST_Msk 9341 #define RCC_APB1RSTR1_PWRRST_Pos (28U) 9342 #define RCC_APB1RSTR1_PWRRST_Msk (0x1UL << RCC_APB1RSTR1_PWRRST_Pos) /*!< 0x10000000 */ 9343 #define RCC_APB1RSTR1_PWRRST RCC_APB1RSTR1_PWRRST_Msk 9344 #define RCC_APB1RSTR1_DAC1RST_Pos (29U) 9345 #define RCC_APB1RSTR1_DAC1RST_Msk (0x1UL << RCC_APB1RSTR1_DAC1RST_Pos) /*!< 0x20000000 */ 9346 #define RCC_APB1RSTR1_DAC1RST RCC_APB1RSTR1_DAC1RST_Msk 9347 #define RCC_APB1RSTR1_OPAMPRST_Pos (30U) 9348 #define RCC_APB1RSTR1_OPAMPRST_Msk (0x1UL << RCC_APB1RSTR1_OPAMPRST_Pos) /*!< 0x40000000 */ 9349 #define RCC_APB1RSTR1_OPAMPRST RCC_APB1RSTR1_OPAMPRST_Msk 9350 #define RCC_APB1RSTR1_LPTIM1RST_Pos (31U) 9351 #define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos) /*!< 0x80000000 */ 9352 #define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk 9353 9354 /******************** Bit definition for RCC_APB1RSTR2 register **************/ 9355 #define RCC_APB1RSTR2_LPUART1RST_Pos (0U) 9356 #define RCC_APB1RSTR2_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR2_LPUART1RST_Pos) /*!< 0x00000001 */ 9357 #define RCC_APB1RSTR2_LPUART1RST RCC_APB1RSTR2_LPUART1RST_Msk 9358 #define RCC_APB1RSTR2_SWPMI1RST_Pos (2U) 9359 #define RCC_APB1RSTR2_SWPMI1RST_Msk (0x1UL << RCC_APB1RSTR2_SWPMI1RST_Pos) /*!< 0x00000004 */ 9360 #define RCC_APB1RSTR2_SWPMI1RST RCC_APB1RSTR2_SWPMI1RST_Msk 9361 #define RCC_APB1RSTR2_LPTIM2RST_Pos (5U) 9362 #define RCC_APB1RSTR2_LPTIM2RST_Msk (0x1UL << RCC_APB1RSTR2_LPTIM2RST_Pos) /*!< 0x00000020 */ 9363 #define RCC_APB1RSTR2_LPTIM2RST RCC_APB1RSTR2_LPTIM2RST_Msk 9364 9365 /******************** Bit definition for RCC_APB2RSTR register **************/ 9366 #define RCC_APB2RSTR_SYSCFGRST_Pos (0U) 9367 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ 9368 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk 9369 #define RCC_APB2RSTR_TIM1RST_Pos (11U) 9370 #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ 9371 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk 9372 #define RCC_APB2RSTR_SPI1RST_Pos (12U) 9373 #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ 9374 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk 9375 #define RCC_APB2RSTR_USART1RST_Pos (14U) 9376 #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ 9377 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk 9378 #define RCC_APB2RSTR_TIM15RST_Pos (16U) 9379 #define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ 9380 #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk 9381 #define RCC_APB2RSTR_TIM16RST_Pos (17U) 9382 #define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ 9383 #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk 9384 #define RCC_APB2RSTR_SAI1RST_Pos (21U) 9385 #define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00200000 */ 9386 #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk 9387 9388 /******************** Bit definition for RCC_AHB1ENR register ***************/ 9389 #define RCC_AHB1ENR_DMA1EN_Pos (0U) 9390 #define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */ 9391 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk 9392 #define RCC_AHB1ENR_DMA2EN_Pos (1U) 9393 #define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */ 9394 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk 9395 #define RCC_AHB1ENR_FLASHEN_Pos (8U) 9396 #define RCC_AHB1ENR_FLASHEN_Msk (0x1UL << RCC_AHB1ENR_FLASHEN_Pos) /*!< 0x00000100 */ 9397 #define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk 9398 #define RCC_AHB1ENR_CRCEN_Pos (12U) 9399 #define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */ 9400 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk 9401 #define RCC_AHB1ENR_TSCEN_Pos (16U) 9402 #define RCC_AHB1ENR_TSCEN_Msk (0x1UL << RCC_AHB1ENR_TSCEN_Pos) /*!< 0x00010000 */ 9403 #define RCC_AHB1ENR_TSCEN RCC_AHB1ENR_TSCEN_Msk 9404 9405 /******************** Bit definition for RCC_AHB2ENR register ***************/ 9406 #define RCC_AHB2ENR_GPIOAEN_Pos (0U) 9407 #define RCC_AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */ 9408 #define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk 9409 #define RCC_AHB2ENR_GPIOBEN_Pos (1U) 9410 #define RCC_AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */ 9411 #define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk 9412 #define RCC_AHB2ENR_GPIOCEN_Pos (2U) 9413 #define RCC_AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */ 9414 #define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk 9415 #define RCC_AHB2ENR_GPIOHEN_Pos (7U) 9416 #define RCC_AHB2ENR_GPIOHEN_Msk (0x1UL << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */ 9417 #define RCC_AHB2ENR_GPIOHEN RCC_AHB2ENR_GPIOHEN_Msk 9418 #define RCC_AHB2ENR_ADCEN_Pos (13U) 9419 #define RCC_AHB2ENR_ADCEN_Msk (0x1UL << RCC_AHB2ENR_ADCEN_Pos) /*!< 0x00002000 */ 9420 #define RCC_AHB2ENR_ADCEN RCC_AHB2ENR_ADCEN_Msk 9421 #define RCC_AHB2ENR_RNGEN_Pos (18U) 9422 #define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00040000 */ 9423 #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk 9424 9425 /******************** Bit definition for RCC_AHB3ENR register ***************/ 9426 #define RCC_AHB3ENR_QSPIEN_Pos (8U) 9427 #define RCC_AHB3ENR_QSPIEN_Msk (0x1UL << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000100 */ 9428 #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk 9429 9430 /******************** Bit definition for RCC_APB1ENR1 register ***************/ 9431 #define RCC_APB1ENR1_TIM2EN_Pos (0U) 9432 #define RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */ 9433 #define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk 9434 #define RCC_APB1ENR1_TIM6EN_Pos (4U) 9435 #define RCC_APB1ENR1_TIM6EN_Msk (0x1UL << RCC_APB1ENR1_TIM6EN_Pos) /*!< 0x00000010 */ 9436 #define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk 9437 #define RCC_APB1ENR1_TIM7EN_Pos (5U) 9438 #define RCC_APB1ENR1_TIM7EN_Msk (0x1UL << RCC_APB1ENR1_TIM7EN_Pos) /*!< 0x00000020 */ 9439 #define RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk 9440 #define RCC_APB1ENR1_RTCAPBEN_Pos (10U) 9441 #define RCC_APB1ENR1_RTCAPBEN_Msk (0x1UL << RCC_APB1ENR1_RTCAPBEN_Pos) /*!< 0x00000400 */ 9442 #define RCC_APB1ENR1_RTCAPBEN RCC_APB1ENR1_RTCAPBEN_Msk 9443 #define RCC_APB1ENR1_WWDGEN_Pos (11U) 9444 #define RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */ 9445 #define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk 9446 #define RCC_APB1ENR1_SPI3EN_Pos (15U) 9447 #define RCC_APB1ENR1_SPI3EN_Msk (0x1UL << RCC_APB1ENR1_SPI3EN_Pos) /*!< 0x00008000 */ 9448 #define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk 9449 #define RCC_APB1ENR1_USART2EN_Pos (17U) 9450 #define RCC_APB1ENR1_USART2EN_Msk (0x1UL << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */ 9451 #define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk 9452 #define RCC_APB1ENR1_I2C1EN_Pos (21U) 9453 #define RCC_APB1ENR1_I2C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */ 9454 #define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk 9455 #define RCC_APB1ENR1_I2C3EN_Pos (23U) 9456 #define RCC_APB1ENR1_I2C3EN_Msk (0x1UL << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */ 9457 #define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk 9458 #define RCC_APB1ENR1_CRSEN_Pos (24U) 9459 #define RCC_APB1ENR1_CRSEN_Msk (0x1UL << RCC_APB1ENR1_CRSEN_Pos) /*!< 0x01000000 */ 9460 #define RCC_APB1ENR1_CRSEN RCC_APB1ENR1_CRSEN_Msk 9461 #define RCC_APB1ENR1_CAN1EN_Pos (25U) 9462 #define RCC_APB1ENR1_CAN1EN_Msk (0x1UL << RCC_APB1ENR1_CAN1EN_Pos) /*!< 0x02000000 */ 9463 #define RCC_APB1ENR1_CAN1EN RCC_APB1ENR1_CAN1EN_Msk 9464 #define RCC_APB1ENR1_USBFSEN_Pos (26U) 9465 #define RCC_APB1ENR1_USBFSEN_Msk (0x1UL << RCC_APB1ENR1_USBFSEN_Pos) /*!< 0x04000000 */ 9466 #define RCC_APB1ENR1_USBFSEN RCC_APB1ENR1_USBFSEN_Msk 9467 #define RCC_APB1ENR1_PWREN_Pos (28U) 9468 #define RCC_APB1ENR1_PWREN_Msk (0x1UL << RCC_APB1ENR1_PWREN_Pos) /*!< 0x10000000 */ 9469 #define RCC_APB1ENR1_PWREN RCC_APB1ENR1_PWREN_Msk 9470 #define RCC_APB1ENR1_DAC1EN_Pos (29U) 9471 #define RCC_APB1ENR1_DAC1EN_Msk (0x1UL << RCC_APB1ENR1_DAC1EN_Pos) /*!< 0x20000000 */ 9472 #define RCC_APB1ENR1_DAC1EN RCC_APB1ENR1_DAC1EN_Msk 9473 #define RCC_APB1ENR1_OPAMPEN_Pos (30U) 9474 #define RCC_APB1ENR1_OPAMPEN_Msk (0x1UL << RCC_APB1ENR1_OPAMPEN_Pos) /*!< 0x40000000 */ 9475 #define RCC_APB1ENR1_OPAMPEN RCC_APB1ENR1_OPAMPEN_Msk 9476 #define RCC_APB1ENR1_LPTIM1EN_Pos (31U) 9477 #define RCC_APB1ENR1_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos) /*!< 0x80000000 */ 9478 #define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk 9479 9480 /******************** Bit definition for RCC_APB1RSTR2 register **************/ 9481 #define RCC_APB1ENR2_LPUART1EN_Pos (0U) 9482 #define RCC_APB1ENR2_LPUART1EN_Msk (0x1UL << RCC_APB1ENR2_LPUART1EN_Pos) /*!< 0x00000001 */ 9483 #define RCC_APB1ENR2_LPUART1EN RCC_APB1ENR2_LPUART1EN_Msk 9484 #define RCC_APB1ENR2_SWPMI1EN_Pos (2U) 9485 #define RCC_APB1ENR2_SWPMI1EN_Msk (0x1UL << RCC_APB1ENR2_SWPMI1EN_Pos) /*!< 0x00000004 */ 9486 #define RCC_APB1ENR2_SWPMI1EN RCC_APB1ENR2_SWPMI1EN_Msk 9487 #define RCC_APB1ENR2_LPTIM2EN_Pos (5U) 9488 #define RCC_APB1ENR2_LPTIM2EN_Msk (0x1UL << RCC_APB1ENR2_LPTIM2EN_Pos) /*!< 0x00000020 */ 9489 #define RCC_APB1ENR2_LPTIM2EN RCC_APB1ENR2_LPTIM2EN_Msk 9490 9491 /******************** Bit definition for RCC_APB2ENR register ***************/ 9492 #define RCC_APB2ENR_SYSCFGEN_Pos (0U) 9493 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */ 9494 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk 9495 #define RCC_APB2ENR_FWEN_Pos (7U) 9496 #define RCC_APB2ENR_FWEN_Msk (0x1UL << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */ 9497 #define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk 9498 #define RCC_APB2ENR_TIM1EN_Pos (11U) 9499 #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ 9500 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk 9501 #define RCC_APB2ENR_SPI1EN_Pos (12U) 9502 #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ 9503 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk 9504 #define RCC_APB2ENR_USART1EN_Pos (14U) 9505 #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ 9506 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk 9507 #define RCC_APB2ENR_TIM15EN_Pos (16U) 9508 #define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */ 9509 #define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk 9510 #define RCC_APB2ENR_TIM16EN_Pos (17U) 9511 #define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ 9512 #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk 9513 #define RCC_APB2ENR_SAI1EN_Pos (21U) 9514 #define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00200000 */ 9515 #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk 9516 9517 /******************** Bit definition for RCC_AHB1SMENR register ***************/ 9518 #define RCC_AHB1SMENR_DMA1SMEN_Pos (0U) 9519 #define RCC_AHB1SMENR_DMA1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA1SMEN_Pos) /*!< 0x00000001 */ 9520 #define RCC_AHB1SMENR_DMA1SMEN RCC_AHB1SMENR_DMA1SMEN_Msk 9521 #define RCC_AHB1SMENR_DMA2SMEN_Pos (1U) 9522 #define RCC_AHB1SMENR_DMA2SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA2SMEN_Pos) /*!< 0x00000002 */ 9523 #define RCC_AHB1SMENR_DMA2SMEN RCC_AHB1SMENR_DMA2SMEN_Msk 9524 #define RCC_AHB1SMENR_FLASHSMEN_Pos (8U) 9525 #define RCC_AHB1SMENR_FLASHSMEN_Msk (0x1UL << RCC_AHB1SMENR_FLASHSMEN_Pos) /*!< 0x00000100 */ 9526 #define RCC_AHB1SMENR_FLASHSMEN RCC_AHB1SMENR_FLASHSMEN_Msk 9527 #define RCC_AHB1SMENR_SRAM1SMEN_Pos (9U) 9528 #define RCC_AHB1SMENR_SRAM1SMEN_Msk (0x1UL << RCC_AHB1SMENR_SRAM1SMEN_Pos) /*!< 0x00000200 */ 9529 #define RCC_AHB1SMENR_SRAM1SMEN RCC_AHB1SMENR_SRAM1SMEN_Msk 9530 #define RCC_AHB1SMENR_CRCSMEN_Pos (12U) 9531 #define RCC_AHB1SMENR_CRCSMEN_Msk (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos) /*!< 0x00001000 */ 9532 #define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk 9533 #define RCC_AHB1SMENR_TSCSMEN_Pos (16U) 9534 #define RCC_AHB1SMENR_TSCSMEN_Msk (0x1UL << RCC_AHB1SMENR_TSCSMEN_Pos) /*!< 0x00010000 */ 9535 #define RCC_AHB1SMENR_TSCSMEN RCC_AHB1SMENR_TSCSMEN_Msk 9536 9537 /******************** Bit definition for RCC_AHB2SMENR register *************/ 9538 #define RCC_AHB2SMENR_GPIOASMEN_Pos (0U) 9539 #define RCC_AHB2SMENR_GPIOASMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos) /*!< 0x00000001 */ 9540 #define RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk 9541 #define RCC_AHB2SMENR_GPIOBSMEN_Pos (1U) 9542 #define RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */ 9543 #define RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk 9544 #define RCC_AHB2SMENR_GPIOCSMEN_Pos (2U) 9545 #define RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */ 9546 #define RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk 9547 #define RCC_AHB2SMENR_GPIOHSMEN_Pos (7U) 9548 #define RCC_AHB2SMENR_GPIOHSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOHSMEN_Pos) /*!< 0x00000080 */ 9549 #define RCC_AHB2SMENR_GPIOHSMEN RCC_AHB2SMENR_GPIOHSMEN_Msk 9550 #define RCC_AHB2SMENR_SRAM2SMEN_Pos (9U) 9551 #define RCC_AHB2SMENR_SRAM2SMEN_Msk (0x1UL << RCC_AHB2SMENR_SRAM2SMEN_Pos) /*!< 0x00000200 */ 9552 #define RCC_AHB2SMENR_SRAM2SMEN RCC_AHB2SMENR_SRAM2SMEN_Msk 9553 #define RCC_AHB2SMENR_ADCSMEN_Pos (13U) 9554 #define RCC_AHB2SMENR_ADCSMEN_Msk (0x1UL << RCC_AHB2SMENR_ADCSMEN_Pos) /*!< 0x00002000 */ 9555 #define RCC_AHB2SMENR_ADCSMEN RCC_AHB2SMENR_ADCSMEN_Msk 9556 #define RCC_AHB2SMENR_RNGSMEN_Pos (18U) 9557 #define RCC_AHB2SMENR_RNGSMEN_Msk (0x1UL << RCC_AHB2SMENR_RNGSMEN_Pos) /*!< 0x00040000 */ 9558 #define RCC_AHB2SMENR_RNGSMEN RCC_AHB2SMENR_RNGSMEN_Msk 9559 9560 /******************** Bit definition for RCC_AHB3SMENR register *************/ 9561 #define RCC_AHB3SMENR_QSPISMEN_Pos (8U) 9562 #define RCC_AHB3SMENR_QSPISMEN_Msk (0x1UL << RCC_AHB3SMENR_QSPISMEN_Pos) /*!< 0x00000100 */ 9563 #define RCC_AHB3SMENR_QSPISMEN RCC_AHB3SMENR_QSPISMEN_Msk 9564 9565 /******************** Bit definition for RCC_APB1SMENR1 register *************/ 9566 #define RCC_APB1SMENR1_TIM2SMEN_Pos (0U) 9567 #define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos) /*!< 0x00000001 */ 9568 #define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk 9569 #define RCC_APB1SMENR1_TIM6SMEN_Pos (4U) 9570 #define RCC_APB1SMENR1_TIM6SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM6SMEN_Pos) /*!< 0x00000010 */ 9571 #define RCC_APB1SMENR1_TIM6SMEN RCC_APB1SMENR1_TIM6SMEN_Msk 9572 #define RCC_APB1SMENR1_TIM7SMEN_Pos (5U) 9573 #define RCC_APB1SMENR1_TIM7SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM7SMEN_Pos) /*!< 0x00000020 */ 9574 #define RCC_APB1SMENR1_TIM7SMEN RCC_APB1SMENR1_TIM7SMEN_Msk 9575 #define RCC_APB1SMENR1_RTCAPBSMEN_Pos (10U) 9576 #define RCC_APB1SMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APB1SMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */ 9577 #define RCC_APB1SMENR1_RTCAPBSMEN RCC_APB1SMENR1_RTCAPBSMEN_Msk 9578 #define RCC_APB1SMENR1_WWDGSMEN_Pos (11U) 9579 #define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */ 9580 #define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk 9581 #define RCC_APB1SMENR1_SPI3SMEN_Pos (15U) 9582 #define RCC_APB1SMENR1_SPI3SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI3SMEN_Pos) /*!< 0x00008000 */ 9583 #define RCC_APB1SMENR1_SPI3SMEN RCC_APB1SMENR1_SPI3SMEN_Msk 9584 #define RCC_APB1SMENR1_USART2SMEN_Pos (17U) 9585 #define RCC_APB1SMENR1_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos) /*!< 0x00020000 */ 9586 #define RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk 9587 #define RCC_APB1SMENR1_I2C1SMEN_Pos (21U) 9588 #define RCC_APB1SMENR1_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */ 9589 #define RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk 9590 #define RCC_APB1SMENR1_I2C3SMEN_Pos (23U) 9591 #define RCC_APB1SMENR1_I2C3SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C3SMEN_Pos) /*!< 0x00800000 */ 9592 #define RCC_APB1SMENR1_I2C3SMEN RCC_APB1SMENR1_I2C3SMEN_Msk 9593 #define RCC_APB1SMENR1_CRSSMEN_Pos (24U) 9594 #define RCC_APB1SMENR1_CRSSMEN_Msk (0x1UL << RCC_APB1SMENR1_CRSSMEN_Pos) /*!< 0x01000000 */ 9595 #define RCC_APB1SMENR1_CRSSMEN RCC_APB1SMENR1_CRSSMEN_Msk 9596 #define RCC_APB1SMENR1_CAN1SMEN_Pos (25U) 9597 #define RCC_APB1SMENR1_CAN1SMEN_Msk (0x1UL << RCC_APB1SMENR1_CAN1SMEN_Pos) /*!< 0x02000000 */ 9598 #define RCC_APB1SMENR1_CAN1SMEN RCC_APB1SMENR1_CAN1SMEN_Msk 9599 #define RCC_APB1SMENR1_USBFSSMEN_Pos (26U) 9600 #define RCC_APB1SMENR1_USBFSSMEN_Msk (0x1UL << RCC_APB1SMENR1_USBFSSMEN_Pos) /*!< 0x04000000 */ 9601 #define RCC_APB1SMENR1_USBFSSMEN RCC_APB1SMENR1_USBFSSMEN_Msk 9602 #define RCC_APB1SMENR1_PWRSMEN_Pos (28U) 9603 #define RCC_APB1SMENR1_PWRSMEN_Msk (0x1UL << RCC_APB1SMENR1_PWRSMEN_Pos) /*!< 0x10000000 */ 9604 #define RCC_APB1SMENR1_PWRSMEN RCC_APB1SMENR1_PWRSMEN_Msk 9605 #define RCC_APB1SMENR1_DAC1SMEN_Pos (29U) 9606 #define RCC_APB1SMENR1_DAC1SMEN_Msk (0x1UL << RCC_APB1SMENR1_DAC1SMEN_Pos) /*!< 0x20000000 */ 9607 #define RCC_APB1SMENR1_DAC1SMEN RCC_APB1SMENR1_DAC1SMEN_Msk 9608 #define RCC_APB1SMENR1_OPAMPSMEN_Pos (30U) 9609 #define RCC_APB1SMENR1_OPAMPSMEN_Msk (0x1UL << RCC_APB1SMENR1_OPAMPSMEN_Pos) /*!< 0x40000000 */ 9610 #define RCC_APB1SMENR1_OPAMPSMEN RCC_APB1SMENR1_OPAMPSMEN_Msk 9611 #define RCC_APB1SMENR1_LPTIM1SMEN_Pos (31U) 9612 #define RCC_APB1SMENR1_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR1_LPTIM1SMEN_Pos) /*!< 0x80000000 */ 9613 #define RCC_APB1SMENR1_LPTIM1SMEN RCC_APB1SMENR1_LPTIM1SMEN_Msk 9614 9615 /******************** Bit definition for RCC_APB1SMENR2 register *************/ 9616 #define RCC_APB1SMENR2_LPUART1SMEN_Pos (0U) 9617 #define RCC_APB1SMENR2_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPUART1SMEN_Pos) /*!< 0x00000001 */ 9618 #define RCC_APB1SMENR2_LPUART1SMEN RCC_APB1SMENR2_LPUART1SMEN_Msk 9619 #define RCC_APB1SMENR2_SWPMI1SMEN_Pos (2U) 9620 #define RCC_APB1SMENR2_SWPMI1SMEN_Msk (0x1UL << RCC_APB1SMENR2_SWPMI1SMEN_Pos) /*!< 0x00000004 */ 9621 #define RCC_APB1SMENR2_SWPMI1SMEN RCC_APB1SMENR2_SWPMI1SMEN_Msk 9622 #define RCC_APB1SMENR2_LPTIM2SMEN_Pos (5U) 9623 #define RCC_APB1SMENR2_LPTIM2SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPTIM2SMEN_Pos) /*!< 0x00000020 */ 9624 #define RCC_APB1SMENR2_LPTIM2SMEN RCC_APB1SMENR2_LPTIM2SMEN_Msk 9625 9626 /******************** Bit definition for RCC_APB2SMENR register *************/ 9627 #define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U) 9628 #define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */ 9629 #define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk 9630 #define RCC_APB2SMENR_TIM1SMEN_Pos (11U) 9631 #define RCC_APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */ 9632 #define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk 9633 #define RCC_APB2SMENR_SPI1SMEN_Pos (12U) 9634 #define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */ 9635 #define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk 9636 #define RCC_APB2SMENR_USART1SMEN_Pos (14U) 9637 #define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */ 9638 #define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk 9639 #define RCC_APB2SMENR_TIM15SMEN_Pos (16U) 9640 #define RCC_APB2SMENR_TIM15SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM15SMEN_Pos) /*!< 0x00010000 */ 9641 #define RCC_APB2SMENR_TIM15SMEN RCC_APB2SMENR_TIM15SMEN_Msk 9642 #define RCC_APB2SMENR_TIM16SMEN_Pos (17U) 9643 #define RCC_APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */ 9644 #define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk 9645 #define RCC_APB2SMENR_SAI1SMEN_Pos (21U) 9646 #define RCC_APB2SMENR_SAI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SAI1SMEN_Pos) /*!< 0x00200000 */ 9647 #define RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk 9648 9649 /******************** Bit definition for RCC_CCIPR register ******************/ 9650 #define RCC_CCIPR_USART1SEL_Pos (0U) 9651 #define RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */ 9652 #define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk 9653 #define RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */ 9654 #define RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */ 9655 9656 #define RCC_CCIPR_USART2SEL_Pos (2U) 9657 #define RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */ 9658 #define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk 9659 #define RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */ 9660 #define RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */ 9661 9662 #define RCC_CCIPR_LPUART1SEL_Pos (10U) 9663 #define RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */ 9664 #define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk 9665 #define RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000400 */ 9666 #define RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000800 */ 9667 9668 #define RCC_CCIPR_I2C1SEL_Pos (12U) 9669 #define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */ 9670 #define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk 9671 #define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */ 9672 #define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */ 9673 9674 #define RCC_CCIPR_I2C3SEL_Pos (16U) 9675 #define RCC_CCIPR_I2C3SEL_Msk (0x3UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00030000 */ 9676 #define RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk 9677 #define RCC_CCIPR_I2C3SEL_0 (0x1UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00010000 */ 9678 #define RCC_CCIPR_I2C3SEL_1 (0x2UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00020000 */ 9679 9680 #define RCC_CCIPR_LPTIM1SEL_Pos (18U) 9681 #define RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */ 9682 #define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk 9683 #define RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */ 9684 #define RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */ 9685 9686 #define RCC_CCIPR_LPTIM2SEL_Pos (20U) 9687 #define RCC_CCIPR_LPTIM2SEL_Msk (0x3UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00300000 */ 9688 #define RCC_CCIPR_LPTIM2SEL RCC_CCIPR_LPTIM2SEL_Msk 9689 #define RCC_CCIPR_LPTIM2SEL_0 (0x1UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00100000 */ 9690 #define RCC_CCIPR_LPTIM2SEL_1 (0x2UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00200000 */ 9691 9692 #define RCC_CCIPR_SAI1SEL_Pos (22U) 9693 #define RCC_CCIPR_SAI1SEL_Msk (0x3UL << RCC_CCIPR_SAI1SEL_Pos) /*!< 0x00C00000 */ 9694 #define RCC_CCIPR_SAI1SEL RCC_CCIPR_SAI1SEL_Msk 9695 #define RCC_CCIPR_SAI1SEL_0 (0x1UL << RCC_CCIPR_SAI1SEL_Pos) /*!< 0x00400000 */ 9696 #define RCC_CCIPR_SAI1SEL_1 (0x2UL << RCC_CCIPR_SAI1SEL_Pos) /*!< 0x00800000 */ 9697 9698 #define RCC_CCIPR_CLK48SEL_Pos (26U) 9699 #define RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */ 9700 #define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk 9701 #define RCC_CCIPR_CLK48SEL_0 (0x1UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x04000000 */ 9702 #define RCC_CCIPR_CLK48SEL_1 (0x2UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x08000000 */ 9703 9704 #define RCC_CCIPR_ADCSEL_Pos (28U) 9705 #define RCC_CCIPR_ADCSEL_Msk (0x3UL << RCC_CCIPR_ADCSEL_Pos) /*!< 0x30000000 */ 9706 #define RCC_CCIPR_ADCSEL RCC_CCIPR_ADCSEL_Msk 9707 #define RCC_CCIPR_ADCSEL_0 (0x1UL << RCC_CCIPR_ADCSEL_Pos) /*!< 0x10000000 */ 9708 #define RCC_CCIPR_ADCSEL_1 (0x2UL << RCC_CCIPR_ADCSEL_Pos) /*!< 0x20000000 */ 9709 9710 #define RCC_CCIPR_SWPMI1SEL_Pos (30U) 9711 #define RCC_CCIPR_SWPMI1SEL_Msk (0x1UL << RCC_CCIPR_SWPMI1SEL_Pos) /*!< 0x40000000 */ 9712 #define RCC_CCIPR_SWPMI1SEL RCC_CCIPR_SWPMI1SEL_Msk 9713 9714 /******************** Bit definition for RCC_BDCR register ******************/ 9715 #define RCC_BDCR_LSEON_Pos (0U) 9716 #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ 9717 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk 9718 #define RCC_BDCR_LSERDY_Pos (1U) 9719 #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ 9720 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk 9721 #define RCC_BDCR_LSEBYP_Pos (2U) 9722 #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ 9723 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk 9724 9725 #define RCC_BDCR_LSEDRV_Pos (3U) 9726 #define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */ 9727 #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk 9728 #define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */ 9729 #define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ 9730 9731 #define RCC_BDCR_LSECSSON_Pos (5U) 9732 #define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */ 9733 #define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk 9734 #define RCC_BDCR_LSECSSD_Pos (6U) 9735 #define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */ 9736 #define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk 9737 9738 #define RCC_BDCR_RTCSEL_Pos (8U) 9739 #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ 9740 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk 9741 #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ 9742 #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ 9743 9744 #define RCC_BDCR_RTCEN_Pos (15U) 9745 #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ 9746 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk 9747 #define RCC_BDCR_BDRST_Pos (16U) 9748 #define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */ 9749 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk 9750 #define RCC_BDCR_LSCOEN_Pos (24U) 9751 #define RCC_BDCR_LSCOEN_Msk (0x1UL << RCC_BDCR_LSCOEN_Pos) /*!< 0x01000000 */ 9752 #define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk 9753 #define RCC_BDCR_LSCOSEL_Pos (25U) 9754 #define RCC_BDCR_LSCOSEL_Msk (0x1UL << RCC_BDCR_LSCOSEL_Pos) /*!< 0x02000000 */ 9755 #define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk 9756 9757 /******************** Bit definition for RCC_CSR register *******************/ 9758 #define RCC_CSR_LSION_Pos (0U) 9759 #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ 9760 #define RCC_CSR_LSION RCC_CSR_LSION_Msk 9761 #define RCC_CSR_LSIRDY_Pos (1U) 9762 #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ 9763 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk 9764 9765 #define RCC_CSR_MSISRANGE_Pos (8U) 9766 #define RCC_CSR_MSISRANGE_Msk (0xFUL << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000F00 */ 9767 #define RCC_CSR_MSISRANGE RCC_CSR_MSISRANGE_Msk 9768 #define RCC_CSR_MSISRANGE_1 (0x4UL << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000400 */ 9769 #define RCC_CSR_MSISRANGE_2 (0x5UL << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000500 */ 9770 #define RCC_CSR_MSISRANGE_4 (0x6UL << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000600 */ 9771 #define RCC_CSR_MSISRANGE_8 (0x7UL << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000700 */ 9772 9773 #define RCC_CSR_RMVF_Pos (23U) 9774 #define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */ 9775 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk 9776 #define RCC_CSR_FWRSTF_Pos (24U) 9777 #define RCC_CSR_FWRSTF_Msk (0x1UL << RCC_CSR_FWRSTF_Pos) /*!< 0x01000000 */ 9778 #define RCC_CSR_FWRSTF RCC_CSR_FWRSTF_Msk 9779 #define RCC_CSR_OBLRSTF_Pos (25U) 9780 #define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */ 9781 #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk 9782 #define RCC_CSR_PINRSTF_Pos (26U) 9783 #define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ 9784 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk 9785 #define RCC_CSR_BORRSTF_Pos (27U) 9786 #define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos) /*!< 0x08000000 */ 9787 #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk 9788 #define RCC_CSR_SFTRSTF_Pos (28U) 9789 #define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ 9790 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk 9791 #define RCC_CSR_IWDGRSTF_Pos (29U) 9792 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ 9793 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk 9794 #define RCC_CSR_WWDGRSTF_Pos (30U) 9795 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ 9796 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk 9797 #define RCC_CSR_LPWRRSTF_Pos (31U) 9798 #define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ 9799 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk 9800 9801 /******************** Bit definition for RCC_CRRCR register *****************/ 9802 #define RCC_CRRCR_HSI48ON_Pos (0U) 9803 #define RCC_CRRCR_HSI48ON_Msk (0x1UL << RCC_CRRCR_HSI48ON_Pos) /*!< 0x00000001 */ 9804 #define RCC_CRRCR_HSI48ON RCC_CRRCR_HSI48ON_Msk 9805 #define RCC_CRRCR_HSI48RDY_Pos (1U) 9806 #define RCC_CRRCR_HSI48RDY_Msk (0x1UL << RCC_CRRCR_HSI48RDY_Pos) /*!< 0x00000002 */ 9807 #define RCC_CRRCR_HSI48RDY RCC_CRRCR_HSI48RDY_Msk 9808 9809 /*!< HSI48CAL configuration */ 9810 #define RCC_CRRCR_HSI48CAL_Pos (7U) 9811 #define RCC_CRRCR_HSI48CAL_Msk (0x1FFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x0000FF80 */ 9812 #define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI48CAL[8:0] bits */ 9813 #define RCC_CRRCR_HSI48CAL_0 (0x001UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */ 9814 #define RCC_CRRCR_HSI48CAL_1 (0x002UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */ 9815 #define RCC_CRRCR_HSI48CAL_2 (0x004UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */ 9816 #define RCC_CRRCR_HSI48CAL_3 (0x008UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000400 */ 9817 #define RCC_CRRCR_HSI48CAL_4 (0x010UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000800 */ 9818 #define RCC_CRRCR_HSI48CAL_5 (0x020UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00001000 */ 9819 #define RCC_CRRCR_HSI48CAL_6 (0x040UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00002000 */ 9820 #define RCC_CRRCR_HSI48CAL_7 (0x080UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00004000 */ 9821 #define RCC_CRRCR_HSI48CAL_8 (0x100UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00008000 */ 9822 9823 /******************************************************************************/ 9824 /* */ 9825 /* RNG */ 9826 /* */ 9827 /******************************************************************************/ 9828 /******************** Bits definition for RNG_CR register *******************/ 9829 #define RNG_CR_RNGEN_Pos (2U) 9830 #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ 9831 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk 9832 #define RNG_CR_IE_Pos (3U) 9833 #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ 9834 #define RNG_CR_IE RNG_CR_IE_Msk 9835 9836 /******************** Bits definition for RNG_SR register *******************/ 9837 #define RNG_SR_DRDY_Pos (0U) 9838 #define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ 9839 #define RNG_SR_DRDY RNG_SR_DRDY_Msk 9840 #define RNG_SR_CECS_Pos (1U) 9841 #define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ 9842 #define RNG_SR_CECS RNG_SR_CECS_Msk 9843 #define RNG_SR_SECS_Pos (2U) 9844 #define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ 9845 #define RNG_SR_SECS RNG_SR_SECS_Msk 9846 #define RNG_SR_CEIS_Pos (5U) 9847 #define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ 9848 #define RNG_SR_CEIS RNG_SR_CEIS_Msk 9849 #define RNG_SR_SEIS_Pos (6U) 9850 #define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ 9851 #define RNG_SR_SEIS RNG_SR_SEIS_Msk 9852 9853 /******************************************************************************/ 9854 /* */ 9855 /* Real-Time Clock (RTC) */ 9856 /* */ 9857 /******************************************************************************/ 9858 /* 9859 * @brief Specific device feature definitions 9860 */ 9861 #define RTC_TAMPER2_SUPPORT 9862 9863 #define RTC_WAKEUP_SUPPORT 9864 #define RTC_BACKUP_SUPPORT 9865 /******************** Number of backup registers ******************************/ 9866 #define RTC_BKP_NUMBER 32U 9867 9868 9869 /******************** Bits definition for RTC_TR register *******************/ 9870 #define RTC_TR_PM_Pos (22U) 9871 #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ 9872 #define RTC_TR_PM RTC_TR_PM_Msk 9873 #define RTC_TR_HT_Pos (20U) 9874 #define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ 9875 #define RTC_TR_HT RTC_TR_HT_Msk 9876 #define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ 9877 #define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ 9878 #define RTC_TR_HU_Pos (16U) 9879 #define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ 9880 #define RTC_TR_HU RTC_TR_HU_Msk 9881 #define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ 9882 #define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ 9883 #define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ 9884 #define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ 9885 #define RTC_TR_MNT_Pos (12U) 9886 #define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ 9887 #define RTC_TR_MNT RTC_TR_MNT_Msk 9888 #define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ 9889 #define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ 9890 #define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ 9891 #define RTC_TR_MNU_Pos (8U) 9892 #define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ 9893 #define RTC_TR_MNU RTC_TR_MNU_Msk 9894 #define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ 9895 #define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ 9896 #define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ 9897 #define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ 9898 #define RTC_TR_ST_Pos (4U) 9899 #define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ 9900 #define RTC_TR_ST RTC_TR_ST_Msk 9901 #define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ 9902 #define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ 9903 #define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ 9904 #define RTC_TR_SU_Pos (0U) 9905 #define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ 9906 #define RTC_TR_SU RTC_TR_SU_Msk 9907 #define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ 9908 #define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ 9909 #define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ 9910 #define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ 9911 9912 /******************** Bits definition for RTC_DR register *******************/ 9913 #define RTC_DR_YT_Pos (20U) 9914 #define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ 9915 #define RTC_DR_YT RTC_DR_YT_Msk 9916 #define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ 9917 #define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ 9918 #define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ 9919 #define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ 9920 #define RTC_DR_YU_Pos (16U) 9921 #define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ 9922 #define RTC_DR_YU RTC_DR_YU_Msk 9923 #define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ 9924 #define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ 9925 #define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ 9926 #define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ 9927 #define RTC_DR_WDU_Pos (13U) 9928 #define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ 9929 #define RTC_DR_WDU RTC_DR_WDU_Msk 9930 #define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ 9931 #define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ 9932 #define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ 9933 #define RTC_DR_MT_Pos (12U) 9934 #define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ 9935 #define RTC_DR_MT RTC_DR_MT_Msk 9936 #define RTC_DR_MU_Pos (8U) 9937 #define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ 9938 #define RTC_DR_MU RTC_DR_MU_Msk 9939 #define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ 9940 #define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ 9941 #define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ 9942 #define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ 9943 #define RTC_DR_DT_Pos (4U) 9944 #define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ 9945 #define RTC_DR_DT RTC_DR_DT_Msk 9946 #define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ 9947 #define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ 9948 #define RTC_DR_DU_Pos (0U) 9949 #define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ 9950 #define RTC_DR_DU RTC_DR_DU_Msk 9951 #define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ 9952 #define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ 9953 #define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ 9954 #define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ 9955 9956 /******************** Bits definition for RTC_CR register *******************/ 9957 #define RTC_CR_ITSE_Pos (24U) 9958 #define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */ 9959 #define RTC_CR_ITSE RTC_CR_ITSE_Msk 9960 #define RTC_CR_COE_Pos (23U) 9961 #define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ 9962 #define RTC_CR_COE RTC_CR_COE_Msk 9963 #define RTC_CR_OSEL_Pos (21U) 9964 #define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ 9965 #define RTC_CR_OSEL RTC_CR_OSEL_Msk 9966 #define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ 9967 #define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ 9968 #define RTC_CR_POL_Pos (20U) 9969 #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ 9970 #define RTC_CR_POL RTC_CR_POL_Msk 9971 #define RTC_CR_COSEL_Pos (19U) 9972 #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ 9973 #define RTC_CR_COSEL RTC_CR_COSEL_Msk 9974 #define RTC_CR_BKP_Pos (18U) 9975 #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ 9976 #define RTC_CR_BKP RTC_CR_BKP_Msk 9977 #define RTC_CR_SUB1H_Pos (17U) 9978 #define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ 9979 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk 9980 #define RTC_CR_ADD1H_Pos (16U) 9981 #define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ 9982 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk 9983 #define RTC_CR_TSIE_Pos (15U) 9984 #define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ 9985 #define RTC_CR_TSIE RTC_CR_TSIE_Msk 9986 #define RTC_CR_WUTIE_Pos (14U) 9987 #define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ 9988 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk 9989 #define RTC_CR_ALRBIE_Pos (13U) 9990 #define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ 9991 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk 9992 #define RTC_CR_ALRAIE_Pos (12U) 9993 #define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ 9994 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk 9995 #define RTC_CR_TSE_Pos (11U) 9996 #define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ 9997 #define RTC_CR_TSE RTC_CR_TSE_Msk 9998 #define RTC_CR_WUTE_Pos (10U) 9999 #define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ 10000 #define RTC_CR_WUTE RTC_CR_WUTE_Msk 10001 #define RTC_CR_ALRBE_Pos (9U) 10002 #define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ 10003 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk 10004 #define RTC_CR_ALRAE_Pos (8U) 10005 #define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ 10006 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk 10007 #define RTC_CR_FMT_Pos (6U) 10008 #define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ 10009 #define RTC_CR_FMT RTC_CR_FMT_Msk 10010 #define RTC_CR_BYPSHAD_Pos (5U) 10011 #define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ 10012 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk 10013 #define RTC_CR_REFCKON_Pos (4U) 10014 #define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ 10015 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk 10016 #define RTC_CR_TSEDGE_Pos (3U) 10017 #define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ 10018 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk 10019 #define RTC_CR_WUCKSEL_Pos (0U) 10020 #define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ 10021 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk 10022 #define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ 10023 #define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ 10024 #define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ 10025 10026 /* Legacy defines */ 10027 #define RTC_CR_BCK_Pos RTC_CR_BKP_Pos 10028 #define RTC_CR_BCK_Msk RTC_CR_BKP_Msk 10029 #define RTC_CR_BCK RTC_CR_BKP 10030 10031 /******************** Bits definition for RTC_ISR register ******************/ 10032 #define RTC_ISR_ITSF_Pos (17U) 10033 #define RTC_ISR_ITSF_Msk (0x1UL << RTC_ISR_ITSF_Pos) /*!< 0x00020000 */ 10034 #define RTC_ISR_ITSF RTC_ISR_ITSF_Msk 10035 #define RTC_ISR_RECALPF_Pos (16U) 10036 #define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ 10037 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk 10038 #define RTC_ISR_TAMP2F_Pos (14U) 10039 #define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */ 10040 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk 10041 #define RTC_ISR_TSOVF_Pos (12U) 10042 #define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */ 10043 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk 10044 #define RTC_ISR_TSF_Pos (11U) 10045 #define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */ 10046 #define RTC_ISR_TSF RTC_ISR_TSF_Msk 10047 #define RTC_ISR_WUTF_Pos (10U) 10048 #define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */ 10049 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk 10050 #define RTC_ISR_ALRBF_Pos (9U) 10051 #define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */ 10052 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk 10053 #define RTC_ISR_ALRAF_Pos (8U) 10054 #define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */ 10055 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk 10056 #define RTC_ISR_INIT_Pos (7U) 10057 #define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ 10058 #define RTC_ISR_INIT RTC_ISR_INIT_Msk 10059 #define RTC_ISR_INITF_Pos (6U) 10060 #define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ 10061 #define RTC_ISR_INITF RTC_ISR_INITF_Msk 10062 #define RTC_ISR_RSF_Pos (5U) 10063 #define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ 10064 #define RTC_ISR_RSF RTC_ISR_RSF_Msk 10065 #define RTC_ISR_INITS_Pos (4U) 10066 #define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ 10067 #define RTC_ISR_INITS RTC_ISR_INITS_Msk 10068 #define RTC_ISR_SHPF_Pos (3U) 10069 #define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ 10070 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk 10071 #define RTC_ISR_WUTWF_Pos (2U) 10072 #define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ 10073 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk 10074 #define RTC_ISR_ALRBWF_Pos (1U) 10075 #define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ 10076 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk 10077 #define RTC_ISR_ALRAWF_Pos (0U) 10078 #define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ 10079 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk 10080 10081 /******************** Bits definition for RTC_PRER register *****************/ 10082 #define RTC_PRER_PREDIV_A_Pos (16U) 10083 #define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ 10084 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk 10085 #define RTC_PRER_PREDIV_S_Pos (0U) 10086 #define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ 10087 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk 10088 10089 /******************** Bits definition for RTC_WUTR register *****************/ 10090 #define RTC_WUTR_WUT_Pos (0U) 10091 #define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ 10092 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk 10093 10094 /******************** Bits definition for RTC_ALRMAR register ***************/ 10095 #define RTC_ALRMAR_MSK4_Pos (31U) 10096 #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ 10097 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk 10098 #define RTC_ALRMAR_WDSEL_Pos (30U) 10099 #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ 10100 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk 10101 #define RTC_ALRMAR_DT_Pos (28U) 10102 #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ 10103 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk 10104 #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ 10105 #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ 10106 #define RTC_ALRMAR_DU_Pos (24U) 10107 #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ 10108 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk 10109 #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ 10110 #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ 10111 #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ 10112 #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ 10113 #define RTC_ALRMAR_MSK3_Pos (23U) 10114 #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ 10115 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk 10116 #define RTC_ALRMAR_PM_Pos (22U) 10117 #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ 10118 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk 10119 #define RTC_ALRMAR_HT_Pos (20U) 10120 #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ 10121 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk 10122 #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ 10123 #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ 10124 #define RTC_ALRMAR_HU_Pos (16U) 10125 #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ 10126 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk 10127 #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ 10128 #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ 10129 #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ 10130 #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ 10131 #define RTC_ALRMAR_MSK2_Pos (15U) 10132 #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ 10133 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk 10134 #define RTC_ALRMAR_MNT_Pos (12U) 10135 #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ 10136 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk 10137 #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ 10138 #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ 10139 #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ 10140 #define RTC_ALRMAR_MNU_Pos (8U) 10141 #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ 10142 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk 10143 #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ 10144 #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ 10145 #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ 10146 #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ 10147 #define RTC_ALRMAR_MSK1_Pos (7U) 10148 #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ 10149 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk 10150 #define RTC_ALRMAR_ST_Pos (4U) 10151 #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ 10152 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk 10153 #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ 10154 #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ 10155 #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ 10156 #define RTC_ALRMAR_SU_Pos (0U) 10157 #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ 10158 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk 10159 #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ 10160 #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ 10161 #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ 10162 #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ 10163 10164 /******************** Bits definition for RTC_ALRMBR register ***************/ 10165 #define RTC_ALRMBR_MSK4_Pos (31U) 10166 #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ 10167 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk 10168 #define RTC_ALRMBR_WDSEL_Pos (30U) 10169 #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ 10170 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk 10171 #define RTC_ALRMBR_DT_Pos (28U) 10172 #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ 10173 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk 10174 #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ 10175 #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ 10176 #define RTC_ALRMBR_DU_Pos (24U) 10177 #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ 10178 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk 10179 #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ 10180 #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ 10181 #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ 10182 #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ 10183 #define RTC_ALRMBR_MSK3_Pos (23U) 10184 #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ 10185 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk 10186 #define RTC_ALRMBR_PM_Pos (22U) 10187 #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ 10188 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk 10189 #define RTC_ALRMBR_HT_Pos (20U) 10190 #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ 10191 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk 10192 #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ 10193 #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ 10194 #define RTC_ALRMBR_HU_Pos (16U) 10195 #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ 10196 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk 10197 #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ 10198 #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ 10199 #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ 10200 #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ 10201 #define RTC_ALRMBR_MSK2_Pos (15U) 10202 #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ 10203 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk 10204 #define RTC_ALRMBR_MNT_Pos (12U) 10205 #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ 10206 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk 10207 #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ 10208 #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ 10209 #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ 10210 #define RTC_ALRMBR_MNU_Pos (8U) 10211 #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ 10212 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk 10213 #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ 10214 #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ 10215 #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ 10216 #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ 10217 #define RTC_ALRMBR_MSK1_Pos (7U) 10218 #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ 10219 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk 10220 #define RTC_ALRMBR_ST_Pos (4U) 10221 #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ 10222 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk 10223 #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ 10224 #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ 10225 #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ 10226 #define RTC_ALRMBR_SU_Pos (0U) 10227 #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ 10228 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk 10229 #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ 10230 #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ 10231 #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ 10232 #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ 10233 10234 /******************** Bits definition for RTC_WPR register ******************/ 10235 #define RTC_WPR_KEY_Pos (0U) 10236 #define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ 10237 #define RTC_WPR_KEY RTC_WPR_KEY_Msk 10238 10239 /******************** Bits definition for RTC_SSR register ******************/ 10240 #define RTC_SSR_SS_Pos (0U) 10241 #define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */ 10242 #define RTC_SSR_SS RTC_SSR_SS_Msk 10243 10244 /******************** Bits definition for RTC_SHIFTR register ***************/ 10245 #define RTC_SHIFTR_SUBFS_Pos (0U) 10246 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ 10247 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk 10248 #define RTC_SHIFTR_ADD1S_Pos (31U) 10249 #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ 10250 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk 10251 10252 /******************** Bits definition for RTC_TSTR register *****************/ 10253 #define RTC_TSTR_PM_Pos (22U) 10254 #define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ 10255 #define RTC_TSTR_PM RTC_TSTR_PM_Msk 10256 #define RTC_TSTR_HT_Pos (20U) 10257 #define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ 10258 #define RTC_TSTR_HT RTC_TSTR_HT_Msk 10259 #define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ 10260 #define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ 10261 #define RTC_TSTR_HU_Pos (16U) 10262 #define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ 10263 #define RTC_TSTR_HU RTC_TSTR_HU_Msk 10264 #define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ 10265 #define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ 10266 #define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ 10267 #define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ 10268 #define RTC_TSTR_MNT_Pos (12U) 10269 #define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ 10270 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk 10271 #define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ 10272 #define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ 10273 #define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ 10274 #define RTC_TSTR_MNU_Pos (8U) 10275 #define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ 10276 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk 10277 #define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ 10278 #define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ 10279 #define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ 10280 #define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ 10281 #define RTC_TSTR_ST_Pos (4U) 10282 #define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ 10283 #define RTC_TSTR_ST RTC_TSTR_ST_Msk 10284 #define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ 10285 #define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ 10286 #define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ 10287 #define RTC_TSTR_SU_Pos (0U) 10288 #define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ 10289 #define RTC_TSTR_SU RTC_TSTR_SU_Msk 10290 #define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ 10291 #define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ 10292 #define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ 10293 #define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ 10294 10295 /******************** Bits definition for RTC_TSDR register *****************/ 10296 #define RTC_TSDR_WDU_Pos (13U) 10297 #define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ 10298 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk 10299 #define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ 10300 #define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ 10301 #define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ 10302 #define RTC_TSDR_MT_Pos (12U) 10303 #define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ 10304 #define RTC_TSDR_MT RTC_TSDR_MT_Msk 10305 #define RTC_TSDR_MU_Pos (8U) 10306 #define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ 10307 #define RTC_TSDR_MU RTC_TSDR_MU_Msk 10308 #define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ 10309 #define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ 10310 #define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ 10311 #define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ 10312 #define RTC_TSDR_DT_Pos (4U) 10313 #define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ 10314 #define RTC_TSDR_DT RTC_TSDR_DT_Msk 10315 #define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ 10316 #define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ 10317 #define RTC_TSDR_DU_Pos (0U) 10318 #define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ 10319 #define RTC_TSDR_DU RTC_TSDR_DU_Msk 10320 #define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ 10321 #define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ 10322 #define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ 10323 #define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ 10324 10325 /******************** Bits definition for RTC_TSSSR register ****************/ 10326 #define RTC_TSSSR_SS_Pos (0U) 10327 #define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ 10328 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk 10329 10330 /******************** Bits definition for RTC_CAL register *****************/ 10331 #define RTC_CALR_CALP_Pos (15U) 10332 #define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ 10333 #define RTC_CALR_CALP RTC_CALR_CALP_Msk 10334 #define RTC_CALR_CALW8_Pos (14U) 10335 #define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ 10336 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk 10337 #define RTC_CALR_CALW16_Pos (13U) 10338 #define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ 10339 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk 10340 #define RTC_CALR_CALM_Pos (0U) 10341 #define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ 10342 #define RTC_CALR_CALM RTC_CALR_CALM_Msk 10343 #define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ 10344 #define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ 10345 #define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ 10346 #define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ 10347 #define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ 10348 #define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ 10349 #define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ 10350 #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ 10351 #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ 10352 10353 /******************** Bits definition for RTC_TAMPCR register ***************/ 10354 #define RTC_TAMPCR_TAMP2MF_Pos (21U) 10355 #define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */ 10356 #define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk 10357 #define RTC_TAMPCR_TAMP2NOERASE_Pos (20U) 10358 #define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */ 10359 #define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk 10360 #define RTC_TAMPCR_TAMP2IE_Pos (19U) 10361 #define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */ 10362 #define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk 10363 #define RTC_TAMPCR_TAMPPUDIS_Pos (15U) 10364 #define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ 10365 #define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk 10366 #define RTC_TAMPCR_TAMPPRCH_Pos (13U) 10367 #define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */ 10368 #define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk 10369 #define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */ 10370 #define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */ 10371 #define RTC_TAMPCR_TAMPFLT_Pos (11U) 10372 #define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */ 10373 #define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk 10374 #define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */ 10375 #define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */ 10376 #define RTC_TAMPCR_TAMPFREQ_Pos (8U) 10377 #define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */ 10378 #define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk 10379 #define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */ 10380 #define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */ 10381 #define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */ 10382 #define RTC_TAMPCR_TAMPTS_Pos (7U) 10383 #define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */ 10384 #define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk 10385 #define RTC_TAMPCR_TAMP2TRG_Pos (4U) 10386 #define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */ 10387 #define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk 10388 #define RTC_TAMPCR_TAMP2E_Pos (3U) 10389 #define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */ 10390 #define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk 10391 #define RTC_TAMPCR_TAMPIE_Pos (2U) 10392 #define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */ 10393 #define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk 10394 10395 /******************** Bits definition for RTC_ALRMASSR register *************/ 10396 #define RTC_ALRMASSR_MASKSS_Pos (24U) 10397 #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ 10398 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk 10399 #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ 10400 #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ 10401 #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ 10402 #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ 10403 #define RTC_ALRMASSR_SS_Pos (0U) 10404 #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ 10405 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk 10406 10407 /******************** Bits definition for RTC_ALRMBSSR register *************/ 10408 #define RTC_ALRMBSSR_MASKSS_Pos (24U) 10409 #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ 10410 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk 10411 #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ 10412 #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ 10413 #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ 10414 #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ 10415 #define RTC_ALRMBSSR_SS_Pos (0U) 10416 #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ 10417 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk 10418 10419 /******************** Bits definition for RTC_0R register *******************/ 10420 #define RTC_OR_OUT_RMP_Pos (1U) 10421 #define RTC_OR_OUT_RMP_Msk (0x1UL << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */ 10422 #define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk 10423 #define RTC_OR_ALARMOUTTYPE_Pos (0U) 10424 #define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */ 10425 #define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk 10426 10427 10428 /******************** Bits definition for RTC_BKP0R register ****************/ 10429 #define RTC_BKP0R_Pos (0U) 10430 #define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */ 10431 #define RTC_BKP0R RTC_BKP0R_Msk 10432 10433 /******************** Bits definition for RTC_BKP1R register ****************/ 10434 #define RTC_BKP1R_Pos (0U) 10435 #define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */ 10436 #define RTC_BKP1R RTC_BKP1R_Msk 10437 10438 /******************** Bits definition for RTC_BKP2R register ****************/ 10439 #define RTC_BKP2R_Pos (0U) 10440 #define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */ 10441 #define RTC_BKP2R RTC_BKP2R_Msk 10442 10443 /******************** Bits definition for RTC_BKP3R register ****************/ 10444 #define RTC_BKP3R_Pos (0U) 10445 #define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */ 10446 #define RTC_BKP3R RTC_BKP3R_Msk 10447 10448 /******************** Bits definition for RTC_BKP4R register ****************/ 10449 #define RTC_BKP4R_Pos (0U) 10450 #define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */ 10451 #define RTC_BKP4R RTC_BKP4R_Msk 10452 10453 /******************** Bits definition for RTC_BKP5R register ****************/ 10454 #define RTC_BKP5R_Pos (0U) 10455 #define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */ 10456 #define RTC_BKP5R RTC_BKP5R_Msk 10457 10458 /******************** Bits definition for RTC_BKP6R register ****************/ 10459 #define RTC_BKP6R_Pos (0U) 10460 #define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */ 10461 #define RTC_BKP6R RTC_BKP6R_Msk 10462 10463 /******************** Bits definition for RTC_BKP7R register ****************/ 10464 #define RTC_BKP7R_Pos (0U) 10465 #define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */ 10466 #define RTC_BKP7R RTC_BKP7R_Msk 10467 10468 /******************** Bits definition for RTC_BKP8R register ****************/ 10469 #define RTC_BKP8R_Pos (0U) 10470 #define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */ 10471 #define RTC_BKP8R RTC_BKP8R_Msk 10472 10473 /******************** Bits definition for RTC_BKP9R register ****************/ 10474 #define RTC_BKP9R_Pos (0U) 10475 #define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */ 10476 #define RTC_BKP9R RTC_BKP9R_Msk 10477 10478 /******************** Bits definition for RTC_BKP10R register ***************/ 10479 #define RTC_BKP10R_Pos (0U) 10480 #define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */ 10481 #define RTC_BKP10R RTC_BKP10R_Msk 10482 10483 /******************** Bits definition for RTC_BKP11R register ***************/ 10484 #define RTC_BKP11R_Pos (0U) 10485 #define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */ 10486 #define RTC_BKP11R RTC_BKP11R_Msk 10487 10488 /******************** Bits definition for RTC_BKP12R register ***************/ 10489 #define RTC_BKP12R_Pos (0U) 10490 #define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */ 10491 #define RTC_BKP12R RTC_BKP12R_Msk 10492 10493 /******************** Bits definition for RTC_BKP13R register ***************/ 10494 #define RTC_BKP13R_Pos (0U) 10495 #define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */ 10496 #define RTC_BKP13R RTC_BKP13R_Msk 10497 10498 /******************** Bits definition for RTC_BKP14R register ***************/ 10499 #define RTC_BKP14R_Pos (0U) 10500 #define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */ 10501 #define RTC_BKP14R RTC_BKP14R_Msk 10502 10503 /******************** Bits definition for RTC_BKP15R register ***************/ 10504 #define RTC_BKP15R_Pos (0U) 10505 #define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */ 10506 #define RTC_BKP15R RTC_BKP15R_Msk 10507 10508 /******************** Bits definition for RTC_BKP16R register ***************/ 10509 #define RTC_BKP16R_Pos (0U) 10510 #define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */ 10511 #define RTC_BKP16R RTC_BKP16R_Msk 10512 10513 /******************** Bits definition for RTC_BKP17R register ***************/ 10514 #define RTC_BKP17R_Pos (0U) 10515 #define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */ 10516 #define RTC_BKP17R RTC_BKP17R_Msk 10517 10518 /******************** Bits definition for RTC_BKP18R register ***************/ 10519 #define RTC_BKP18R_Pos (0U) 10520 #define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */ 10521 #define RTC_BKP18R RTC_BKP18R_Msk 10522 10523 /******************** Bits definition for RTC_BKP19R register ***************/ 10524 #define RTC_BKP19R_Pos (0U) 10525 #define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */ 10526 #define RTC_BKP19R RTC_BKP19R_Msk 10527 10528 /******************** Bits definition for RTC_BKP20R register ***************/ 10529 #define RTC_BKP20R_Pos (0U) 10530 #define RTC_BKP20R_Msk (0xFFFFFFFFUL << RTC_BKP20R_Pos) /*!< 0xFFFFFFFF */ 10531 #define RTC_BKP20R RTC_BKP20R_Msk 10532 10533 /******************** Bits definition for RTC_BKP21R register ***************/ 10534 #define RTC_BKP21R_Pos (0U) 10535 #define RTC_BKP21R_Msk (0xFFFFFFFFUL << RTC_BKP21R_Pos) /*!< 0xFFFFFFFF */ 10536 #define RTC_BKP21R RTC_BKP21R_Msk 10537 10538 /******************** Bits definition for RTC_BKP22R register ***************/ 10539 #define RTC_BKP22R_Pos (0U) 10540 #define RTC_BKP22R_Msk (0xFFFFFFFFUL << RTC_BKP22R_Pos) /*!< 0xFFFFFFFF */ 10541 #define RTC_BKP22R RTC_BKP22R_Msk 10542 10543 /******************** Bits definition for RTC_BKP23R register ***************/ 10544 #define RTC_BKP23R_Pos (0U) 10545 #define RTC_BKP23R_Msk (0xFFFFFFFFUL << RTC_BKP23R_Pos) /*!< 0xFFFFFFFF */ 10546 #define RTC_BKP23R RTC_BKP23R_Msk 10547 10548 /******************** Bits definition for RTC_BKP24R register ***************/ 10549 #define RTC_BKP24R_Pos (0U) 10550 #define RTC_BKP24R_Msk (0xFFFFFFFFUL << RTC_BKP24R_Pos) /*!< 0xFFFFFFFF */ 10551 #define RTC_BKP24R RTC_BKP24R_Msk 10552 10553 /******************** Bits definition for RTC_BKP25R register ***************/ 10554 #define RTC_BKP25R_Pos (0U) 10555 #define RTC_BKP25R_Msk (0xFFFFFFFFUL << RTC_BKP25R_Pos) /*!< 0xFFFFFFFF */ 10556 #define RTC_BKP25R RTC_BKP25R_Msk 10557 10558 /******************** Bits definition for RTC_BKP26R register ***************/ 10559 #define RTC_BKP26R_Pos (0U) 10560 #define RTC_BKP26R_Msk (0xFFFFFFFFUL << RTC_BKP26R_Pos) /*!< 0xFFFFFFFF */ 10561 #define RTC_BKP26R RTC_BKP26R_Msk 10562 10563 /******************** Bits definition for RTC_BKP27R register ***************/ 10564 #define RTC_BKP27R_Pos (0U) 10565 #define RTC_BKP27R_Msk (0xFFFFFFFFUL << RTC_BKP27R_Pos) /*!< 0xFFFFFFFF */ 10566 #define RTC_BKP27R RTC_BKP27R_Msk 10567 10568 /******************** Bits definition for RTC_BKP28R register ***************/ 10569 #define RTC_BKP28R_Pos (0U) 10570 #define RTC_BKP28R_Msk (0xFFFFFFFFUL << RTC_BKP28R_Pos) /*!< 0xFFFFFFFF */ 10571 #define RTC_BKP28R RTC_BKP28R_Msk 10572 10573 /******************** Bits definition for RTC_BKP29R register ***************/ 10574 #define RTC_BKP29R_Pos (0U) 10575 #define RTC_BKP29R_Msk (0xFFFFFFFFUL << RTC_BKP29R_Pos) /*!< 0xFFFFFFFF */ 10576 #define RTC_BKP29R RTC_BKP29R_Msk 10577 10578 /******************** Bits definition for RTC_BKP30R register ***************/ 10579 #define RTC_BKP30R_Pos (0U) 10580 #define RTC_BKP30R_Msk (0xFFFFFFFFUL << RTC_BKP30R_Pos) /*!< 0xFFFFFFFF */ 10581 #define RTC_BKP30R RTC_BKP30R_Msk 10582 10583 /******************** Bits definition for RTC_BKP31R register ***************/ 10584 #define RTC_BKP31R_Pos (0U) 10585 #define RTC_BKP31R_Msk (0xFFFFFFFFUL << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */ 10586 #define RTC_BKP31R RTC_BKP31R_Msk 10587 10588 /******************************************************************************/ 10589 /* */ 10590 /* Serial Audio Interface */ 10591 /* */ 10592 /******************************************************************************/ 10593 /******************** Bit definition for SAI_GCR register *******************/ 10594 #define SAI_GCR_SYNCIN_Pos (0U) 10595 #define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */ 10596 #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */ 10597 #define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */ 10598 #define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */ 10599 10600 #define SAI_GCR_SYNCOUT_Pos (4U) 10601 #define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */ 10602 #define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */ 10603 #define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */ 10604 #define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */ 10605 10606 /******************* Bit definition for SAI_xCR1 register *******************/ 10607 #define SAI_xCR1_MODE_Pos (0U) 10608 #define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */ 10609 #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */ 10610 #define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */ 10611 #define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */ 10612 10613 #define SAI_xCR1_PRTCFG_Pos (2U) 10614 #define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */ 10615 #define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */ 10616 #define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */ 10617 #define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */ 10618 10619 #define SAI_xCR1_DS_Pos (5U) 10620 #define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */ 10621 #define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */ 10622 #define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos) /*!< 0x00000020 */ 10623 #define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos) /*!< 0x00000040 */ 10624 #define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos) /*!< 0x00000080 */ 10625 10626 #define SAI_xCR1_LSBFIRST_Pos (8U) 10627 #define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */ 10628 #define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */ 10629 #define SAI_xCR1_CKSTR_Pos (9U) 10630 #define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */ 10631 #define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */ 10632 10633 #define SAI_xCR1_SYNCEN_Pos (10U) 10634 #define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */ 10635 #define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */ 10636 #define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */ 10637 #define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */ 10638 10639 #define SAI_xCR1_MONO_Pos (12U) 10640 #define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */ 10641 #define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */ 10642 #define SAI_xCR1_OUTDRIV_Pos (13U) 10643 #define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */ 10644 #define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */ 10645 #define SAI_xCR1_SAIEN_Pos (16U) 10646 #define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */ 10647 #define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */ 10648 #define SAI_xCR1_DMAEN_Pos (17U) 10649 #define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */ 10650 #define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */ 10651 #define SAI_xCR1_NODIV_Pos (19U) 10652 #define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */ 10653 #define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */ 10654 10655 #define SAI_xCR1_MCKDIV_Pos (20U) 10656 #define SAI_xCR1_MCKDIV_Msk (0xFUL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00F00000 */ 10657 #define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[3:0] (Master ClocK Divider) */ 10658 #define SAI_xCR1_MCKDIV_0 (0x1UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00100000 */ 10659 #define SAI_xCR1_MCKDIV_1 (0x2UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00200000 */ 10660 #define SAI_xCR1_MCKDIV_2 (0x4UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00400000 */ 10661 #define SAI_xCR1_MCKDIV_3 (0x8UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00800000 */ 10662 10663 /******************* Bit definition for SAI_xCR2 register *******************/ 10664 #define SAI_xCR2_FTH_Pos (0U) 10665 #define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */ 10666 #define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */ 10667 #define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */ 10668 #define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */ 10669 #define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */ 10670 10671 #define SAI_xCR2_FFLUSH_Pos (3U) 10672 #define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */ 10673 #define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */ 10674 #define SAI_xCR2_TRIS_Pos (4U) 10675 #define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */ 10676 #define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */ 10677 #define SAI_xCR2_MUTE_Pos (5U) 10678 #define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */ 10679 #define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */ 10680 #define SAI_xCR2_MUTEVAL_Pos (6U) 10681 #define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */ 10682 #define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */ 10683 10684 10685 #define SAI_xCR2_MUTECNT_Pos (7U) 10686 #define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */ 10687 #define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */ 10688 #define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */ 10689 #define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */ 10690 #define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */ 10691 #define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */ 10692 #define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */ 10693 #define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */ 10694 10695 #define SAI_xCR2_CPL_Pos (13U) 10696 #define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */ 10697 #define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!<CPL mode */ 10698 #define SAI_xCR2_COMP_Pos (14U) 10699 #define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */ 10700 #define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */ 10701 #define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */ 10702 #define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */ 10703 10704 10705 /****************** Bit definition for SAI_xFRCR register *******************/ 10706 #define SAI_xFRCR_FRL_Pos (0U) 10707 #define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */ 10708 #define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[7:0](Frame length) */ 10709 #define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */ 10710 #define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */ 10711 #define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */ 10712 #define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */ 10713 #define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */ 10714 #define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */ 10715 #define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */ 10716 #define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */ 10717 10718 #define SAI_xFRCR_FSALL_Pos (8U) 10719 #define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */ 10720 #define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[6:0] (Frame synchronization active level length) */ 10721 #define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */ 10722 #define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */ 10723 #define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */ 10724 #define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */ 10725 #define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */ 10726 #define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */ 10727 #define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */ 10728 10729 #define SAI_xFRCR_FSDEF_Pos (16U) 10730 #define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */ 10731 #define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */ 10732 #define SAI_xFRCR_FSPOL_Pos (17U) 10733 #define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */ 10734 #define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */ 10735 #define SAI_xFRCR_FSOFF_Pos (18U) 10736 #define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */ 10737 #define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */ 10738 10739 /****************** Bit definition for SAI_xSLOTR register *******************/ 10740 #define SAI_xSLOTR_FBOFF_Pos (0U) 10741 #define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */ 10742 #define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */ 10743 #define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */ 10744 #define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */ 10745 #define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */ 10746 #define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */ 10747 #define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */ 10748 10749 #define SAI_xSLOTR_SLOTSZ_Pos (6U) 10750 #define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */ 10751 #define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */ 10752 #define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */ 10753 #define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */ 10754 10755 #define SAI_xSLOTR_NBSLOT_Pos (8U) 10756 #define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */ 10757 #define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */ 10758 #define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */ 10759 #define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */ 10760 #define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */ 10761 #define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */ 10762 10763 #define SAI_xSLOTR_SLOTEN_Pos (16U) 10764 #define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */ 10765 #define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */ 10766 10767 /******************* Bit definition for SAI_xIMR register *******************/ 10768 #define SAI_xIMR_OVRUDRIE_Pos (0U) 10769 #define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */ 10770 #define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */ 10771 #define SAI_xIMR_MUTEDETIE_Pos (1U) 10772 #define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */ 10773 #define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */ 10774 #define SAI_xIMR_WCKCFGIE_Pos (2U) 10775 #define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */ 10776 #define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */ 10777 #define SAI_xIMR_FREQIE_Pos (3U) 10778 #define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */ 10779 #define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */ 10780 #define SAI_xIMR_CNRDYIE_Pos (4U) 10781 #define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */ 10782 #define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */ 10783 #define SAI_xIMR_AFSDETIE_Pos (5U) 10784 #define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */ 10785 #define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */ 10786 #define SAI_xIMR_LFSDETIE_Pos (6U) 10787 #define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */ 10788 #define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */ 10789 10790 /******************** Bit definition for SAI_xSR register *******************/ 10791 #define SAI_xSR_OVRUDR_Pos (0U) 10792 #define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */ 10793 #define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */ 10794 #define SAI_xSR_MUTEDET_Pos (1U) 10795 #define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */ 10796 #define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */ 10797 #define SAI_xSR_WCKCFG_Pos (2U) 10798 #define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */ 10799 #define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */ 10800 #define SAI_xSR_FREQ_Pos (3U) 10801 #define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */ 10802 #define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */ 10803 #define SAI_xSR_CNRDY_Pos (4U) 10804 #define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */ 10805 #define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */ 10806 #define SAI_xSR_AFSDET_Pos (5U) 10807 #define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */ 10808 #define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */ 10809 #define SAI_xSR_LFSDET_Pos (6U) 10810 #define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */ 10811 #define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */ 10812 10813 #define SAI_xSR_FLVL_Pos (16U) 10814 #define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */ 10815 #define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */ 10816 #define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */ 10817 #define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */ 10818 #define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */ 10819 10820 /****************** Bit definition for SAI_xCLRFR register ******************/ 10821 #define SAI_xCLRFR_COVRUDR_Pos (0U) 10822 #define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */ 10823 #define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */ 10824 #define SAI_xCLRFR_CMUTEDET_Pos (1U) 10825 #define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */ 10826 #define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */ 10827 #define SAI_xCLRFR_CWCKCFG_Pos (2U) 10828 #define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */ 10829 #define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */ 10830 #define SAI_xCLRFR_CFREQ_Pos (3U) 10831 #define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */ 10832 #define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */ 10833 #define SAI_xCLRFR_CCNRDY_Pos (4U) 10834 #define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */ 10835 #define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */ 10836 #define SAI_xCLRFR_CAFSDET_Pos (5U) 10837 #define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */ 10838 #define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */ 10839 #define SAI_xCLRFR_CLFSDET_Pos (6U) 10840 #define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */ 10841 #define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */ 10842 10843 /****************** Bit definition for SAI_xDR register ******************/ 10844 #define SAI_xDR_DATA_Pos (0U) 10845 #define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */ 10846 #define SAI_xDR_DATA SAI_xDR_DATA_Msk 10847 10848 /******************************************************************************/ 10849 /* */ 10850 /* Serial Peripheral Interface (SPI) */ 10851 /* */ 10852 /******************************************************************************/ 10853 /******************* Bit definition for SPI_CR1 register ********************/ 10854 #define SPI_CR1_CPHA_Pos (0U) 10855 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ 10856 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */ 10857 #define SPI_CR1_CPOL_Pos (1U) 10858 #define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */ 10859 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */ 10860 #define SPI_CR1_MSTR_Pos (2U) 10861 #define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */ 10862 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */ 10863 10864 #define SPI_CR1_BR_Pos (3U) 10865 #define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */ 10866 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */ 10867 #define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */ 10868 #define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */ 10869 #define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */ 10870 10871 #define SPI_CR1_SPE_Pos (6U) 10872 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ 10873 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */ 10874 #define SPI_CR1_LSBFIRST_Pos (7U) 10875 #define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */ 10876 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */ 10877 #define SPI_CR1_SSI_Pos (8U) 10878 #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */ 10879 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */ 10880 #define SPI_CR1_SSM_Pos (9U) 10881 #define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */ 10882 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */ 10883 #define SPI_CR1_RXONLY_Pos (10U) 10884 #define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */ 10885 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */ 10886 #define SPI_CR1_CRCL_Pos (11U) 10887 #define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */ 10888 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */ 10889 #define SPI_CR1_CRCNEXT_Pos (12U) 10890 #define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */ 10891 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */ 10892 #define SPI_CR1_CRCEN_Pos (13U) 10893 #define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */ 10894 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */ 10895 #define SPI_CR1_BIDIOE_Pos (14U) 10896 #define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */ 10897 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */ 10898 #define SPI_CR1_BIDIMODE_Pos (15U) 10899 #define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */ 10900 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */ 10901 10902 /******************* Bit definition for SPI_CR2 register ********************/ 10903 #define SPI_CR2_RXDMAEN_Pos (0U) 10904 #define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */ 10905 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */ 10906 #define SPI_CR2_TXDMAEN_Pos (1U) 10907 #define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */ 10908 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */ 10909 #define SPI_CR2_SSOE_Pos (2U) 10910 #define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */ 10911 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */ 10912 #define SPI_CR2_NSSP_Pos (3U) 10913 #define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */ 10914 #define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */ 10915 #define SPI_CR2_FRF_Pos (4U) 10916 #define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */ 10917 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */ 10918 #define SPI_CR2_ERRIE_Pos (5U) 10919 #define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */ 10920 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */ 10921 #define SPI_CR2_RXNEIE_Pos (6U) 10922 #define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */ 10923 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */ 10924 #define SPI_CR2_TXEIE_Pos (7U) 10925 #define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */ 10926 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */ 10927 #define SPI_CR2_DS_Pos (8U) 10928 #define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos) /*!< 0x00000F00 */ 10929 #define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */ 10930 #define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos) /*!< 0x00000100 */ 10931 #define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos) /*!< 0x00000200 */ 10932 #define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos) /*!< 0x00000400 */ 10933 #define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos) /*!< 0x00000800 */ 10934 #define SPI_CR2_FRXTH_Pos (12U) 10935 #define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */ 10936 #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */ 10937 #define SPI_CR2_LDMARX_Pos (13U) 10938 #define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */ 10939 #define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */ 10940 #define SPI_CR2_LDMATX_Pos (14U) 10941 #define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */ 10942 #define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */ 10943 10944 /******************** Bit definition for SPI_SR register ********************/ 10945 #define SPI_SR_RXNE_Pos (0U) 10946 #define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */ 10947 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */ 10948 #define SPI_SR_TXE_Pos (1U) 10949 #define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */ 10950 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */ 10951 #define SPI_SR_CHSIDE_Pos (2U) 10952 #define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */ 10953 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */ 10954 #define SPI_SR_UDR_Pos (3U) 10955 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ 10956 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */ 10957 #define SPI_SR_CRCERR_Pos (4U) 10958 #define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ 10959 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */ 10960 #define SPI_SR_MODF_Pos (5U) 10961 #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */ 10962 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */ 10963 #define SPI_SR_OVR_Pos (6U) 10964 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */ 10965 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */ 10966 #define SPI_SR_BSY_Pos (7U) 10967 #define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */ 10968 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */ 10969 #define SPI_SR_FRE_Pos (8U) 10970 #define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */ 10971 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */ 10972 #define SPI_SR_FRLVL_Pos (9U) 10973 #define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */ 10974 #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */ 10975 #define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */ 10976 #define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */ 10977 #define SPI_SR_FTLVL_Pos (11U) 10978 #define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */ 10979 #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */ 10980 #define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */ 10981 #define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */ 10982 10983 /******************** Bit definition for SPI_DR register ********************/ 10984 #define SPI_DR_DR_Pos (0U) 10985 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ 10986 #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */ 10987 10988 /******************* Bit definition for SPI_CRCPR register ******************/ 10989 #define SPI_CRCPR_CRCPOLY_Pos (0U) 10990 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */ 10991 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */ 10992 10993 /****************** Bit definition for SPI_RXCRCR register ******************/ 10994 #define SPI_RXCRCR_RXCRC_Pos (0U) 10995 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */ 10996 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */ 10997 10998 /****************** Bit definition for SPI_TXCRCR register ******************/ 10999 #define SPI_TXCRCR_TXCRC_Pos (0U) 11000 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ 11001 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */ 11002 11003 /******************************************************************************/ 11004 /* */ 11005 /* QUADSPI */ 11006 /* */ 11007 /******************************************************************************/ 11008 /***************** Bit definition for QUADSPI_CR register *******************/ 11009 #define QUADSPI_CR_EN_Pos (0U) 11010 #define QUADSPI_CR_EN_Msk (0x1UL << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */ 11011 #define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */ 11012 #define QUADSPI_CR_ABORT_Pos (1U) 11013 #define QUADSPI_CR_ABORT_Msk (0x1UL << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */ 11014 #define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */ 11015 #define QUADSPI_CR_DMAEN_Pos (2U) 11016 #define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */ 11017 #define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */ 11018 #define QUADSPI_CR_TCEN_Pos (3U) 11019 #define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */ 11020 #define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */ 11021 #define QUADSPI_CR_SSHIFT_Pos (4U) 11022 #define QUADSPI_CR_SSHIFT_Msk (0x1UL << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */ 11023 #define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< Sample Shift */ 11024 #define QUADSPI_CR_DFM_Pos (6U) 11025 #define QUADSPI_CR_DFM_Msk (0x1UL << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */ 11026 #define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual-flash mode */ 11027 #define QUADSPI_CR_FSEL_Pos (7U) 11028 #define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */ 11029 #define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash memory selection */ 11030 #define QUADSPI_CR_FTHRES_Pos (8U) 11031 #define QUADSPI_CR_FTHRES_Msk (0xFUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */ 11032 #define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */ 11033 #define QUADSPI_CR_TEIE_Pos (16U) 11034 #define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */ 11035 #define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */ 11036 #define QUADSPI_CR_TCIE_Pos (17U) 11037 #define QUADSPI_CR_TCIE_Msk (0x1UL << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */ 11038 #define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */ 11039 #define QUADSPI_CR_FTIE_Pos (18U) 11040 #define QUADSPI_CR_FTIE_Msk (0x1UL << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */ 11041 #define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */ 11042 #define QUADSPI_CR_SMIE_Pos (19U) 11043 #define QUADSPI_CR_SMIE_Msk (0x1UL << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */ 11044 #define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */ 11045 #define QUADSPI_CR_TOIE_Pos (20U) 11046 #define QUADSPI_CR_TOIE_Msk (0x1UL << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */ 11047 #define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */ 11048 #define QUADSPI_CR_APMS_Pos (22U) 11049 #define QUADSPI_CR_APMS_Msk (0x1UL << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */ 11050 #define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Automatic Polling Mode Stop */ 11051 #define QUADSPI_CR_PMM_Pos (23U) 11052 #define QUADSPI_CR_PMM_Msk (0x1UL << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */ 11053 #define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */ 11054 #define QUADSPI_CR_PRESCALER_Pos (24U) 11055 #define QUADSPI_CR_PRESCALER_Msk (0xFFUL << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */ 11056 #define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */ 11057 11058 /***************** Bit definition for QUADSPI_DCR register ******************/ 11059 #define QUADSPI_DCR_CKMODE_Pos (0U) 11060 #define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */ 11061 #define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */ 11062 #define QUADSPI_DCR_CSHT_Pos (8U) 11063 #define QUADSPI_DCR_CSHT_Msk (0x7UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */ 11064 #define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */ 11065 #define QUADSPI_DCR_CSHT_0 (0x1UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */ 11066 #define QUADSPI_DCR_CSHT_1 (0x2UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */ 11067 #define QUADSPI_DCR_CSHT_2 (0x4UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */ 11068 #define QUADSPI_DCR_FSIZE_Pos (16U) 11069 #define QUADSPI_DCR_FSIZE_Msk (0x1FUL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */ 11070 #define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */ 11071 11072 /****************** Bit definition for QUADSPI_SR register *******************/ 11073 #define QUADSPI_SR_TEF_Pos (0U) 11074 #define QUADSPI_SR_TEF_Msk (0x1UL << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */ 11075 #define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */ 11076 #define QUADSPI_SR_TCF_Pos (1U) 11077 #define QUADSPI_SR_TCF_Msk (0x1UL << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */ 11078 #define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */ 11079 #define QUADSPI_SR_FTF_Pos (2U) 11080 #define QUADSPI_SR_FTF_Msk (0x1UL << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */ 11081 #define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */ 11082 #define QUADSPI_SR_SMF_Pos (3U) 11083 #define QUADSPI_SR_SMF_Msk (0x1UL << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */ 11084 #define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */ 11085 #define QUADSPI_SR_TOF_Pos (4U) 11086 #define QUADSPI_SR_TOF_Msk (0x1UL << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */ 11087 #define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */ 11088 #define QUADSPI_SR_BUSY_Pos (5U) 11089 #define QUADSPI_SR_BUSY_Msk (0x1UL << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */ 11090 #define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */ 11091 #define QUADSPI_SR_FLEVEL_Pos (8U) 11092 #define QUADSPI_SR_FLEVEL_Msk (0x1FUL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001F00 */ 11093 #define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */ 11094 11095 /****************** Bit definition for QUADSPI_FCR register ******************/ 11096 #define QUADSPI_FCR_CTEF_Pos (0U) 11097 #define QUADSPI_FCR_CTEF_Msk (0x1UL << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */ 11098 #define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */ 11099 #define QUADSPI_FCR_CTCF_Pos (1U) 11100 #define QUADSPI_FCR_CTCF_Msk (0x1UL << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */ 11101 #define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */ 11102 #define QUADSPI_FCR_CSMF_Pos (3U) 11103 #define QUADSPI_FCR_CSMF_Msk (0x1UL << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */ 11104 #define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */ 11105 #define QUADSPI_FCR_CTOF_Pos (4U) 11106 #define QUADSPI_FCR_CTOF_Msk (0x1UL << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */ 11107 #define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */ 11108 11109 /****************** Bit definition for QUADSPI_DLR register ******************/ 11110 #define QUADSPI_DLR_DL_Pos (0U) 11111 #define QUADSPI_DLR_DL_Msk (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */ 11112 #define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */ 11113 11114 /****************** Bit definition for QUADSPI_CCR register ******************/ 11115 #define QUADSPI_CCR_INSTRUCTION_Pos (0U) 11116 #define QUADSPI_CCR_INSTRUCTION_Msk (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */ 11117 #define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */ 11118 #define QUADSPI_CCR_IMODE_Pos (8U) 11119 #define QUADSPI_CCR_IMODE_Msk (0x3UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */ 11120 #define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */ 11121 #define QUADSPI_CCR_IMODE_0 (0x1UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */ 11122 #define QUADSPI_CCR_IMODE_1 (0x2UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */ 11123 #define QUADSPI_CCR_ADMODE_Pos (10U) 11124 #define QUADSPI_CCR_ADMODE_Msk (0x3UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */ 11125 #define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */ 11126 #define QUADSPI_CCR_ADMODE_0 (0x1UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */ 11127 #define QUADSPI_CCR_ADMODE_1 (0x2UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */ 11128 #define QUADSPI_CCR_ADSIZE_Pos (12U) 11129 #define QUADSPI_CCR_ADSIZE_Msk (0x3UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */ 11130 #define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */ 11131 #define QUADSPI_CCR_ADSIZE_0 (0x1UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */ 11132 #define QUADSPI_CCR_ADSIZE_1 (0x2UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */ 11133 #define QUADSPI_CCR_ABMODE_Pos (14U) 11134 #define QUADSPI_CCR_ABMODE_Msk (0x3UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */ 11135 #define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */ 11136 #define QUADSPI_CCR_ABMODE_0 (0x1UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */ 11137 #define QUADSPI_CCR_ABMODE_1 (0x2UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */ 11138 #define QUADSPI_CCR_ABSIZE_Pos (16U) 11139 #define QUADSPI_CCR_ABSIZE_Msk (0x3UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */ 11140 #define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */ 11141 #define QUADSPI_CCR_ABSIZE_0 (0x1UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */ 11142 #define QUADSPI_CCR_ABSIZE_1 (0x2UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */ 11143 #define QUADSPI_CCR_DCYC_Pos (18U) 11144 #define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */ 11145 #define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */ 11146 #define QUADSPI_CCR_DMODE_Pos (24U) 11147 #define QUADSPI_CCR_DMODE_Msk (0x3UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */ 11148 #define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */ 11149 #define QUADSPI_CCR_DMODE_0 (0x1UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */ 11150 #define QUADSPI_CCR_DMODE_1 (0x2UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */ 11151 #define QUADSPI_CCR_FMODE_Pos (26U) 11152 #define QUADSPI_CCR_FMODE_Msk (0x3UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */ 11153 #define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */ 11154 #define QUADSPI_CCR_FMODE_0 (0x1UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */ 11155 #define QUADSPI_CCR_FMODE_1 (0x2UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */ 11156 #define QUADSPI_CCR_SIOO_Pos (28U) 11157 #define QUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */ 11158 #define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */ 11159 #define QUADSPI_CCR_DHHC_Pos (30U) 11160 #define QUADSPI_CCR_DHHC_Msk (0x1UL << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */ 11161 #define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: DDR hold */ 11162 #define QUADSPI_CCR_DDRM_Pos (31U) 11163 #define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */ 11164 #define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */ 11165 11166 /****************** Bit definition for QUADSPI_AR register *******************/ 11167 #define QUADSPI_AR_ADDRESS_Pos (0U) 11168 #define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ 11169 #define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */ 11170 11171 /****************** Bit definition for QUADSPI_ABR register ******************/ 11172 #define QUADSPI_ABR_ALTERNATE_Pos (0U) 11173 #define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */ 11174 #define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */ 11175 11176 /****************** Bit definition for QUADSPI_DR register *******************/ 11177 #define QUADSPI_DR_DATA_Pos (0U) 11178 #define QUADSPI_DR_DATA_Msk (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */ 11179 #define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */ 11180 11181 /****************** Bit definition for QUADSPI_PSMKR register ****************/ 11182 #define QUADSPI_PSMKR_MASK_Pos (0U) 11183 #define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */ 11184 #define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */ 11185 11186 /****************** Bit definition for QUADSPI_PSMAR register ****************/ 11187 #define QUADSPI_PSMAR_MATCH_Pos (0U) 11188 #define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */ 11189 #define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */ 11190 11191 /****************** Bit definition for QUADSPI_PIR register *****************/ 11192 #define QUADSPI_PIR_INTERVAL_Pos (0U) 11193 #define QUADSPI_PIR_INTERVAL_Msk (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */ 11194 #define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */ 11195 11196 /****************** Bit definition for QUADSPI_LPTR register *****************/ 11197 #define QUADSPI_LPTR_TIMEOUT_Pos (0U) 11198 #define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */ 11199 #define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */ 11200 11201 /******************************************************************************/ 11202 /* */ 11203 /* SYSCFG */ 11204 /* */ 11205 /******************************************************************************/ 11206 /****************** Bit definition for SYSCFG_MEMRMP register ***************/ 11207 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U) 11208 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */ 11209 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */ 11210 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */ 11211 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */ 11212 #define SYSCFG_MEMRMP_MEM_MODE_2 (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */ 11213 11214 /****************** Bit definition for SYSCFG_CFGR1 register ******************/ 11215 #define SYSCFG_CFGR1_FWDIS_Pos (0U) 11216 #define SYSCFG_CFGR1_FWDIS_Msk (0x1UL << SYSCFG_CFGR1_FWDIS_Pos) /*!< 0x00000001 */ 11217 #define SYSCFG_CFGR1_FWDIS SYSCFG_CFGR1_FWDIS_Msk /*!< FIREWALL access enable*/ 11218 #define SYSCFG_CFGR1_BOOSTEN_Pos (8U) 11219 #define SYSCFG_CFGR1_BOOSTEN_Msk (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos) /*!< 0x00000100 */ 11220 #define SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk /*!< I/O analog switch voltage booster enable */ 11221 #define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U) 11222 #define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */ 11223 #define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */ 11224 #define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U) 11225 #define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */ 11226 #define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */ 11227 #define SYSCFG_CFGR1_I2C1_FMP_Pos (20U) 11228 #define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */ 11229 #define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */ 11230 #define SYSCFG_CFGR1_I2C3_FMP_Pos (22U) 11231 #define SYSCFG_CFGR1_I2C3_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C3_FMP_Pos) /*!< 0x00400000 */ 11232 #define SYSCFG_CFGR1_I2C3_FMP SYSCFG_CFGR1_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */ 11233 #define SYSCFG_CFGR1_FPU_IE_0 (0x04000000UL) /*!< Invalid operation Interrupt enable */ 11234 #define SYSCFG_CFGR1_FPU_IE_1 (0x08000000UL) /*!< Divide-by-zero Interrupt enable */ 11235 #define SYSCFG_CFGR1_FPU_IE_2 (0x10000000UL) /*!< Underflow Interrupt enable */ 11236 #define SYSCFG_CFGR1_FPU_IE_3 (0x20000000UL) /*!< Overflow Interrupt enable */ 11237 #define SYSCFG_CFGR1_FPU_IE_4 (0x40000000UL) /*!< Input denormal Interrupt enable */ 11238 #define SYSCFG_CFGR1_FPU_IE_5 (0x80000000UL) /*!< Inexact Interrupt enable (interrupt disabled at reset) */ 11239 11240 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/ 11241 #define SYSCFG_EXTICR1_EXTI0_Pos (0U) 11242 #define SYSCFG_EXTICR1_EXTI0_Msk (0x7UL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x00000007 */ 11243 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */ 11244 #define SYSCFG_EXTICR1_EXTI1_Pos (4U) 11245 #define SYSCFG_EXTICR1_EXTI1_Msk (0x7UL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x00000070 */ 11246 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */ 11247 #define SYSCFG_EXTICR1_EXTI2_Pos (8U) 11248 #define SYSCFG_EXTICR1_EXTI2_Msk (0x7UL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000700 */ 11249 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */ 11250 #define SYSCFG_EXTICR1_EXTI3_Pos (12U) 11251 #define SYSCFG_EXTICR1_EXTI3_Msk (0x7UL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x00007000 */ 11252 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */ 11253 11254 /** 11255 * @brief EXTI0 configuration 11256 */ 11257 #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000UL) /*!<PA[0] pin */ 11258 #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001UL) /*!<PB[0] pin */ 11259 #define SYSCFG_EXTICR1_EXTI0_PH (0x00000007UL) /*!<PH[0] pin */ 11260 11261 /** 11262 * @brief EXTI1 configuration 11263 */ 11264 #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000UL) /*!<PA[1] pin */ 11265 #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010UL) /*!<PB[1] pin */ 11266 #define SYSCFG_EXTICR1_EXTI1_PH (0x00000070UL) /*!<PH[1] pin */ 11267 11268 /** 11269 * @brief EXTI2 configuration 11270 */ 11271 #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000UL) /*!<PA[2] pin */ 11272 11273 /** 11274 * @brief EXTI3 configuration 11275 */ 11276 #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000UL) /*!<PA[3] pin */ 11277 #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000UL) /*!<PB[3] pin */ 11278 #define SYSCFG_EXTICR1_EXTI3_PG (0x00006000UL) /*!<PG[3] pin */ 11279 11280 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/ 11281 #define SYSCFG_EXTICR2_EXTI4_Pos (0U) 11282 #define SYSCFG_EXTICR2_EXTI4_Msk (0x7UL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x00000007 */ 11283 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */ 11284 #define SYSCFG_EXTICR2_EXTI5_Pos (4U) 11285 #define SYSCFG_EXTICR2_EXTI5_Msk (0x7UL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x00000070 */ 11286 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */ 11287 #define SYSCFG_EXTICR2_EXTI6_Pos (8U) 11288 #define SYSCFG_EXTICR2_EXTI6_Msk (0x7UL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000700 */ 11289 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */ 11290 #define SYSCFG_EXTICR2_EXTI7_Pos (12U) 11291 #define SYSCFG_EXTICR2_EXTI7_Msk (0x7UL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x00007000 */ 11292 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */ 11293 /** 11294 * @brief EXTI4 configuration 11295 */ 11296 #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000UL) /*!<PA[4] pin */ 11297 #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001UL) /*!<PB[4] pin */ 11298 11299 /** 11300 * @brief EXTI5 configuration 11301 */ 11302 #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000UL) /*!<PA[5] pin */ 11303 #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010UL) /*!<PB[5] pin */ 11304 11305 /** 11306 * @brief EXTI6 configuration 11307 */ 11308 #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000UL) /*!<PA[6] pin */ 11309 #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100UL) /*!<PB[6] pin */ 11310 11311 /** 11312 * @brief EXTI7 configuration 11313 */ 11314 #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000UL) /*!<PA[7] pin */ 11315 #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000UL) /*!<PB[7] pin */ 11316 11317 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/ 11318 #define SYSCFG_EXTICR3_EXTI8_Pos (0U) 11319 #define SYSCFG_EXTICR3_EXTI8_Msk (0x7UL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x00000007 */ 11320 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */ 11321 #define SYSCFG_EXTICR3_EXTI9_Pos (4U) 11322 #define SYSCFG_EXTICR3_EXTI9_Msk (0x7UL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x00000070 */ 11323 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */ 11324 #define SYSCFG_EXTICR3_EXTI10_Pos (8U) 11325 #define SYSCFG_EXTICR3_EXTI10_Msk (0x7UL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000700 */ 11326 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */ 11327 #define SYSCFG_EXTICR3_EXTI11_Pos (12U) 11328 #define SYSCFG_EXTICR3_EXTI11_Msk (0x7UL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x00007000 */ 11329 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */ 11330 11331 /** 11332 * @brief EXTI8 configuration 11333 */ 11334 #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000UL) /*!<PA[8] pin */ 11335 11336 /** 11337 * @brief EXTI9 configuration 11338 */ 11339 #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000UL) /*!<PA[9] pin */ 11340 11341 /** 11342 * @brief EXTI10 configuration 11343 */ 11344 #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000UL) /*!<PA[10] pin */ 11345 11346 /** 11347 * @brief EXTI11 configuration 11348 */ 11349 #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000UL) /*!<PA[11] pin */ 11350 11351 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/ 11352 #define SYSCFG_EXTICR4_EXTI12_Pos (0U) 11353 #define SYSCFG_EXTICR4_EXTI12_Msk (0x7UL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */ 11354 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */ 11355 #define SYSCFG_EXTICR4_EXTI13_Pos (4U) 11356 #define SYSCFG_EXTICR4_EXTI13_Msk (0x7UL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x00000070 */ 11357 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */ 11358 #define SYSCFG_EXTICR4_EXTI14_Pos (8U) 11359 #define SYSCFG_EXTICR4_EXTI14_Msk (0x7UL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000700 */ 11360 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */ 11361 #define SYSCFG_EXTICR4_EXTI15_Pos (12U) 11362 #define SYSCFG_EXTICR4_EXTI15_Msk (0x7UL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x00007000 */ 11363 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */ 11364 11365 /** 11366 * @brief EXTI12 configuration 11367 */ 11368 #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000UL) /*!<PA[12] pin */ 11369 11370 /** 11371 * @brief EXTI13 configuration 11372 */ 11373 #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000UL) /*!<PA[13] pin */ 11374 11375 /** 11376 * @brief EXTI14 configuration 11377 */ 11378 #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000UL) /*!<PA[14] pin */ 11379 #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200UL) /*!<PC[14] pin */ 11380 11381 /** 11382 * @brief EXTI15 configuration 11383 */ 11384 #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000UL) /*!<PA[15] pin */ 11385 #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000UL) /*!<PC[15] pin */ 11386 11387 /****************** Bit definition for SYSCFG_SCSR register ****************/ 11388 #define SYSCFG_SCSR_SRAM2ER_Pos (0U) 11389 #define SYSCFG_SCSR_SRAM2ER_Msk (0x1UL << SYSCFG_SCSR_SRAM2ER_Pos) /*!< 0x00000001 */ 11390 #define SYSCFG_SCSR_SRAM2ER SYSCFG_SCSR_SRAM2ER_Msk /*!< SRAM2 Erase Request */ 11391 #define SYSCFG_SCSR_SRAM2BSY_Pos (1U) 11392 #define SYSCFG_SCSR_SRAM2BSY_Msk (0x1UL << SYSCFG_SCSR_SRAM2BSY_Pos) /*!< 0x00000002 */ 11393 #define SYSCFG_SCSR_SRAM2BSY SYSCFG_SCSR_SRAM2BSY_Msk /*!< SRAM2 Erase Ongoing */ 11394 11395 /****************** Bit definition for SYSCFG_CFGR2 register ****************/ 11396 #define SYSCFG_CFGR2_CLL_Pos (0U) 11397 #define SYSCFG_CFGR2_CLL_Msk (0x1UL << SYSCFG_CFGR2_CLL_Pos) /*!< 0x00000001 */ 11398 #define SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk /*!< Core Lockup Lock */ 11399 #define SYSCFG_CFGR2_SPL_Pos (1U) 11400 #define SYSCFG_CFGR2_SPL_Msk (0x1UL << SYSCFG_CFGR2_SPL_Pos) /*!< 0x00000002 */ 11401 #define SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk /*!< SRAM Parity Lock*/ 11402 #define SYSCFG_CFGR2_PVDL_Pos (2U) 11403 #define SYSCFG_CFGR2_PVDL_Msk (0x1UL << SYSCFG_CFGR2_PVDL_Pos) /*!< 0x00000004 */ 11404 #define SYSCFG_CFGR2_PVDL SYSCFG_CFGR2_PVDL_Msk /*!< PVD Lock */ 11405 #define SYSCFG_CFGR2_ECCL_Pos (3U) 11406 #define SYSCFG_CFGR2_ECCL_Msk (0x1UL << SYSCFG_CFGR2_ECCL_Pos) /*!< 0x00000008 */ 11407 #define SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk /*!< ECC Lock*/ 11408 #define SYSCFG_CFGR2_SPF_Pos (8U) 11409 #define SYSCFG_CFGR2_SPF_Msk (0x1UL << SYSCFG_CFGR2_SPF_Pos) /*!< 0x00000100 */ 11410 #define SYSCFG_CFGR2_SPF SYSCFG_CFGR2_SPF_Msk /*!< SRAM Parity Flag */ 11411 11412 /****************** Bit definition for SYSCFG_SWPR register ****************/ 11413 #define SYSCFG_SWPR_PAGE0_Pos (0U) 11414 #define SYSCFG_SWPR_PAGE0_Msk (0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */ 11415 #define SYSCFG_SWPR_PAGE0 SYSCFG_SWPR_PAGE0_Msk /*!< SRAM2 Write protection page 0 */ 11416 #define SYSCFG_SWPR_PAGE1_Pos (1U) 11417 #define SYSCFG_SWPR_PAGE1_Msk (0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */ 11418 #define SYSCFG_SWPR_PAGE1 SYSCFG_SWPR_PAGE1_Msk /*!< SRAM2 Write protection page 1 */ 11419 #define SYSCFG_SWPR_PAGE2_Pos (2U) 11420 #define SYSCFG_SWPR_PAGE2_Msk (0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */ 11421 #define SYSCFG_SWPR_PAGE2 SYSCFG_SWPR_PAGE2_Msk /*!< SRAM2 Write protection page 2 */ 11422 #define SYSCFG_SWPR_PAGE3_Pos (3U) 11423 #define SYSCFG_SWPR_PAGE3_Msk (0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */ 11424 #define SYSCFG_SWPR_PAGE3 SYSCFG_SWPR_PAGE3_Msk /*!< SRAM2 Write protection page 3 */ 11425 #define SYSCFG_SWPR_PAGE4_Pos (4U) 11426 #define SYSCFG_SWPR_PAGE4_Msk (0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */ 11427 #define SYSCFG_SWPR_PAGE4 SYSCFG_SWPR_PAGE4_Msk /*!< SRAM2 Write protection page 4 */ 11428 #define SYSCFG_SWPR_PAGE5_Pos (5U) 11429 #define SYSCFG_SWPR_PAGE5_Msk (0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */ 11430 #define SYSCFG_SWPR_PAGE5 SYSCFG_SWPR_PAGE5_Msk /*!< SRAM2 Write protection page 5 */ 11431 #define SYSCFG_SWPR_PAGE6_Pos (6U) 11432 #define SYSCFG_SWPR_PAGE6_Msk (0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */ 11433 #define SYSCFG_SWPR_PAGE6 SYSCFG_SWPR_PAGE6_Msk /*!< SRAM2 Write protection page 6 */ 11434 #define SYSCFG_SWPR_PAGE7_Pos (7U) 11435 #define SYSCFG_SWPR_PAGE7_Msk (0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */ 11436 #define SYSCFG_SWPR_PAGE7 SYSCFG_SWPR_PAGE7_Msk /*!< SRAM2 Write protection page 7 */ 11437 #define SYSCFG_SWPR_PAGE8_Pos (8U) 11438 #define SYSCFG_SWPR_PAGE8_Msk (0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */ 11439 #define SYSCFG_SWPR_PAGE8 SYSCFG_SWPR_PAGE8_Msk /*!< SRAM2 Write protection page 8 */ 11440 #define SYSCFG_SWPR_PAGE9_Pos (9U) 11441 #define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */ 11442 #define SYSCFG_SWPR_PAGE9 SYSCFG_SWPR_PAGE9_Msk /*!< SRAM2 Write protection page 9 */ 11443 #define SYSCFG_SWPR_PAGE10_Pos (10U) 11444 #define SYSCFG_SWPR_PAGE10_Msk (0x1UL << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */ 11445 #define SYSCFG_SWPR_PAGE10 SYSCFG_SWPR_PAGE10_Msk /*!< SRAM2 Write protection page 10*/ 11446 #define SYSCFG_SWPR_PAGE11_Pos (11U) 11447 #define SYSCFG_SWPR_PAGE11_Msk (0x1UL << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */ 11448 #define SYSCFG_SWPR_PAGE11 SYSCFG_SWPR_PAGE11_Msk /*!< SRAM2 Write protection page 11*/ 11449 #define SYSCFG_SWPR_PAGE12_Pos (12U) 11450 #define SYSCFG_SWPR_PAGE12_Msk (0x1UL << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */ 11451 #define SYSCFG_SWPR_PAGE12 SYSCFG_SWPR_PAGE12_Msk /*!< SRAM2 Write protection page 12*/ 11452 #define SYSCFG_SWPR_PAGE13_Pos (13U) 11453 #define SYSCFG_SWPR_PAGE13_Msk (0x1UL << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */ 11454 #define SYSCFG_SWPR_PAGE13 SYSCFG_SWPR_PAGE13_Msk /*!< SRAM2 Write protection page 13*/ 11455 #define SYSCFG_SWPR_PAGE14_Pos (14U) 11456 #define SYSCFG_SWPR_PAGE14_Msk (0x1UL << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */ 11457 #define SYSCFG_SWPR_PAGE14 SYSCFG_SWPR_PAGE14_Msk /*!< SRAM2 Write protection page 14*/ 11458 #define SYSCFG_SWPR_PAGE15_Pos (15U) 11459 #define SYSCFG_SWPR_PAGE15_Msk (0x1UL << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */ 11460 #define SYSCFG_SWPR_PAGE15 SYSCFG_SWPR_PAGE15_Msk /*!< SRAM2 Write protection page 15*/ 11461 11462 /****************** Bit definition for SYSCFG_SKR register ****************/ 11463 #define SYSCFG_SKR_KEY_Pos (0U) 11464 #define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */ 11465 #define SYSCFG_SKR_KEY SYSCFG_SKR_KEY_Msk /*!< SRAM2 write protection key for software erase */ 11466 11467 11468 11469 11470 /******************************************************************************/ 11471 /* */ 11472 /* TIM */ 11473 /* */ 11474 /******************************************************************************/ 11475 /******************* Bit definition for TIM_CR1 register ********************/ 11476 #define TIM_CR1_CEN_Pos (0U) 11477 #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ 11478 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */ 11479 #define TIM_CR1_UDIS_Pos (1U) 11480 #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */ 11481 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ 11482 #define TIM_CR1_URS_Pos (2U) 11483 #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */ 11484 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */ 11485 #define TIM_CR1_OPM_Pos (3U) 11486 #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */ 11487 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */ 11488 #define TIM_CR1_DIR_Pos (4U) 11489 #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */ 11490 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */ 11491 11492 #define TIM_CR1_CMS_Pos (5U) 11493 #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */ 11494 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */ 11495 #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */ 11496 #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */ 11497 11498 #define TIM_CR1_ARPE_Pos (7U) 11499 #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */ 11500 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */ 11501 11502 #define TIM_CR1_CKD_Pos (8U) 11503 #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */ 11504 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */ 11505 #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */ 11506 #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */ 11507 11508 #define TIM_CR1_UIFREMAP_Pos (11U) 11509 #define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */ 11510 #define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */ 11511 11512 /******************* Bit definition for TIM_CR2 register ********************/ 11513 #define TIM_CR2_CCPC_Pos (0U) 11514 #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */ 11515 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */ 11516 #define TIM_CR2_CCUS_Pos (2U) 11517 #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */ 11518 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */ 11519 #define TIM_CR2_CCDS_Pos (3U) 11520 #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */ 11521 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */ 11522 11523 #define TIM_CR2_MMS_Pos (4U) 11524 #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */ 11525 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ 11526 #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */ 11527 #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */ 11528 #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */ 11529 11530 #define TIM_CR2_TI1S_Pos (7U) 11531 #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */ 11532 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */ 11533 #define TIM_CR2_OIS1_Pos (8U) 11534 #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */ 11535 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */ 11536 #define TIM_CR2_OIS1N_Pos (9U) 11537 #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */ 11538 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */ 11539 #define TIM_CR2_OIS2_Pos (10U) 11540 #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */ 11541 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */ 11542 #define TIM_CR2_OIS2N_Pos (11U) 11543 #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */ 11544 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */ 11545 #define TIM_CR2_OIS3_Pos (12U) 11546 #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */ 11547 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */ 11548 #define TIM_CR2_OIS3N_Pos (13U) 11549 #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */ 11550 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */ 11551 #define TIM_CR2_OIS4_Pos (14U) 11552 #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */ 11553 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */ 11554 #define TIM_CR2_OIS5_Pos (16U) 11555 #define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */ 11556 #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 5 (OC5 output) */ 11557 #define TIM_CR2_OIS6_Pos (18U) 11558 #define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */ 11559 #define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 6 (OC6 output) */ 11560 11561 #define TIM_CR2_MMS2_Pos (20U) 11562 #define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */ 11563 #define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ 11564 #define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */ 11565 #define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */ 11566 #define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */ 11567 #define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */ 11568 11569 /******************* Bit definition for TIM_SMCR register *******************/ 11570 #define TIM_SMCR_SMS_Pos (0U) 11571 #define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */ 11572 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */ 11573 #define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */ 11574 #define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */ 11575 #define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */ 11576 #define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */ 11577 11578 #define TIM_SMCR_OCCS_Pos (3U) 11579 #define TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */ 11580 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */ 11581 11582 #define TIM_SMCR_TS_Pos (4U) 11583 #define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */ 11584 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */ 11585 #define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */ 11586 #define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */ 11587 #define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */ 11588 11589 #define TIM_SMCR_MSM_Pos (7U) 11590 #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */ 11591 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */ 11592 11593 #define TIM_SMCR_ETF_Pos (8U) 11594 #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */ 11595 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */ 11596 #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */ 11597 #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */ 11598 #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */ 11599 #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */ 11600 11601 #define TIM_SMCR_ETPS_Pos (12U) 11602 #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */ 11603 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */ 11604 #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */ 11605 #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */ 11606 11607 #define TIM_SMCR_ECE_Pos (14U) 11608 #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */ 11609 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */ 11610 #define TIM_SMCR_ETP_Pos (15U) 11611 #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */ 11612 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */ 11613 11614 /******************* Bit definition for TIM_DIER register *******************/ 11615 #define TIM_DIER_UIE_Pos (0U) 11616 #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */ 11617 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */ 11618 #define TIM_DIER_CC1IE_Pos (1U) 11619 #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */ 11620 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */ 11621 #define TIM_DIER_CC2IE_Pos (2U) 11622 #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */ 11623 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */ 11624 #define TIM_DIER_CC3IE_Pos (3U) 11625 #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */ 11626 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */ 11627 #define TIM_DIER_CC4IE_Pos (4U) 11628 #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */ 11629 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */ 11630 #define TIM_DIER_COMIE_Pos (5U) 11631 #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */ 11632 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */ 11633 #define TIM_DIER_TIE_Pos (6U) 11634 #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */ 11635 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */ 11636 #define TIM_DIER_BIE_Pos (7U) 11637 #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */ 11638 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */ 11639 #define TIM_DIER_UDE_Pos (8U) 11640 #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */ 11641 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */ 11642 #define TIM_DIER_CC1DE_Pos (9U) 11643 #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */ 11644 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */ 11645 #define TIM_DIER_CC2DE_Pos (10U) 11646 #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */ 11647 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */ 11648 #define TIM_DIER_CC3DE_Pos (11U) 11649 #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */ 11650 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */ 11651 #define TIM_DIER_CC4DE_Pos (12U) 11652 #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */ 11653 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */ 11654 #define TIM_DIER_COMDE_Pos (13U) 11655 #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */ 11656 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */ 11657 #define TIM_DIER_TDE_Pos (14U) 11658 #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */ 11659 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */ 11660 11661 /******************** Bit definition for TIM_SR register ********************/ 11662 #define TIM_SR_UIF_Pos (0U) 11663 #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */ 11664 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */ 11665 #define TIM_SR_CC1IF_Pos (1U) 11666 #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */ 11667 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */ 11668 #define TIM_SR_CC2IF_Pos (2U) 11669 #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */ 11670 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */ 11671 #define TIM_SR_CC3IF_Pos (3U) 11672 #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */ 11673 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */ 11674 #define TIM_SR_CC4IF_Pos (4U) 11675 #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */ 11676 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */ 11677 #define TIM_SR_COMIF_Pos (5U) 11678 #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */ 11679 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */ 11680 #define TIM_SR_TIF_Pos (6U) 11681 #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */ 11682 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */ 11683 #define TIM_SR_BIF_Pos (7U) 11684 #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */ 11685 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */ 11686 #define TIM_SR_B2IF_Pos (8U) 11687 #define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos) /*!< 0x00000100 */ 11688 #define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break 2 interrupt Flag */ 11689 #define TIM_SR_CC1OF_Pos (9U) 11690 #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */ 11691 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */ 11692 #define TIM_SR_CC2OF_Pos (10U) 11693 #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */ 11694 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */ 11695 #define TIM_SR_CC3OF_Pos (11U) 11696 #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */ 11697 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */ 11698 #define TIM_SR_CC4OF_Pos (12U) 11699 #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */ 11700 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */ 11701 #define TIM_SR_SBIF_Pos (13U) 11702 #define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos) /*!< 0x00002000 */ 11703 #define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!<System Break interrupt Flag */ 11704 #define TIM_SR_CC5IF_Pos (16U) 11705 #define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */ 11706 #define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */ 11707 #define TIM_SR_CC6IF_Pos (17U) 11708 #define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */ 11709 #define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */ 11710 11711 11712 /******************* Bit definition for TIM_EGR register ********************/ 11713 #define TIM_EGR_UG_Pos (0U) 11714 #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */ 11715 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */ 11716 #define TIM_EGR_CC1G_Pos (1U) 11717 #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */ 11718 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */ 11719 #define TIM_EGR_CC2G_Pos (2U) 11720 #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */ 11721 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */ 11722 #define TIM_EGR_CC3G_Pos (3U) 11723 #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */ 11724 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */ 11725 #define TIM_EGR_CC4G_Pos (4U) 11726 #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */ 11727 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */ 11728 #define TIM_EGR_COMG_Pos (5U) 11729 #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */ 11730 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */ 11731 #define TIM_EGR_TG_Pos (6U) 11732 #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */ 11733 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */ 11734 #define TIM_EGR_BG_Pos (7U) 11735 #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */ 11736 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */ 11737 #define TIM_EGR_B2G_Pos (8U) 11738 #define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos) /*!< 0x00000100 */ 11739 #define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break 2 Generation */ 11740 11741 11742 /****************** Bit definition for TIM_CCMR1 register *******************/ 11743 #define TIM_CCMR1_CC1S_Pos (0U) 11744 #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */ 11745 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ 11746 #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */ 11747 #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */ 11748 11749 #define TIM_CCMR1_OC1FE_Pos (2U) 11750 #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */ 11751 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */ 11752 #define TIM_CCMR1_OC1PE_Pos (3U) 11753 #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */ 11754 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */ 11755 11756 #define TIM_CCMR1_OC1M_Pos (4U) 11757 #define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */ 11758 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ 11759 #define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */ 11760 #define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */ 11761 #define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */ 11762 #define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */ 11763 11764 #define TIM_CCMR1_OC1CE_Pos (7U) 11765 #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */ 11766 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1 Clear Enable */ 11767 11768 #define TIM_CCMR1_CC2S_Pos (8U) 11769 #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */ 11770 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ 11771 #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */ 11772 #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */ 11773 11774 #define TIM_CCMR1_OC2FE_Pos (10U) 11775 #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */ 11776 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */ 11777 #define TIM_CCMR1_OC2PE_Pos (11U) 11778 #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */ 11779 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */ 11780 11781 #define TIM_CCMR1_OC2M_Pos (12U) 11782 #define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */ 11783 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ 11784 #define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */ 11785 #define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */ 11786 #define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */ 11787 #define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */ 11788 11789 #define TIM_CCMR1_OC2CE_Pos (15U) 11790 #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */ 11791 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */ 11792 11793 /*----------------------------------------------------------------------------*/ 11794 #define TIM_CCMR1_IC1PSC_Pos (2U) 11795 #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */ 11796 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ 11797 #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */ 11798 #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */ 11799 11800 #define TIM_CCMR1_IC1F_Pos (4U) 11801 #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */ 11802 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ 11803 #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */ 11804 #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */ 11805 #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */ 11806 #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */ 11807 11808 #define TIM_CCMR1_IC2PSC_Pos (10U) 11809 #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */ 11810 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ 11811 #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */ 11812 #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */ 11813 11814 #define TIM_CCMR1_IC2F_Pos (12U) 11815 #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */ 11816 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ 11817 #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */ 11818 #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */ 11819 #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */ 11820 #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */ 11821 11822 /****************** Bit definition for TIM_CCMR2 register *******************/ 11823 #define TIM_CCMR2_CC3S_Pos (0U) 11824 #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */ 11825 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ 11826 #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */ 11827 #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */ 11828 11829 #define TIM_CCMR2_OC3FE_Pos (2U) 11830 #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */ 11831 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */ 11832 #define TIM_CCMR2_OC3PE_Pos (3U) 11833 #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */ 11834 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */ 11835 11836 #define TIM_CCMR2_OC3M_Pos (4U) 11837 #define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */ 11838 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ 11839 #define TIM_CCMR2_OC3M_0 (0x0001UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */ 11840 #define TIM_CCMR2_OC3M_1 (0x0002UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */ 11841 #define TIM_CCMR2_OC3M_2 (0x0004UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */ 11842 #define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */ 11843 11844 #define TIM_CCMR2_OC3CE_Pos (7U) 11845 #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */ 11846 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */ 11847 11848 #define TIM_CCMR2_CC4S_Pos (8U) 11849 #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */ 11850 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ 11851 #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */ 11852 #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */ 11853 11854 #define TIM_CCMR2_OC4FE_Pos (10U) 11855 #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */ 11856 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */ 11857 #define TIM_CCMR2_OC4PE_Pos (11U) 11858 #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */ 11859 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */ 11860 11861 #define TIM_CCMR2_OC4M_Pos (12U) 11862 #define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */ 11863 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ 11864 #define TIM_CCMR2_OC4M_0 (0x0001UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */ 11865 #define TIM_CCMR2_OC4M_1 (0x0002UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */ 11866 #define TIM_CCMR2_OC4M_2 (0x0004UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */ 11867 #define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */ 11868 11869 #define TIM_CCMR2_OC4CE_Pos (15U) 11870 #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */ 11871 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */ 11872 11873 /*----------------------------------------------------------------------------*/ 11874 #define TIM_CCMR2_IC3PSC_Pos (2U) 11875 #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */ 11876 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ 11877 #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */ 11878 #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */ 11879 11880 #define TIM_CCMR2_IC3F_Pos (4U) 11881 #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */ 11882 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ 11883 #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */ 11884 #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */ 11885 #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */ 11886 #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */ 11887 11888 #define TIM_CCMR2_IC4PSC_Pos (10U) 11889 #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */ 11890 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ 11891 #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */ 11892 #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */ 11893 11894 #define TIM_CCMR2_IC4F_Pos (12U) 11895 #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */ 11896 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ 11897 #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */ 11898 #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */ 11899 #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */ 11900 #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */ 11901 11902 /****************** Bit definition for TIM_CCMR3 register *******************/ 11903 #define TIM_CCMR3_OC5FE_Pos (2U) 11904 #define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */ 11905 #define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */ 11906 #define TIM_CCMR3_OC5PE_Pos (3U) 11907 #define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */ 11908 #define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */ 11909 11910 #define TIM_CCMR3_OC5M_Pos (4U) 11911 #define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */ 11912 #define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */ 11913 #define TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */ 11914 #define TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */ 11915 #define TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */ 11916 #define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */ 11917 11918 #define TIM_CCMR3_OC5CE_Pos (7U) 11919 #define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */ 11920 #define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */ 11921 11922 #define TIM_CCMR3_OC6FE_Pos (10U) 11923 #define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */ 11924 #define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */ 11925 #define TIM_CCMR3_OC6PE_Pos (11U) 11926 #define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */ 11927 #define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 6 Preload enable */ 11928 11929 #define TIM_CCMR3_OC6M_Pos (12U) 11930 #define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */ 11931 #define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC6M[3:0] bits (Output Compare 6 Mode) */ 11932 #define TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */ 11933 #define TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */ 11934 #define TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */ 11935 #define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */ 11936 11937 #define TIM_CCMR3_OC6CE_Pos (15U) 11938 #define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */ 11939 #define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 6 Clear Enable */ 11940 11941 /******************* Bit definition for TIM_CCER register *******************/ 11942 #define TIM_CCER_CC1E_Pos (0U) 11943 #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */ 11944 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */ 11945 #define TIM_CCER_CC1P_Pos (1U) 11946 #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */ 11947 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */ 11948 #define TIM_CCER_CC1NE_Pos (2U) 11949 #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */ 11950 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */ 11951 #define TIM_CCER_CC1NP_Pos (3U) 11952 #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */ 11953 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */ 11954 #define TIM_CCER_CC2E_Pos (4U) 11955 #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */ 11956 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */ 11957 #define TIM_CCER_CC2P_Pos (5U) 11958 #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */ 11959 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */ 11960 #define TIM_CCER_CC2NE_Pos (6U) 11961 #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */ 11962 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */ 11963 #define TIM_CCER_CC2NP_Pos (7U) 11964 #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */ 11965 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */ 11966 #define TIM_CCER_CC3E_Pos (8U) 11967 #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */ 11968 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */ 11969 #define TIM_CCER_CC3P_Pos (9U) 11970 #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */ 11971 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */ 11972 #define TIM_CCER_CC3NE_Pos (10U) 11973 #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */ 11974 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */ 11975 #define TIM_CCER_CC3NP_Pos (11U) 11976 #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */ 11977 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */ 11978 #define TIM_CCER_CC4E_Pos (12U) 11979 #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */ 11980 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */ 11981 #define TIM_CCER_CC4P_Pos (13U) 11982 #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */ 11983 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */ 11984 #define TIM_CCER_CC4NP_Pos (15U) 11985 #define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */ 11986 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */ 11987 #define TIM_CCER_CC5E_Pos (16U) 11988 #define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */ 11989 #define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */ 11990 #define TIM_CCER_CC5P_Pos (17U) 11991 #define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */ 11992 #define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */ 11993 #define TIM_CCER_CC6E_Pos (20U) 11994 #define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */ 11995 #define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */ 11996 #define TIM_CCER_CC6P_Pos (21U) 11997 #define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */ 11998 #define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */ 11999 12000 /******************* Bit definition for TIM_CNT register ********************/ 12001 #define TIM_CNT_CNT_Pos (0U) 12002 #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */ 12003 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */ 12004 #define TIM_CNT_UIFCPY_Pos (31U) 12005 #define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */ 12006 #define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy (if UIFREMAP=1) */ 12007 12008 /******************* Bit definition for TIM_PSC register ********************/ 12009 #define TIM_PSC_PSC_Pos (0U) 12010 #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */ 12011 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */ 12012 12013 /******************* Bit definition for TIM_ARR register ********************/ 12014 #define TIM_ARR_ARR_Pos (0U) 12015 #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */ 12016 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<Actual auto-reload Value */ 12017 12018 /******************* Bit definition for TIM_RCR register ********************/ 12019 #define TIM_RCR_REP_Pos (0U) 12020 #define TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */ 12021 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */ 12022 12023 /******************* Bit definition for TIM_CCR1 register *******************/ 12024 #define TIM_CCR1_CCR1_Pos (0U) 12025 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */ 12026 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */ 12027 12028 /******************* Bit definition for TIM_CCR2 register *******************/ 12029 #define TIM_CCR2_CCR2_Pos (0U) 12030 #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ 12031 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */ 12032 12033 /******************* Bit definition for TIM_CCR3 register *******************/ 12034 #define TIM_CCR3_CCR3_Pos (0U) 12035 #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */ 12036 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */ 12037 12038 /******************* Bit definition for TIM_CCR4 register *******************/ 12039 #define TIM_CCR4_CCR4_Pos (0U) 12040 #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */ 12041 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */ 12042 12043 /******************* Bit definition for TIM_CCR5 register *******************/ 12044 #define TIM_CCR5_CCR5_Pos (0U) 12045 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */ 12046 #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */ 12047 #define TIM_CCR5_GC5C1_Pos (29U) 12048 #define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */ 12049 #define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */ 12050 #define TIM_CCR5_GC5C2_Pos (30U) 12051 #define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */ 12052 #define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */ 12053 #define TIM_CCR5_GC5C3_Pos (31U) 12054 #define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */ 12055 #define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */ 12056 12057 /******************* Bit definition for TIM_CCR6 register *******************/ 12058 #define TIM_CCR6_CCR6_Pos (0U) 12059 #define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */ 12060 #define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */ 12061 12062 /******************* Bit definition for TIM_BDTR register *******************/ 12063 #define TIM_BDTR_DTG_Pos (0U) 12064 #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */ 12065 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ 12066 #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */ 12067 #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */ 12068 #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */ 12069 #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */ 12070 #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */ 12071 #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */ 12072 #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */ 12073 #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */ 12074 12075 #define TIM_BDTR_LOCK_Pos (8U) 12076 #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */ 12077 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */ 12078 #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */ 12079 #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */ 12080 12081 #define TIM_BDTR_OSSI_Pos (10U) 12082 #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */ 12083 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */ 12084 #define TIM_BDTR_OSSR_Pos (11U) 12085 #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */ 12086 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */ 12087 #define TIM_BDTR_BKE_Pos (12U) 12088 #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */ 12089 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break 1 */ 12090 #define TIM_BDTR_BKP_Pos (13U) 12091 #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */ 12092 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break 1 */ 12093 #define TIM_BDTR_AOE_Pos (14U) 12094 #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */ 12095 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */ 12096 #define TIM_BDTR_MOE_Pos (15U) 12097 #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */ 12098 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */ 12099 12100 #define TIM_BDTR_BKF_Pos (16U) 12101 #define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */ 12102 #define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break 1 */ 12103 #define TIM_BDTR_BK2F_Pos (20U) 12104 #define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */ 12105 #define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break 2 */ 12106 12107 #define TIM_BDTR_BK2E_Pos (24U) 12108 #define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */ 12109 #define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break 2 */ 12110 #define TIM_BDTR_BK2P_Pos (25U) 12111 #define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */ 12112 #define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break 2 */ 12113 12114 /******************* Bit definition for TIM_DCR register ********************/ 12115 #define TIM_DCR_DBA_Pos (0U) 12116 #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */ 12117 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */ 12118 #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */ 12119 #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */ 12120 #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */ 12121 #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */ 12122 #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */ 12123 12124 #define TIM_DCR_DBL_Pos (8U) 12125 #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ 12126 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */ 12127 #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */ 12128 #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */ 12129 #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */ 12130 #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */ 12131 #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */ 12132 12133 /******************* Bit definition for TIM_DMAR register *******************/ 12134 #define TIM_DMAR_DMAB_Pos (0U) 12135 #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */ 12136 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */ 12137 12138 /******************* Bit definition for TIM1_OR1 register *******************/ 12139 #define TIM1_OR1_ETR_ADC1_RMP_Pos (0U) 12140 #define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */ 12141 #define TIM1_OR1_ETR_ADC1_RMP TIM1_OR1_ETR_ADC1_RMP_Msk /*!<ETR_ADC1_RMP[1:0] bits (TIM1 ETR remap on ADC1) */ 12142 #define TIM1_OR1_ETR_ADC1_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */ 12143 #define TIM1_OR1_ETR_ADC1_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */ 12144 12145 #define TIM1_OR1_TI1_RMP_Pos (4U) 12146 #define TIM1_OR1_TI1_RMP_Msk (0x1UL << TIM1_OR1_TI1_RMP_Pos) /*!< 0x00000010 */ 12147 #define TIM1_OR1_TI1_RMP TIM1_OR1_TI1_RMP_Msk /*!<TIM1 Input Capture 1 remap */ 12148 12149 /******************* Bit definition for TIM1_OR2 register *******************/ 12150 #define TIM1_OR2_BKINE_Pos (0U) 12151 #define TIM1_OR2_BKINE_Msk (0x1UL << TIM1_OR2_BKINE_Pos) /*!< 0x00000001 */ 12152 #define TIM1_OR2_BKINE TIM1_OR2_BKINE_Msk /*!<BRK BKIN input enable */ 12153 #define TIM1_OR2_BKCMP1E_Pos (1U) 12154 #define TIM1_OR2_BKCMP1E_Msk (0x1UL << TIM1_OR2_BKCMP1E_Pos) /*!< 0x00000002 */ 12155 #define TIM1_OR2_BKCMP1E TIM1_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */ 12156 #define TIM1_OR2_BKCMP2E_Pos (2U) 12157 #define TIM1_OR2_BKCMP2E_Msk (0x1UL << TIM1_OR2_BKCMP2E_Pos) /*!< 0x00000004 */ 12158 #define TIM1_OR2_BKCMP2E TIM1_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */ 12159 #define TIM1_OR2_BKINP_Pos (9U) 12160 #define TIM1_OR2_BKINP_Msk (0x1UL << TIM1_OR2_BKINP_Pos) /*!< 0x00000200 */ 12161 #define TIM1_OR2_BKINP TIM1_OR2_BKINP_Msk /*!<BRK BKIN input polarity */ 12162 #define TIM1_OR2_BKCMP1P_Pos (10U) 12163 #define TIM1_OR2_BKCMP1P_Msk (0x1UL << TIM1_OR2_BKCMP1P_Pos) /*!< 0x00000400 */ 12164 #define TIM1_OR2_BKCMP1P TIM1_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */ 12165 #define TIM1_OR2_BKCMP2P_Pos (11U) 12166 #define TIM1_OR2_BKCMP2P_Msk (0x1UL << TIM1_OR2_BKCMP2P_Pos) /*!< 0x00000800 */ 12167 #define TIM1_OR2_BKCMP2P TIM1_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */ 12168 12169 #define TIM1_OR2_ETRSEL_Pos (14U) 12170 #define TIM1_OR2_ETRSEL_Msk (0x7UL << TIM1_OR2_ETRSEL_Pos) /*!< 0x0001C000 */ 12171 #define TIM1_OR2_ETRSEL TIM1_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM1 ETR source selection) */ 12172 #define TIM1_OR2_ETRSEL_0 (0x1UL << TIM1_OR2_ETRSEL_Pos) /*!< 0x00004000 */ 12173 #define TIM1_OR2_ETRSEL_1 (0x2UL << TIM1_OR2_ETRSEL_Pos) /*!< 0x00008000 */ 12174 #define TIM1_OR2_ETRSEL_2 (0x4UL << TIM1_OR2_ETRSEL_Pos) /*!< 0x00010000 */ 12175 12176 /******************* Bit definition for TIM1_OR3 register *******************/ 12177 #define TIM1_OR3_BK2INE_Pos (0U) 12178 #define TIM1_OR3_BK2INE_Msk (0x1UL << TIM1_OR3_BK2INE_Pos) /*!< 0x00000001 */ 12179 #define TIM1_OR3_BK2INE TIM1_OR3_BK2INE_Msk /*!<BRK2 BKIN2 input enable */ 12180 #define TIM1_OR3_BK2CMP1E_Pos (1U) 12181 #define TIM1_OR3_BK2CMP1E_Msk (0x1UL << TIM1_OR3_BK2CMP1E_Pos) /*!< 0x00000002 */ 12182 #define TIM1_OR3_BK2CMP1E TIM1_OR3_BK2CMP1E_Msk /*!<BRK2 COMP1 enable */ 12183 #define TIM1_OR3_BK2CMP2E_Pos (2U) 12184 #define TIM1_OR3_BK2CMP2E_Msk (0x1UL << TIM1_OR3_BK2CMP2E_Pos) /*!< 0x00000004 */ 12185 #define TIM1_OR3_BK2CMP2E TIM1_OR3_BK2CMP2E_Msk /*!<BRK2 COMP2 enable */ 12186 #define TIM1_OR3_BK2INP_Pos (9U) 12187 #define TIM1_OR3_BK2INP_Msk (0x1UL << TIM1_OR3_BK2INP_Pos) /*!< 0x00000200 */ 12188 #define TIM1_OR3_BK2INP TIM1_OR3_BK2INP_Msk /*!<BRK2 BKIN2 input polarity */ 12189 #define TIM1_OR3_BK2CMP1P_Pos (10U) 12190 #define TIM1_OR3_BK2CMP1P_Msk (0x1UL << TIM1_OR3_BK2CMP1P_Pos) /*!< 0x00000400 */ 12191 #define TIM1_OR3_BK2CMP1P TIM1_OR3_BK2CMP1P_Msk /*!<BRK2 COMP1 input polarity */ 12192 #define TIM1_OR3_BK2CMP2P_Pos (11U) 12193 #define TIM1_OR3_BK2CMP2P_Msk (0x1UL << TIM1_OR3_BK2CMP2P_Pos) /*!< 0x00000800 */ 12194 #define TIM1_OR3_BK2CMP2P TIM1_OR3_BK2CMP2P_Msk /*!<BRK2 COMP2 input polarity */ 12195 12196 12197 /******************* Bit definition for TIM2_OR1 register *******************/ 12198 #define TIM2_OR1_ITR1_RMP_Pos (0U) 12199 #define TIM2_OR1_ITR1_RMP_Msk (0x1UL << TIM2_OR1_ITR1_RMP_Pos) /*!< 0x00000001 */ 12200 #define TIM2_OR1_ITR1_RMP TIM2_OR1_ITR1_RMP_Msk /*!<TIM2 Internal trigger 1 remap */ 12201 #define TIM2_OR1_ETR1_RMP_Pos (1U) 12202 #define TIM2_OR1_ETR1_RMP_Msk (0x1UL << TIM2_OR1_ETR1_RMP_Pos) /*!< 0x00000002 */ 12203 #define TIM2_OR1_ETR1_RMP TIM2_OR1_ETR1_RMP_Msk /*!<TIM2 External trigger 1 remap */ 12204 12205 #define TIM2_OR1_TI4_RMP_Pos (2U) 12206 #define TIM2_OR1_TI4_RMP_Msk (0x3UL << TIM2_OR1_TI4_RMP_Pos) /*!< 0x0000000C */ 12207 #define TIM2_OR1_TI4_RMP TIM2_OR1_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM2 Input Capture 4 remap) */ 12208 #define TIM2_OR1_TI4_RMP_0 (0x1UL << TIM2_OR1_TI4_RMP_Pos) /*!< 0x00000004 */ 12209 #define TIM2_OR1_TI4_RMP_1 (0x2UL << TIM2_OR1_TI4_RMP_Pos) /*!< 0x00000008 */ 12210 12211 /******************* Bit definition for TIM2_OR2 register *******************/ 12212 #define TIM2_OR2_ETRSEL_Pos (14U) 12213 #define TIM2_OR2_ETRSEL_Msk (0x7UL << TIM2_OR2_ETRSEL_Pos) /*!< 0x0001C000 */ 12214 #define TIM2_OR2_ETRSEL TIM2_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM2 ETR source selection) */ 12215 #define TIM2_OR2_ETRSEL_0 (0x1UL << TIM2_OR2_ETRSEL_Pos) /*!< 0x00004000 */ 12216 #define TIM2_OR2_ETRSEL_1 (0x2UL << TIM2_OR2_ETRSEL_Pos) /*!< 0x00008000 */ 12217 #define TIM2_OR2_ETRSEL_2 (0x4UL << TIM2_OR2_ETRSEL_Pos) /*!< 0x00010000 */ 12218 12219 12220 /******************* Bit definition for TIM15_OR1 register ******************/ 12221 #define TIM15_OR1_TI1_RMP_Pos (0U) 12222 #define TIM15_OR1_TI1_RMP_Msk (0x1UL << TIM15_OR1_TI1_RMP_Pos) /*!< 0x00000001 */ 12223 #define TIM15_OR1_TI1_RMP TIM15_OR1_TI1_RMP_Msk /*!<TIM15 Input Capture 1 remap */ 12224 12225 #define TIM15_OR1_ENCODER_MODE_Pos (1U) 12226 #define TIM15_OR1_ENCODER_MODE_Msk (0x3UL << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000006 */ 12227 #define TIM15_OR1_ENCODER_MODE TIM15_OR1_ENCODER_MODE_Msk /*!<ENCODER_MODE[1:0] bits (TIM15 Encoder mode) */ 12228 #define TIM15_OR1_ENCODER_MODE_0 (0x1UL << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000002 */ 12229 #define TIM15_OR1_ENCODER_MODE_1 (0x2UL << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000004 */ 12230 12231 /******************* Bit definition for TIM15_OR2 register ******************/ 12232 #define TIM15_OR2_BKINE_Pos (0U) 12233 #define TIM15_OR2_BKINE_Msk (0x1UL << TIM15_OR2_BKINE_Pos) /*!< 0x00000001 */ 12234 #define TIM15_OR2_BKINE TIM15_OR2_BKINE_Msk /*!<BRK BKIN input enable */ 12235 #define TIM15_OR2_BKCMP1E_Pos (1U) 12236 #define TIM15_OR2_BKCMP1E_Msk (0x1UL << TIM15_OR2_BKCMP1E_Pos) /*!< 0x00000002 */ 12237 #define TIM15_OR2_BKCMP1E TIM15_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */ 12238 #define TIM15_OR2_BKCMP2E_Pos (2U) 12239 #define TIM15_OR2_BKCMP2E_Msk (0x1UL << TIM15_OR2_BKCMP2E_Pos) /*!< 0x00000004 */ 12240 #define TIM15_OR2_BKCMP2E TIM15_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */ 12241 #define TIM15_OR2_BKINP_Pos (9U) 12242 #define TIM15_OR2_BKINP_Msk (0x1UL << TIM15_OR2_BKINP_Pos) /*!< 0x00000200 */ 12243 #define TIM15_OR2_BKINP TIM15_OR2_BKINP_Msk /*!<BRK BKIN input polarity */ 12244 #define TIM15_OR2_BKCMP1P_Pos (10U) 12245 #define TIM15_OR2_BKCMP1P_Msk (0x1UL << TIM15_OR2_BKCMP1P_Pos) /*!< 0x00000400 */ 12246 #define TIM15_OR2_BKCMP1P TIM15_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */ 12247 #define TIM15_OR2_BKCMP2P_Pos (11U) 12248 #define TIM15_OR2_BKCMP2P_Msk (0x1UL << TIM15_OR2_BKCMP2P_Pos) /*!< 0x00000800 */ 12249 #define TIM15_OR2_BKCMP2P TIM15_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */ 12250 12251 /******************* Bit definition for TIM16_OR1 register ******************/ 12252 #define TIM16_OR1_TI1_RMP_Pos (0U) 12253 #define TIM16_OR1_TI1_RMP_Msk (0x7UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000007 */ 12254 #define TIM16_OR1_TI1_RMP TIM16_OR1_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM16 Input Capture 1 remap) */ 12255 #define TIM16_OR1_TI1_RMP_0 (0x1UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000001 */ 12256 #define TIM16_OR1_TI1_RMP_1 (0x2UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000002 */ 12257 #define TIM16_OR1_TI1_RMP_2 (0x4UL << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000004 */ 12258 12259 /******************* Bit definition for TIM16_OR2 register ******************/ 12260 #define TIM16_OR2_BKINE_Pos (0U) 12261 #define TIM16_OR2_BKINE_Msk (0x1UL << TIM16_OR2_BKINE_Pos) /*!< 0x00000001 */ 12262 #define TIM16_OR2_BKINE TIM16_OR2_BKINE_Msk /*!<BRK BKIN input enable */ 12263 #define TIM16_OR2_BKCMP1E_Pos (1U) 12264 #define TIM16_OR2_BKCMP1E_Msk (0x1UL << TIM16_OR2_BKCMP1E_Pos) /*!< 0x00000002 */ 12265 #define TIM16_OR2_BKCMP1E TIM16_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */ 12266 #define TIM16_OR2_BKCMP2E_Pos (2U) 12267 #define TIM16_OR2_BKCMP2E_Msk (0x1UL << TIM16_OR2_BKCMP2E_Pos) /*!< 0x00000004 */ 12268 #define TIM16_OR2_BKCMP2E TIM16_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */ 12269 #define TIM16_OR2_BKINP_Pos (9U) 12270 #define TIM16_OR2_BKINP_Msk (0x1UL << TIM16_OR2_BKINP_Pos) /*!< 0x00000200 */ 12271 #define TIM16_OR2_BKINP TIM16_OR2_BKINP_Msk /*!<BRK BKIN input polarity */ 12272 #define TIM16_OR2_BKCMP1P_Pos (10U) 12273 #define TIM16_OR2_BKCMP1P_Msk (0x1UL << TIM16_OR2_BKCMP1P_Pos) /*!< 0x00000400 */ 12274 #define TIM16_OR2_BKCMP1P TIM16_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */ 12275 #define TIM16_OR2_BKCMP2P_Pos (11U) 12276 #define TIM16_OR2_BKCMP2P_Msk (0x1UL << TIM16_OR2_BKCMP2P_Pos) /*!< 0x00000800 */ 12277 #define TIM16_OR2_BKCMP2P TIM16_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */ 12278 12279 12280 /******************************************************************************/ 12281 /* */ 12282 /* Low Power Timer (LPTIM) */ 12283 /* */ 12284 /******************************************************************************/ 12285 /****************** Bit definition for LPTIM_ISR register *******************/ 12286 #define LPTIM_ISR_CMPM_Pos (0U) 12287 #define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */ 12288 #define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */ 12289 #define LPTIM_ISR_ARRM_Pos (1U) 12290 #define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */ 12291 #define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */ 12292 #define LPTIM_ISR_EXTTRIG_Pos (2U) 12293 #define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */ 12294 #define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */ 12295 #define LPTIM_ISR_CMPOK_Pos (3U) 12296 #define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */ 12297 #define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */ 12298 #define LPTIM_ISR_ARROK_Pos (4U) 12299 #define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */ 12300 #define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */ 12301 #define LPTIM_ISR_UP_Pos (5U) 12302 #define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */ 12303 #define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */ 12304 #define LPTIM_ISR_DOWN_Pos (6U) 12305 #define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */ 12306 #define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */ 12307 12308 /****************** Bit definition for LPTIM_ICR register *******************/ 12309 #define LPTIM_ICR_CMPMCF_Pos (0U) 12310 #define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */ 12311 #define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */ 12312 #define LPTIM_ICR_ARRMCF_Pos (1U) 12313 #define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */ 12314 #define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */ 12315 #define LPTIM_ICR_EXTTRIGCF_Pos (2U) 12316 #define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */ 12317 #define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */ 12318 #define LPTIM_ICR_CMPOKCF_Pos (3U) 12319 #define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */ 12320 #define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */ 12321 #define LPTIM_ICR_ARROKCF_Pos (4U) 12322 #define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */ 12323 #define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */ 12324 #define LPTIM_ICR_UPCF_Pos (5U) 12325 #define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */ 12326 #define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */ 12327 #define LPTIM_ICR_DOWNCF_Pos (6U) 12328 #define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */ 12329 #define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */ 12330 12331 /****************** Bit definition for LPTIM_IER register ********************/ 12332 #define LPTIM_IER_CMPMIE_Pos (0U) 12333 #define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */ 12334 #define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */ 12335 #define LPTIM_IER_ARRMIE_Pos (1U) 12336 #define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */ 12337 #define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */ 12338 #define LPTIM_IER_EXTTRIGIE_Pos (2U) 12339 #define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */ 12340 #define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */ 12341 #define LPTIM_IER_CMPOKIE_Pos (3U) 12342 #define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */ 12343 #define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */ 12344 #define LPTIM_IER_ARROKIE_Pos (4U) 12345 #define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */ 12346 #define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */ 12347 #define LPTIM_IER_UPIE_Pos (5U) 12348 #define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */ 12349 #define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */ 12350 #define LPTIM_IER_DOWNIE_Pos (6U) 12351 #define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */ 12352 #define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */ 12353 12354 /****************** Bit definition for LPTIM_CFGR register *******************/ 12355 #define LPTIM_CFGR_CKSEL_Pos (0U) 12356 #define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */ 12357 #define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */ 12358 12359 #define LPTIM_CFGR_CKPOL_Pos (1U) 12360 #define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */ 12361 #define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */ 12362 #define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */ 12363 #define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */ 12364 12365 #define LPTIM_CFGR_CKFLT_Pos (3U) 12366 #define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */ 12367 #define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */ 12368 #define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */ 12369 #define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */ 12370 12371 #define LPTIM_CFGR_TRGFLT_Pos (6U) 12372 #define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */ 12373 #define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */ 12374 #define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */ 12375 #define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */ 12376 12377 #define LPTIM_CFGR_PRESC_Pos (9U) 12378 #define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */ 12379 #define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */ 12380 #define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */ 12381 #define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */ 12382 #define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */ 12383 12384 #define LPTIM_CFGR_TRIGSEL_Pos (13U) 12385 #define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */ 12386 #define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */ 12387 #define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */ 12388 #define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */ 12389 #define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */ 12390 12391 #define LPTIM_CFGR_TRIGEN_Pos (17U) 12392 #define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */ 12393 #define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */ 12394 #define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */ 12395 #define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */ 12396 12397 #define LPTIM_CFGR_TIMOUT_Pos (19U) 12398 #define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */ 12399 #define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */ 12400 #define LPTIM_CFGR_WAVE_Pos (20U) 12401 #define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */ 12402 #define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */ 12403 #define LPTIM_CFGR_WAVPOL_Pos (21U) 12404 #define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */ 12405 #define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */ 12406 #define LPTIM_CFGR_PRELOAD_Pos (22U) 12407 #define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */ 12408 #define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */ 12409 #define LPTIM_CFGR_COUNTMODE_Pos (23U) 12410 #define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */ 12411 #define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */ 12412 #define LPTIM_CFGR_ENC_Pos (24U) 12413 #define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */ 12414 #define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */ 12415 12416 /****************** Bit definition for LPTIM_CR register ********************/ 12417 #define LPTIM_CR_ENABLE_Pos (0U) 12418 #define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */ 12419 #define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */ 12420 #define LPTIM_CR_SNGSTRT_Pos (1U) 12421 #define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */ 12422 #define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */ 12423 #define LPTIM_CR_CNTSTRT_Pos (2U) 12424 #define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */ 12425 #define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */ 12426 12427 /****************** Bit definition for LPTIM_CMP register *******************/ 12428 #define LPTIM_CMP_CMP_Pos (0U) 12429 #define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */ 12430 #define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */ 12431 12432 /****************** Bit definition for LPTIM_ARR register *******************/ 12433 #define LPTIM_ARR_ARR_Pos (0U) 12434 #define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */ 12435 #define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */ 12436 12437 /****************** Bit definition for LPTIM_CNT register *******************/ 12438 #define LPTIM_CNT_CNT_Pos (0U) 12439 #define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */ 12440 #define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */ 12441 12442 /****************** Bit definition for LPTIM_OR register ********************/ 12443 #define LPTIM_OR_OR_Pos (0U) 12444 #define LPTIM_OR_OR_Msk (0x3UL << LPTIM_OR_OR_Pos) /*!< 0x00000003 */ 12445 #define LPTIM_OR_OR LPTIM_OR_OR_Msk /*!< OR[1:0] bits (Remap selection) */ 12446 #define LPTIM_OR_OR_0 (0x1UL << LPTIM_OR_OR_Pos) /*!< 0x00000001 */ 12447 #define LPTIM_OR_OR_1 (0x2UL << LPTIM_OR_OR_Pos) /*!< 0x00000002 */ 12448 12449 /******************************************************************************/ 12450 /* */ 12451 /* Analog Comparators (COMP) */ 12452 /* */ 12453 /******************************************************************************/ 12454 /********************** Bit definition for COMP_CSR register ****************/ 12455 #define COMP_CSR_EN_Pos (0U) 12456 #define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ 12457 #define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */ 12458 12459 #define COMP_CSR_PWRMODE_Pos (2U) 12460 #define COMP_CSR_PWRMODE_Msk (0x3UL << COMP_CSR_PWRMODE_Pos) /*!< 0x0000000C */ 12461 #define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< Comparator power mode */ 12462 #define COMP_CSR_PWRMODE_0 (0x1UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00000004 */ 12463 #define COMP_CSR_PWRMODE_1 (0x2UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00000008 */ 12464 12465 #define COMP_CSR_INMSEL_Pos (4U) 12466 #define COMP_CSR_INMSEL_Msk (0x7UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */ 12467 #define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */ 12468 #define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */ 12469 #define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */ 12470 #define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */ 12471 12472 #define COMP_CSR_INPSEL_Pos (7U) 12473 #define COMP_CSR_INPSEL_Msk (0x3UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000180 */ 12474 #define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */ 12475 #define COMP_CSR_INPSEL_0 (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000080 */ 12476 #define COMP_CSR_INPSEL_1 (0x2UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */ 12477 12478 #define COMP_CSR_WINMODE_Pos (9U) 12479 #define COMP_CSR_WINMODE_Msk (0x1UL << COMP_CSR_WINMODE_Pos) /*!< 0x00000200 */ 12480 #define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ 12481 12482 #define COMP_CSR_POLARITY_Pos (15U) 12483 #define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */ 12484 #define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */ 12485 12486 #define COMP_CSR_HYST_Pos (16U) 12487 #define COMP_CSR_HYST_Msk (0x3UL << COMP_CSR_HYST_Pos) /*!< 0x00030000 */ 12488 #define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */ 12489 #define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */ 12490 #define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */ 12491 12492 #define COMP_CSR_BLANKING_Pos (18U) 12493 #define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x001C0000 */ 12494 #define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */ 12495 #define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00040000 */ 12496 #define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */ 12497 #define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */ 12498 12499 #define COMP_CSR_BRGEN_Pos (22U) 12500 #define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */ 12501 #define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator voltage scaler enable */ 12502 #define COMP_CSR_SCALEN_Pos (23U) 12503 #define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */ 12504 #define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator scaler bridge enable */ 12505 12506 #define COMP_CSR_INMESEL_Pos (25U) 12507 #define COMP_CSR_INMESEL_Msk (0x3UL << COMP_CSR_INMESEL_Pos) /*!< 0x06000000 */ 12508 #define COMP_CSR_INMESEL COMP_CSR_INMESEL_Msk /*!< Comparator input minus extended selection */ 12509 #define COMP_CSR_INMESEL_0 (0x1UL << COMP_CSR_INMESEL_Pos) /*!< 0x02000000 */ 12510 #define COMP_CSR_INMESEL_1 (0x2UL << COMP_CSR_INMESEL_Pos) /*!< 0x04000000 */ 12511 12512 #define COMP_CSR_VALUE_Pos (30U) 12513 #define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */ 12514 #define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */ 12515 12516 #define COMP_CSR_LOCK_Pos (31U) 12517 #define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ 12518 #define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */ 12519 12520 /******************************************************************************/ 12521 /* */ 12522 /* Operational Amplifier (OPAMP) */ 12523 /* */ 12524 /******************************************************************************/ 12525 /********************* Bit definition for OPAMPx_CSR register ***************/ 12526 #define OPAMP_CSR_OPAMPxEN_Pos (0U) 12527 #define OPAMP_CSR_OPAMPxEN_Msk (0x1UL << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */ 12528 #define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */ 12529 #define OPAMP_CSR_OPALPM_Pos (1U) 12530 #define OPAMP_CSR_OPALPM_Msk (0x1UL << OPAMP_CSR_OPALPM_Pos) /*!< 0x00000002 */ 12531 #define OPAMP_CSR_OPALPM OPAMP_CSR_OPALPM_Msk /*!< Operational amplifier Low Power Mode */ 12532 12533 #define OPAMP_CSR_OPAMODE_Pos (2U) 12534 #define OPAMP_CSR_OPAMODE_Msk (0x3UL << OPAMP_CSR_OPAMODE_Pos) /*!< 0x0000000C */ 12535 #define OPAMP_CSR_OPAMODE OPAMP_CSR_OPAMODE_Msk /*!< Operational amplifier PGA mode */ 12536 #define OPAMP_CSR_OPAMODE_0 (0x1UL << OPAMP_CSR_OPAMODE_Pos) /*!< 0x00000004 */ 12537 #define OPAMP_CSR_OPAMODE_1 (0x2UL << OPAMP_CSR_OPAMODE_Pos) /*!< 0x00000008 */ 12538 12539 #define OPAMP_CSR_PGGAIN_Pos (4U) 12540 #define OPAMP_CSR_PGGAIN_Msk (0x3UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00000030 */ 12541 #define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Operational amplifier Programmable amplifier gain value */ 12542 #define OPAMP_CSR_PGGAIN_0 (0x1UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00000010 */ 12543 #define OPAMP_CSR_PGGAIN_1 (0x2UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00000020 */ 12544 12545 #define OPAMP_CSR_VMSEL_Pos (8U) 12546 #define OPAMP_CSR_VMSEL_Msk (0x3UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000300 */ 12547 #define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */ 12548 #define OPAMP_CSR_VMSEL_0 (0x1UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000100 */ 12549 #define OPAMP_CSR_VMSEL_1 (0x2UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000200 */ 12550 12551 #define OPAMP_CSR_VPSEL_Pos (10U) 12552 #define OPAMP_CSR_VPSEL_Msk (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000400 */ 12553 #define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverted input selection */ 12554 #define OPAMP_CSR_CALON_Pos (12U) 12555 #define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos) /*!< 0x00001000 */ 12556 #define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */ 12557 #define OPAMP_CSR_CALSEL_Pos (13U) 12558 #define OPAMP_CSR_CALSEL_Msk (0x1UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */ 12559 #define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */ 12560 #define OPAMP_CSR_USERTRIM_Pos (14U) 12561 #define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00004000 */ 12562 #define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */ 12563 #define OPAMP_CSR_CALOUT_Pos (15U) 12564 #define OPAMP_CSR_CALOUT_Msk (0x1UL << OPAMP_CSR_CALOUT_Pos) /*!< 0x00008000 */ 12565 #define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk /*!< Operational amplifier1 calibration output */ 12566 12567 /********************* Bit definition for OPAMP1_CSR register ***************/ 12568 #define OPAMP1_CSR_OPAEN_Pos (0U) 12569 #define OPAMP1_CSR_OPAEN_Msk (0x1UL << OPAMP1_CSR_OPAEN_Pos) /*!< 0x00000001 */ 12570 #define OPAMP1_CSR_OPAEN OPAMP1_CSR_OPAEN_Msk /*!< Operational amplifier1 Enable */ 12571 #define OPAMP1_CSR_OPALPM_Pos (1U) 12572 #define OPAMP1_CSR_OPALPM_Msk (0x1UL << OPAMP1_CSR_OPALPM_Pos) /*!< 0x00000002 */ 12573 #define OPAMP1_CSR_OPALPM OPAMP1_CSR_OPALPM_Msk /*!< Operational amplifier1 Low Power Mode */ 12574 12575 #define OPAMP1_CSR_OPAMODE_Pos (2U) 12576 #define OPAMP1_CSR_OPAMODE_Msk (0x3UL << OPAMP1_CSR_OPAMODE_Pos) /*!< 0x0000000C */ 12577 #define OPAMP1_CSR_OPAMODE OPAMP1_CSR_OPAMODE_Msk /*!< Operational amplifier1 PGA mode */ 12578 #define OPAMP1_CSR_OPAMODE_0 (0x1UL << OPAMP1_CSR_OPAMODE_Pos) /*!< 0x00000004 */ 12579 #define OPAMP1_CSR_OPAMODE_1 (0x2UL << OPAMP1_CSR_OPAMODE_Pos) /*!< 0x00000008 */ 12580 12581 #define OPAMP1_CSR_PGAGAIN_Pos (4U) 12582 #define OPAMP1_CSR_PGAGAIN_Msk (0x3UL << OPAMP1_CSR_PGAGAIN_Pos) /*!< 0x00000030 */ 12583 #define OPAMP1_CSR_PGAGAIN OPAMP1_CSR_PGAGAIN_Msk /*!< Operational amplifier1 Programmable amplifier gain value */ 12584 #define OPAMP1_CSR_PGAGAIN_0 (0x1UL << OPAMP1_CSR_PGAGAIN_Pos) /*!< 0x00000010 */ 12585 #define OPAMP1_CSR_PGAGAIN_1 (0x2UL << OPAMP1_CSR_PGAGAIN_Pos) /*!< 0x00000020 */ 12586 12587 #define OPAMP1_CSR_VMSEL_Pos (8U) 12588 #define OPAMP1_CSR_VMSEL_Msk (0x3UL << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000300 */ 12589 #define OPAMP1_CSR_VMSEL OPAMP1_CSR_VMSEL_Msk /*!< Inverting input selection */ 12590 #define OPAMP1_CSR_VMSEL_0 (0x1UL << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000100 */ 12591 #define OPAMP1_CSR_VMSEL_1 (0x2UL << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000200 */ 12592 12593 #define OPAMP1_CSR_VPSEL_Pos (10U) 12594 #define OPAMP1_CSR_VPSEL_Msk (0x1UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000400 */ 12595 #define OPAMP1_CSR_VPSEL OPAMP1_CSR_VPSEL_Msk /*!< Non inverted input selection */ 12596 #define OPAMP1_CSR_CALON_Pos (12U) 12597 #define OPAMP1_CSR_CALON_Msk (0x1UL << OPAMP1_CSR_CALON_Pos) /*!< 0x00001000 */ 12598 #define OPAMP1_CSR_CALON OPAMP1_CSR_CALON_Msk /*!< Calibration mode enable */ 12599 #define OPAMP1_CSR_CALSEL_Pos (13U) 12600 #define OPAMP1_CSR_CALSEL_Msk (0x1UL << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00002000 */ 12601 #define OPAMP1_CSR_CALSEL OPAMP1_CSR_CALSEL_Msk /*!< Calibration selection */ 12602 #define OPAMP1_CSR_USERTRIM_Pos (14U) 12603 #define OPAMP1_CSR_USERTRIM_Msk (0x1UL << OPAMP1_CSR_USERTRIM_Pos) /*!< 0x00004000 */ 12604 #define OPAMP1_CSR_USERTRIM OPAMP1_CSR_USERTRIM_Msk /*!< User trimming enable */ 12605 #define OPAMP1_CSR_CALOUT_Pos (15U) 12606 #define OPAMP1_CSR_CALOUT_Msk (0x1UL << OPAMP1_CSR_CALOUT_Pos) /*!< 0x00008000 */ 12607 #define OPAMP1_CSR_CALOUT OPAMP1_CSR_CALOUT_Msk /*!< Operational amplifier1 calibration output */ 12608 12609 #define OPAMP1_CSR_OPARANGE_Pos (31U) 12610 #define OPAMP1_CSR_OPARANGE_Msk (0x1UL << OPAMP1_CSR_OPARANGE_Pos) /*!< 0x80000000 */ 12611 #define OPAMP1_CSR_OPARANGE OPAMP1_CSR_OPARANGE_Msk /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */ 12612 12613 /******************* Bit definition for OPAMP_OTR register ******************/ 12614 #define OPAMP_OTR_TRIMOFFSETN_Pos (0U) 12615 #define OPAMP_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */ 12616 #define OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */ 12617 #define OPAMP_OTR_TRIMOFFSETP_Pos (8U) 12618 #define OPAMP_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */ 12619 #define OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */ 12620 12621 /******************* Bit definition for OPAMP1_OTR register ******************/ 12622 #define OPAMP1_OTR_TRIMOFFSETN_Pos (0U) 12623 #define OPAMP1_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */ 12624 #define OPAMP1_OTR_TRIMOFFSETN OPAMP1_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */ 12625 #define OPAMP1_OTR_TRIMOFFSETP_Pos (8U) 12626 #define OPAMP1_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */ 12627 #define OPAMP1_OTR_TRIMOFFSETP OPAMP1_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */ 12628 12629 /******************* Bit definition for OPAMP_LPOTR register ****************/ 12630 #define OPAMP_LPOTR_TRIMLPOFFSETN_Pos (0U) 12631 #define OPAMP_LPOTR_TRIMLPOFFSETN_Msk (0x1FUL << OPAMP_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */ 12632 #define OPAMP_LPOTR_TRIMLPOFFSETN OPAMP_LPOTR_TRIMLPOFFSETN_Msk /*!< Trim for NMOS differential pairs */ 12633 #define OPAMP_LPOTR_TRIMLPOFFSETP_Pos (8U) 12634 #define OPAMP_LPOTR_TRIMLPOFFSETP_Msk (0x1FUL << OPAMP_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */ 12635 #define OPAMP_LPOTR_TRIMLPOFFSETP OPAMP_LPOTR_TRIMLPOFFSETP_Msk /*!< Trim for PMOS differential pairs */ 12636 12637 /******************* Bit definition for OPAMP1_LPOTR register ****************/ 12638 #define OPAMP1_LPOTR_TRIMLPOFFSETN_Pos (0U) 12639 #define OPAMP1_LPOTR_TRIMLPOFFSETN_Msk (0x1FUL << OPAMP1_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */ 12640 #define OPAMP1_LPOTR_TRIMLPOFFSETN OPAMP1_LPOTR_TRIMLPOFFSETN_Msk /*!< Trim for NMOS differential pairs */ 12641 #define OPAMP1_LPOTR_TRIMLPOFFSETP_Pos (8U) 12642 #define OPAMP1_LPOTR_TRIMLPOFFSETP_Msk (0x1FUL << OPAMP1_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */ 12643 #define OPAMP1_LPOTR_TRIMLPOFFSETP OPAMP1_LPOTR_TRIMLPOFFSETP_Msk /*!< Trim for PMOS differential pairs */ 12644 12645 /******************************************************************************/ 12646 /* */ 12647 /* Touch Sensing Controller (TSC) */ 12648 /* */ 12649 /******************************************************************************/ 12650 /******************* Bit definition for TSC_CR register *********************/ 12651 #define TSC_CR_TSCE_Pos (0U) 12652 #define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */ 12653 #define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!<Touch sensing controller enable */ 12654 #define TSC_CR_START_Pos (1U) 12655 #define TSC_CR_START_Msk (0x1UL << TSC_CR_START_Pos) /*!< 0x00000002 */ 12656 #define TSC_CR_START TSC_CR_START_Msk /*!<Start acquisition */ 12657 #define TSC_CR_AM_Pos (2U) 12658 #define TSC_CR_AM_Msk (0x1UL << TSC_CR_AM_Pos) /*!< 0x00000004 */ 12659 #define TSC_CR_AM TSC_CR_AM_Msk /*!<Acquisition mode */ 12660 #define TSC_CR_SYNCPOL_Pos (3U) 12661 #define TSC_CR_SYNCPOL_Msk (0x1UL << TSC_CR_SYNCPOL_Pos) /*!< 0x00000008 */ 12662 #define TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk /*!<Synchronization pin polarity */ 12663 #define TSC_CR_IODEF_Pos (4U) 12664 #define TSC_CR_IODEF_Msk (0x1UL << TSC_CR_IODEF_Pos) /*!< 0x00000010 */ 12665 #define TSC_CR_IODEF TSC_CR_IODEF_Msk /*!<IO default mode */ 12666 12667 #define TSC_CR_MCV_Pos (5U) 12668 #define TSC_CR_MCV_Msk (0x7UL << TSC_CR_MCV_Pos) /*!< 0x000000E0 */ 12669 #define TSC_CR_MCV TSC_CR_MCV_Msk /*!<MCV[2:0] bits (Max Count Value) */ 12670 #define TSC_CR_MCV_0 (0x1UL << TSC_CR_MCV_Pos) /*!< 0x00000020 */ 12671 #define TSC_CR_MCV_1 (0x2UL << TSC_CR_MCV_Pos) /*!< 0x00000040 */ 12672 #define TSC_CR_MCV_2 (0x4UL << TSC_CR_MCV_Pos) /*!< 0x00000080 */ 12673 12674 #define TSC_CR_PGPSC_Pos (12U) 12675 #define TSC_CR_PGPSC_Msk (0x7UL << TSC_CR_PGPSC_Pos) /*!< 0x00007000 */ 12676 #define TSC_CR_PGPSC TSC_CR_PGPSC_Msk /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */ 12677 #define TSC_CR_PGPSC_0 (0x1UL << TSC_CR_PGPSC_Pos) /*!< 0x00001000 */ 12678 #define TSC_CR_PGPSC_1 (0x2UL << TSC_CR_PGPSC_Pos) /*!< 0x00002000 */ 12679 #define TSC_CR_PGPSC_2 (0x4UL << TSC_CR_PGPSC_Pos) /*!< 0x00004000 */ 12680 12681 #define TSC_CR_SSPSC_Pos (15U) 12682 #define TSC_CR_SSPSC_Msk (0x1UL << TSC_CR_SSPSC_Pos) /*!< 0x00008000 */ 12683 #define TSC_CR_SSPSC TSC_CR_SSPSC_Msk /*!<Spread Spectrum Prescaler */ 12684 #define TSC_CR_SSE_Pos (16U) 12685 #define TSC_CR_SSE_Msk (0x1UL << TSC_CR_SSE_Pos) /*!< 0x00010000 */ 12686 #define TSC_CR_SSE TSC_CR_SSE_Msk /*!<Spread Spectrum Enable */ 12687 12688 #define TSC_CR_SSD_Pos (17U) 12689 #define TSC_CR_SSD_Msk (0x7FUL << TSC_CR_SSD_Pos) /*!< 0x00FE0000 */ 12690 #define TSC_CR_SSD TSC_CR_SSD_Msk /*!<SSD[6:0] bits (Spread Spectrum Deviation) */ 12691 #define TSC_CR_SSD_0 (0x01UL << TSC_CR_SSD_Pos) /*!< 0x00020000 */ 12692 #define TSC_CR_SSD_1 (0x02UL << TSC_CR_SSD_Pos) /*!< 0x00040000 */ 12693 #define TSC_CR_SSD_2 (0x04UL << TSC_CR_SSD_Pos) /*!< 0x00080000 */ 12694 #define TSC_CR_SSD_3 (0x08UL << TSC_CR_SSD_Pos) /*!< 0x00100000 */ 12695 #define TSC_CR_SSD_4 (0x10UL << TSC_CR_SSD_Pos) /*!< 0x00200000 */ 12696 #define TSC_CR_SSD_5 (0x20UL << TSC_CR_SSD_Pos) /*!< 0x00400000 */ 12697 #define TSC_CR_SSD_6 (0x40UL << TSC_CR_SSD_Pos) /*!< 0x00800000 */ 12698 12699 #define TSC_CR_CTPL_Pos (24U) 12700 #define TSC_CR_CTPL_Msk (0xFUL << TSC_CR_CTPL_Pos) /*!< 0x0F000000 */ 12701 #define TSC_CR_CTPL TSC_CR_CTPL_Msk /*!<CTPL[3:0] bits (Charge Transfer pulse low) */ 12702 #define TSC_CR_CTPL_0 (0x1UL << TSC_CR_CTPL_Pos) /*!< 0x01000000 */ 12703 #define TSC_CR_CTPL_1 (0x2UL << TSC_CR_CTPL_Pos) /*!< 0x02000000 */ 12704 #define TSC_CR_CTPL_2 (0x4UL << TSC_CR_CTPL_Pos) /*!< 0x04000000 */ 12705 #define TSC_CR_CTPL_3 (0x8UL << TSC_CR_CTPL_Pos) /*!< 0x08000000 */ 12706 12707 #define TSC_CR_CTPH_Pos (28U) 12708 #define TSC_CR_CTPH_Msk (0xFUL << TSC_CR_CTPH_Pos) /*!< 0xF0000000 */ 12709 #define TSC_CR_CTPH TSC_CR_CTPH_Msk /*!<CTPH[3:0] bits (Charge Transfer pulse high) */ 12710 #define TSC_CR_CTPH_0 (0x1UL << TSC_CR_CTPH_Pos) /*!< 0x10000000 */ 12711 #define TSC_CR_CTPH_1 (0x2UL << TSC_CR_CTPH_Pos) /*!< 0x20000000 */ 12712 #define TSC_CR_CTPH_2 (0x4UL << TSC_CR_CTPH_Pos) /*!< 0x40000000 */ 12713 #define TSC_CR_CTPH_3 (0x8UL << TSC_CR_CTPH_Pos) /*!< 0x80000000 */ 12714 12715 /******************* Bit definition for TSC_IER register ********************/ 12716 #define TSC_IER_EOAIE_Pos (0U) 12717 #define TSC_IER_EOAIE_Msk (0x1UL << TSC_IER_EOAIE_Pos) /*!< 0x00000001 */ 12718 #define TSC_IER_EOAIE TSC_IER_EOAIE_Msk /*!<End of acquisition interrupt enable */ 12719 #define TSC_IER_MCEIE_Pos (1U) 12720 #define TSC_IER_MCEIE_Msk (0x1UL << TSC_IER_MCEIE_Pos) /*!< 0x00000002 */ 12721 #define TSC_IER_MCEIE TSC_IER_MCEIE_Msk /*!<Max count error interrupt enable */ 12722 12723 /******************* Bit definition for TSC_ICR register ********************/ 12724 #define TSC_ICR_EOAIC_Pos (0U) 12725 #define TSC_ICR_EOAIC_Msk (0x1UL << TSC_ICR_EOAIC_Pos) /*!< 0x00000001 */ 12726 #define TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk /*!<End of acquisition interrupt clear */ 12727 #define TSC_ICR_MCEIC_Pos (1U) 12728 #define TSC_ICR_MCEIC_Msk (0x1UL << TSC_ICR_MCEIC_Pos) /*!< 0x00000002 */ 12729 #define TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk /*!<Max count error interrupt clear */ 12730 12731 /******************* Bit definition for TSC_ISR register ********************/ 12732 #define TSC_ISR_EOAF_Pos (0U) 12733 #define TSC_ISR_EOAF_Msk (0x1UL << TSC_ISR_EOAF_Pos) /*!< 0x00000001 */ 12734 #define TSC_ISR_EOAF TSC_ISR_EOAF_Msk /*!<End of acquisition flag */ 12735 #define TSC_ISR_MCEF_Pos (1U) 12736 #define TSC_ISR_MCEF_Msk (0x1UL << TSC_ISR_MCEF_Pos) /*!< 0x00000002 */ 12737 #define TSC_ISR_MCEF TSC_ISR_MCEF_Msk /*!<Max count error flag */ 12738 12739 /******************* Bit definition for TSC_IOHCR register ******************/ 12740 #define TSC_IOHCR_G1_IO1_Pos (0U) 12741 #define TSC_IOHCR_G1_IO1_Msk (0x1UL << TSC_IOHCR_G1_IO1_Pos) /*!< 0x00000001 */ 12742 #define TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk /*!<GROUP1_IO1 schmitt trigger hysteresis mode */ 12743 #define TSC_IOHCR_G1_IO2_Pos (1U) 12744 #define TSC_IOHCR_G1_IO2_Msk (0x1UL << TSC_IOHCR_G1_IO2_Pos) /*!< 0x00000002 */ 12745 #define TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk /*!<GROUP1_IO2 schmitt trigger hysteresis mode */ 12746 #define TSC_IOHCR_G1_IO3_Pos (2U) 12747 #define TSC_IOHCR_G1_IO3_Msk (0x1UL << TSC_IOHCR_G1_IO3_Pos) /*!< 0x00000004 */ 12748 #define TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk /*!<GROUP1_IO3 schmitt trigger hysteresis mode */ 12749 #define TSC_IOHCR_G1_IO4_Pos (3U) 12750 #define TSC_IOHCR_G1_IO4_Msk (0x1UL << TSC_IOHCR_G1_IO4_Pos) /*!< 0x00000008 */ 12751 #define TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk /*!<GROUP1_IO4 schmitt trigger hysteresis mode */ 12752 #define TSC_IOHCR_G2_IO1_Pos (4U) 12753 #define TSC_IOHCR_G2_IO1_Msk (0x1UL << TSC_IOHCR_G2_IO1_Pos) /*!< 0x00000010 */ 12754 #define TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk /*!<GROUP2_IO1 schmitt trigger hysteresis mode */ 12755 #define TSC_IOHCR_G2_IO2_Pos (5U) 12756 #define TSC_IOHCR_G2_IO2_Msk (0x1UL << TSC_IOHCR_G2_IO2_Pos) /*!< 0x00000020 */ 12757 #define TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk /*!<GROUP2_IO2 schmitt trigger hysteresis mode */ 12758 #define TSC_IOHCR_G2_IO3_Pos (6U) 12759 #define TSC_IOHCR_G2_IO3_Msk (0x1UL << TSC_IOHCR_G2_IO3_Pos) /*!< 0x00000040 */ 12760 #define TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk /*!<GROUP2_IO3 schmitt trigger hysteresis mode */ 12761 #define TSC_IOHCR_G2_IO4_Pos (7U) 12762 #define TSC_IOHCR_G2_IO4_Msk (0x1UL << TSC_IOHCR_G2_IO4_Pos) /*!< 0x00000080 */ 12763 #define TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk /*!<GROUP2_IO4 schmitt trigger hysteresis mode */ 12764 #define TSC_IOHCR_G3_IO1_Pos (8U) 12765 #define TSC_IOHCR_G3_IO1_Msk (0x1UL << TSC_IOHCR_G3_IO1_Pos) /*!< 0x00000100 */ 12766 #define TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk /*!<GROUP3_IO1 schmitt trigger hysteresis mode */ 12767 #define TSC_IOHCR_G3_IO2_Pos (9U) 12768 #define TSC_IOHCR_G3_IO2_Msk (0x1UL << TSC_IOHCR_G3_IO2_Pos) /*!< 0x00000200 */ 12769 #define TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk /*!<GROUP3_IO2 schmitt trigger hysteresis mode */ 12770 #define TSC_IOHCR_G3_IO3_Pos (10U) 12771 #define TSC_IOHCR_G3_IO3_Msk (0x1UL << TSC_IOHCR_G3_IO3_Pos) /*!< 0x00000400 */ 12772 #define TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk /*!<GROUP3_IO3 schmitt trigger hysteresis mode */ 12773 #define TSC_IOHCR_G3_IO4_Pos (11U) 12774 #define TSC_IOHCR_G3_IO4_Msk (0x1UL << TSC_IOHCR_G3_IO4_Pos) /*!< 0x00000800 */ 12775 #define TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk /*!<GROUP3_IO4 schmitt trigger hysteresis mode */ 12776 #define TSC_IOHCR_G4_IO1_Pos (12U) 12777 #define TSC_IOHCR_G4_IO1_Msk (0x1UL << TSC_IOHCR_G4_IO1_Pos) /*!< 0x00001000 */ 12778 #define TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk /*!<GROUP4_IO1 schmitt trigger hysteresis mode */ 12779 #define TSC_IOHCR_G4_IO2_Pos (13U) 12780 #define TSC_IOHCR_G4_IO2_Msk (0x1UL << TSC_IOHCR_G4_IO2_Pos) /*!< 0x00002000 */ 12781 #define TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk /*!<GROUP4_IO2 schmitt trigger hysteresis mode */ 12782 #define TSC_IOHCR_G4_IO3_Pos (14U) 12783 #define TSC_IOHCR_G4_IO3_Msk (0x1UL << TSC_IOHCR_G4_IO3_Pos) /*!< 0x00004000 */ 12784 #define TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk /*!<GROUP4_IO3 schmitt trigger hysteresis mode */ 12785 #define TSC_IOHCR_G4_IO4_Pos (15U) 12786 #define TSC_IOHCR_G4_IO4_Msk (0x1UL << TSC_IOHCR_G4_IO4_Pos) /*!< 0x00008000 */ 12787 #define TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk /*!<GROUP4_IO4 schmitt trigger hysteresis mode */ 12788 #define TSC_IOHCR_G5_IO1_Pos (16U) 12789 #define TSC_IOHCR_G5_IO1_Msk (0x1UL << TSC_IOHCR_G5_IO1_Pos) /*!< 0x00010000 */ 12790 #define TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk /*!<GROUP5_IO1 schmitt trigger hysteresis mode */ 12791 #define TSC_IOHCR_G5_IO2_Pos (17U) 12792 #define TSC_IOHCR_G5_IO2_Msk (0x1UL << TSC_IOHCR_G5_IO2_Pos) /*!< 0x00020000 */ 12793 #define TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk /*!<GROUP5_IO2 schmitt trigger hysteresis mode */ 12794 #define TSC_IOHCR_G5_IO3_Pos (18U) 12795 #define TSC_IOHCR_G5_IO3_Msk (0x1UL << TSC_IOHCR_G5_IO3_Pos) /*!< 0x00040000 */ 12796 #define TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk /*!<GROUP5_IO3 schmitt trigger hysteresis mode */ 12797 #define TSC_IOHCR_G5_IO4_Pos (19U) 12798 #define TSC_IOHCR_G5_IO4_Msk (0x1UL << TSC_IOHCR_G5_IO4_Pos) /*!< 0x00080000 */ 12799 #define TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk /*!<GROUP5_IO4 schmitt trigger hysteresis mode */ 12800 #define TSC_IOHCR_G6_IO1_Pos (20U) 12801 #define TSC_IOHCR_G6_IO1_Msk (0x1UL << TSC_IOHCR_G6_IO1_Pos) /*!< 0x00100000 */ 12802 #define TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk /*!<GROUP6_IO1 schmitt trigger hysteresis mode */ 12803 #define TSC_IOHCR_G6_IO2_Pos (21U) 12804 #define TSC_IOHCR_G6_IO2_Msk (0x1UL << TSC_IOHCR_G6_IO2_Pos) /*!< 0x00200000 */ 12805 #define TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk /*!<GROUP6_IO2 schmitt trigger hysteresis mode */ 12806 #define TSC_IOHCR_G6_IO3_Pos (22U) 12807 #define TSC_IOHCR_G6_IO3_Msk (0x1UL << TSC_IOHCR_G6_IO3_Pos) /*!< 0x00400000 */ 12808 #define TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk /*!<GROUP6_IO3 schmitt trigger hysteresis mode */ 12809 #define TSC_IOHCR_G6_IO4_Pos (23U) 12810 #define TSC_IOHCR_G6_IO4_Msk (0x1UL << TSC_IOHCR_G6_IO4_Pos) /*!< 0x00800000 */ 12811 #define TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk /*!<GROUP6_IO4 schmitt trigger hysteresis mode */ 12812 #define TSC_IOHCR_G7_IO1_Pos (24U) 12813 #define TSC_IOHCR_G7_IO1_Msk (0x1UL << TSC_IOHCR_G7_IO1_Pos) /*!< 0x01000000 */ 12814 #define TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk /*!<GROUP7_IO1 schmitt trigger hysteresis mode */ 12815 #define TSC_IOHCR_G7_IO2_Pos (25U) 12816 #define TSC_IOHCR_G7_IO2_Msk (0x1UL << TSC_IOHCR_G7_IO2_Pos) /*!< 0x02000000 */ 12817 #define TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk /*!<GROUP7_IO2 schmitt trigger hysteresis mode */ 12818 #define TSC_IOHCR_G7_IO3_Pos (26U) 12819 #define TSC_IOHCR_G7_IO3_Msk (0x1UL << TSC_IOHCR_G7_IO3_Pos) /*!< 0x04000000 */ 12820 #define TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk /*!<GROUP7_IO3 schmitt trigger hysteresis mode */ 12821 #define TSC_IOHCR_G7_IO4_Pos (27U) 12822 #define TSC_IOHCR_G7_IO4_Msk (0x1UL << TSC_IOHCR_G7_IO4_Pos) /*!< 0x08000000 */ 12823 #define TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk /*!<GROUP7_IO4 schmitt trigger hysteresis mode */ 12824 12825 /******************* Bit definition for TSC_IOASCR register *****************/ 12826 #define TSC_IOASCR_G1_IO1_Pos (0U) 12827 #define TSC_IOASCR_G1_IO1_Msk (0x1UL << TSC_IOASCR_G1_IO1_Pos) /*!< 0x00000001 */ 12828 #define TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk /*!<GROUP1_IO1 analog switch enable */ 12829 #define TSC_IOASCR_G1_IO2_Pos (1U) 12830 #define TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */ 12831 #define TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk /*!<GROUP1_IO2 analog switch enable */ 12832 #define TSC_IOASCR_G1_IO3_Pos (2U) 12833 #define TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */ 12834 #define TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk /*!<GROUP1_IO3 analog switch enable */ 12835 #define TSC_IOASCR_G1_IO4_Pos (3U) 12836 #define TSC_IOASCR_G1_IO4_Msk (0x1UL << TSC_IOASCR_G1_IO4_Pos) /*!< 0x00000008 */ 12837 #define TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk /*!<GROUP1_IO4 analog switch enable */ 12838 #define TSC_IOASCR_G2_IO1_Pos (4U) 12839 #define TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */ 12840 #define TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk /*!<GROUP2_IO1 analog switch enable */ 12841 #define TSC_IOASCR_G2_IO2_Pos (5U) 12842 #define TSC_IOASCR_G2_IO2_Msk (0x1UL << TSC_IOASCR_G2_IO2_Pos) /*!< 0x00000020 */ 12843 #define TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk /*!<GROUP2_IO2 analog switch enable */ 12844 #define TSC_IOASCR_G2_IO3_Pos (6U) 12845 #define TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */ 12846 #define TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk /*!<GROUP2_IO3 analog switch enable */ 12847 #define TSC_IOASCR_G2_IO4_Pos (7U) 12848 #define TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */ 12849 #define TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk /*!<GROUP2_IO4 analog switch enable */ 12850 #define TSC_IOASCR_G3_IO1_Pos (8U) 12851 #define TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */ 12852 #define TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk /*!<GROUP3_IO1 analog switch enable */ 12853 #define TSC_IOASCR_G3_IO2_Pos (9U) 12854 #define TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */ 12855 #define TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk /*!<GROUP3_IO2 analog switch enable */ 12856 #define TSC_IOASCR_G3_IO3_Pos (10U) 12857 #define TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */ 12858 #define TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk /*!<GROUP3_IO3 analog switch enable */ 12859 #define TSC_IOASCR_G3_IO4_Pos (11U) 12860 #define TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */ 12861 #define TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk /*!<GROUP3_IO4 analog switch enable */ 12862 #define TSC_IOASCR_G4_IO1_Pos (12U) 12863 #define TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */ 12864 #define TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk /*!<GROUP4_IO1 analog switch enable */ 12865 #define TSC_IOASCR_G4_IO2_Pos (13U) 12866 #define TSC_IOASCR_G4_IO2_Msk (0x1UL << TSC_IOASCR_G4_IO2_Pos) /*!< 0x00002000 */ 12867 #define TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk /*!<GROUP4_IO2 analog switch enable */ 12868 #define TSC_IOASCR_G4_IO3_Pos (14U) 12869 #define TSC_IOASCR_G4_IO3_Msk (0x1UL << TSC_IOASCR_G4_IO3_Pos) /*!< 0x00004000 */ 12870 #define TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk /*!<GROUP4_IO3 analog switch enable */ 12871 #define TSC_IOASCR_G4_IO4_Pos (15U) 12872 #define TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */ 12873 #define TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk /*!<GROUP4_IO4 analog switch enable */ 12874 #define TSC_IOASCR_G5_IO1_Pos (16U) 12875 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */ 12876 #define TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk /*!<GROUP5_IO1 analog switch enable */ 12877 #define TSC_IOASCR_G5_IO2_Pos (17U) 12878 #define TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */ 12879 #define TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk /*!<GROUP5_IO2 analog switch enable */ 12880 #define TSC_IOASCR_G5_IO3_Pos (18U) 12881 #define TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */ 12882 #define TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk /*!<GROUP5_IO3 analog switch enable */ 12883 #define TSC_IOASCR_G5_IO4_Pos (19U) 12884 #define TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */ 12885 #define TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk /*!<GROUP5_IO4 analog switch enable */ 12886 #define TSC_IOASCR_G6_IO1_Pos (20U) 12887 #define TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */ 12888 #define TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk /*!<GROUP6_IO1 analog switch enable */ 12889 #define TSC_IOASCR_G6_IO2_Pos (21U) 12890 #define TSC_IOASCR_G6_IO2_Msk (0x1UL << TSC_IOASCR_G6_IO2_Pos) /*!< 0x00200000 */ 12891 #define TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk /*!<GROUP6_IO2 analog switch enable */ 12892 #define TSC_IOASCR_G6_IO3_Pos (22U) 12893 #define TSC_IOASCR_G6_IO3_Msk (0x1UL << TSC_IOASCR_G6_IO3_Pos) /*!< 0x00400000 */ 12894 #define TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk /*!<GROUP6_IO3 analog switch enable */ 12895 #define TSC_IOASCR_G6_IO4_Pos (23U) 12896 #define TSC_IOASCR_G6_IO4_Msk (0x1UL << TSC_IOASCR_G6_IO4_Pos) /*!< 0x00800000 */ 12897 #define TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk /*!<GROUP6_IO4 analog switch enable */ 12898 #define TSC_IOASCR_G7_IO1_Pos (24U) 12899 #define TSC_IOASCR_G7_IO1_Msk (0x1UL << TSC_IOASCR_G7_IO1_Pos) /*!< 0x01000000 */ 12900 #define TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk /*!<GROUP7_IO1 analog switch enable */ 12901 #define TSC_IOASCR_G7_IO2_Pos (25U) 12902 #define TSC_IOASCR_G7_IO2_Msk (0x1UL << TSC_IOASCR_G7_IO2_Pos) /*!< 0x02000000 */ 12903 #define TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk /*!<GROUP7_IO2 analog switch enable */ 12904 #define TSC_IOASCR_G7_IO3_Pos (26U) 12905 #define TSC_IOASCR_G7_IO3_Msk (0x1UL << TSC_IOASCR_G7_IO3_Pos) /*!< 0x04000000 */ 12906 #define TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk /*!<GROUP7_IO3 analog switch enable */ 12907 #define TSC_IOASCR_G7_IO4_Pos (27U) 12908 #define TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */ 12909 #define TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk /*!<GROUP7_IO4 analog switch enable */ 12910 12911 /******************* Bit definition for TSC_IOSCR register ******************/ 12912 #define TSC_IOSCR_G1_IO1_Pos (0U) 12913 #define TSC_IOSCR_G1_IO1_Msk (0x1UL << TSC_IOSCR_G1_IO1_Pos) /*!< 0x00000001 */ 12914 #define TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk /*!<GROUP1_IO1 sampling mode */ 12915 #define TSC_IOSCR_G1_IO2_Pos (1U) 12916 #define TSC_IOSCR_G1_IO2_Msk (0x1UL << TSC_IOSCR_G1_IO2_Pos) /*!< 0x00000002 */ 12917 #define TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk /*!<GROUP1_IO2 sampling mode */ 12918 #define TSC_IOSCR_G1_IO3_Pos (2U) 12919 #define TSC_IOSCR_G1_IO3_Msk (0x1UL << TSC_IOSCR_G1_IO3_Pos) /*!< 0x00000004 */ 12920 #define TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk /*!<GROUP1_IO3 sampling mode */ 12921 #define TSC_IOSCR_G1_IO4_Pos (3U) 12922 #define TSC_IOSCR_G1_IO4_Msk (0x1UL << TSC_IOSCR_G1_IO4_Pos) /*!< 0x00000008 */ 12923 #define TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk /*!<GROUP1_IO4 sampling mode */ 12924 #define TSC_IOSCR_G2_IO1_Pos (4U) 12925 #define TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */ 12926 #define TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk /*!<GROUP2_IO1 sampling mode */ 12927 #define TSC_IOSCR_G2_IO2_Pos (5U) 12928 #define TSC_IOSCR_G2_IO2_Msk (0x1UL << TSC_IOSCR_G2_IO2_Pos) /*!< 0x00000020 */ 12929 #define TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk /*!<GROUP2_IO2 sampling mode */ 12930 #define TSC_IOSCR_G2_IO3_Pos (6U) 12931 #define TSC_IOSCR_G2_IO3_Msk (0x1UL << TSC_IOSCR_G2_IO3_Pos) /*!< 0x00000040 */ 12932 #define TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk /*!<GROUP2_IO3 sampling mode */ 12933 #define TSC_IOSCR_G2_IO4_Pos (7U) 12934 #define TSC_IOSCR_G2_IO4_Msk (0x1UL << TSC_IOSCR_G2_IO4_Pos) /*!< 0x00000080 */ 12935 #define TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk /*!<GROUP2_IO4 sampling mode */ 12936 #define TSC_IOSCR_G3_IO1_Pos (8U) 12937 #define TSC_IOSCR_G3_IO1_Msk (0x1UL << TSC_IOSCR_G3_IO1_Pos) /*!< 0x00000100 */ 12938 #define TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk /*!<GROUP3_IO1 sampling mode */ 12939 #define TSC_IOSCR_G3_IO2_Pos (9U) 12940 #define TSC_IOSCR_G3_IO2_Msk (0x1UL << TSC_IOSCR_G3_IO2_Pos) /*!< 0x00000200 */ 12941 #define TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk /*!<GROUP3_IO2 sampling mode */ 12942 #define TSC_IOSCR_G3_IO3_Pos (10U) 12943 #define TSC_IOSCR_G3_IO3_Msk (0x1UL << TSC_IOSCR_G3_IO3_Pos) /*!< 0x00000400 */ 12944 #define TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk /*!<GROUP3_IO3 sampling mode */ 12945 #define TSC_IOSCR_G3_IO4_Pos (11U) 12946 #define TSC_IOSCR_G3_IO4_Msk (0x1UL << TSC_IOSCR_G3_IO4_Pos) /*!< 0x00000800 */ 12947 #define TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk /*!<GROUP3_IO4 sampling mode */ 12948 #define TSC_IOSCR_G4_IO1_Pos (12U) 12949 #define TSC_IOSCR_G4_IO1_Msk (0x1UL << TSC_IOSCR_G4_IO1_Pos) /*!< 0x00001000 */ 12950 #define TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk /*!<GROUP4_IO1 sampling mode */ 12951 #define TSC_IOSCR_G4_IO2_Pos (13U) 12952 #define TSC_IOSCR_G4_IO2_Msk (0x1UL << TSC_IOSCR_G4_IO2_Pos) /*!< 0x00002000 */ 12953 #define TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk /*!<GROUP4_IO2 sampling mode */ 12954 #define TSC_IOSCR_G4_IO3_Pos (14U) 12955 #define TSC_IOSCR_G4_IO3_Msk (0x1UL << TSC_IOSCR_G4_IO3_Pos) /*!< 0x00004000 */ 12956 #define TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk /*!<GROUP4_IO3 sampling mode */ 12957 #define TSC_IOSCR_G4_IO4_Pos (15U) 12958 #define TSC_IOSCR_G4_IO4_Msk (0x1UL << TSC_IOSCR_G4_IO4_Pos) /*!< 0x00008000 */ 12959 #define TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk /*!<GROUP4_IO4 sampling mode */ 12960 #define TSC_IOSCR_G5_IO1_Pos (16U) 12961 #define TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */ 12962 #define TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk /*!<GROUP5_IO1 sampling mode */ 12963 #define TSC_IOSCR_G5_IO2_Pos (17U) 12964 #define TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */ 12965 #define TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk /*!<GROUP5_IO2 sampling mode */ 12966 #define TSC_IOSCR_G5_IO3_Pos (18U) 12967 #define TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */ 12968 #define TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk /*!<GROUP5_IO3 sampling mode */ 12969 #define TSC_IOSCR_G5_IO4_Pos (19U) 12970 #define TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */ 12971 #define TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk /*!<GROUP5_IO4 sampling mode */ 12972 #define TSC_IOSCR_G6_IO1_Pos (20U) 12973 #define TSC_IOSCR_G6_IO1_Msk (0x1UL << TSC_IOSCR_G6_IO1_Pos) /*!< 0x00100000 */ 12974 #define TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk /*!<GROUP6_IO1 sampling mode */ 12975 #define TSC_IOSCR_G6_IO2_Pos (21U) 12976 #define TSC_IOSCR_G6_IO2_Msk (0x1UL << TSC_IOSCR_G6_IO2_Pos) /*!< 0x00200000 */ 12977 #define TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk /*!<GROUP6_IO2 sampling mode */ 12978 #define TSC_IOSCR_G6_IO3_Pos (22U) 12979 #define TSC_IOSCR_G6_IO3_Msk (0x1UL << TSC_IOSCR_G6_IO3_Pos) /*!< 0x00400000 */ 12980 #define TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk /*!<GROUP6_IO3 sampling mode */ 12981 #define TSC_IOSCR_G6_IO4_Pos (23U) 12982 #define TSC_IOSCR_G6_IO4_Msk (0x1UL << TSC_IOSCR_G6_IO4_Pos) /*!< 0x00800000 */ 12983 #define TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk /*!<GROUP6_IO4 sampling mode */ 12984 #define TSC_IOSCR_G7_IO1_Pos (24U) 12985 #define TSC_IOSCR_G7_IO1_Msk (0x1UL << TSC_IOSCR_G7_IO1_Pos) /*!< 0x01000000 */ 12986 #define TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk /*!<GROUP7_IO1 sampling mode */ 12987 #define TSC_IOSCR_G7_IO2_Pos (25U) 12988 #define TSC_IOSCR_G7_IO2_Msk (0x1UL << TSC_IOSCR_G7_IO2_Pos) /*!< 0x02000000 */ 12989 #define TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk /*!<GROUP7_IO2 sampling mode */ 12990 #define TSC_IOSCR_G7_IO3_Pos (26U) 12991 #define TSC_IOSCR_G7_IO3_Msk (0x1UL << TSC_IOSCR_G7_IO3_Pos) /*!< 0x04000000 */ 12992 #define TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk /*!<GROUP7_IO3 sampling mode */ 12993 #define TSC_IOSCR_G7_IO4_Pos (27U) 12994 #define TSC_IOSCR_G7_IO4_Msk (0x1UL << TSC_IOSCR_G7_IO4_Pos) /*!< 0x08000000 */ 12995 #define TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk /*!<GROUP7_IO4 sampling mode */ 12996 12997 /******************* Bit definition for TSC_IOCCR register ******************/ 12998 #define TSC_IOCCR_G1_IO1_Pos (0U) 12999 #define TSC_IOCCR_G1_IO1_Msk (0x1UL << TSC_IOCCR_G1_IO1_Pos) /*!< 0x00000001 */ 13000 #define TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk /*!<GROUP1_IO1 channel mode */ 13001 #define TSC_IOCCR_G1_IO2_Pos (1U) 13002 #define TSC_IOCCR_G1_IO2_Msk (0x1UL << TSC_IOCCR_G1_IO2_Pos) /*!< 0x00000002 */ 13003 #define TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk /*!<GROUP1_IO2 channel mode */ 13004 #define TSC_IOCCR_G1_IO3_Pos (2U) 13005 #define TSC_IOCCR_G1_IO3_Msk (0x1UL << TSC_IOCCR_G1_IO3_Pos) /*!< 0x00000004 */ 13006 #define TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk /*!<GROUP1_IO3 channel mode */ 13007 #define TSC_IOCCR_G1_IO4_Pos (3U) 13008 #define TSC_IOCCR_G1_IO4_Msk (0x1UL << TSC_IOCCR_G1_IO4_Pos) /*!< 0x00000008 */ 13009 #define TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk /*!<GROUP1_IO4 channel mode */ 13010 #define TSC_IOCCR_G2_IO1_Pos (4U) 13011 #define TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */ 13012 #define TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk /*!<GROUP2_IO1 channel mode */ 13013 #define TSC_IOCCR_G2_IO2_Pos (5U) 13014 #define TSC_IOCCR_G2_IO2_Msk (0x1UL << TSC_IOCCR_G2_IO2_Pos) /*!< 0x00000020 */ 13015 #define TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk /*!<GROUP2_IO2 channel mode */ 13016 #define TSC_IOCCR_G2_IO3_Pos (6U) 13017 #define TSC_IOCCR_G2_IO3_Msk (0x1UL << TSC_IOCCR_G2_IO3_Pos) /*!< 0x00000040 */ 13018 #define TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk /*!<GROUP2_IO3 channel mode */ 13019 #define TSC_IOCCR_G2_IO4_Pos (7U) 13020 #define TSC_IOCCR_G2_IO4_Msk (0x1UL << TSC_IOCCR_G2_IO4_Pos) /*!< 0x00000080 */ 13021 #define TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk /*!<GROUP2_IO4 channel mode */ 13022 #define TSC_IOCCR_G3_IO1_Pos (8U) 13023 #define TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */ 13024 #define TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk /*!<GROUP3_IO1 channel mode */ 13025 #define TSC_IOCCR_G3_IO2_Pos (9U) 13026 #define TSC_IOCCR_G3_IO2_Msk (0x1UL << TSC_IOCCR_G3_IO2_Pos) /*!< 0x00000200 */ 13027 #define TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk /*!<GROUP3_IO2 channel mode */ 13028 #define TSC_IOCCR_G3_IO3_Pos (10U) 13029 #define TSC_IOCCR_G3_IO3_Msk (0x1UL << TSC_IOCCR_G3_IO3_Pos) /*!< 0x00000400 */ 13030 #define TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk /*!<GROUP3_IO3 channel mode */ 13031 #define TSC_IOCCR_G3_IO4_Pos (11U) 13032 #define TSC_IOCCR_G3_IO4_Msk (0x1UL << TSC_IOCCR_G3_IO4_Pos) /*!< 0x00000800 */ 13033 #define TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk /*!<GROUP3_IO4 channel mode */ 13034 #define TSC_IOCCR_G4_IO1_Pos (12U) 13035 #define TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */ 13036 #define TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk /*!<GROUP4_IO1 channel mode */ 13037 #define TSC_IOCCR_G4_IO2_Pos (13U) 13038 #define TSC_IOCCR_G4_IO2_Msk (0x1UL << TSC_IOCCR_G4_IO2_Pos) /*!< 0x00002000 */ 13039 #define TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk /*!<GROUP4_IO2 channel mode */ 13040 #define TSC_IOCCR_G4_IO3_Pos (14U) 13041 #define TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */ 13042 #define TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk /*!<GROUP4_IO3 channel mode */ 13043 #define TSC_IOCCR_G4_IO4_Pos (15U) 13044 #define TSC_IOCCR_G4_IO4_Msk (0x1UL << TSC_IOCCR_G4_IO4_Pos) /*!< 0x00008000 */ 13045 #define TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk /*!<GROUP4_IO4 channel mode */ 13046 #define TSC_IOCCR_G5_IO1_Pos (16U) 13047 #define TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */ 13048 #define TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk /*!<GROUP5_IO1 channel mode */ 13049 #define TSC_IOCCR_G5_IO2_Pos (17U) 13050 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */ 13051 #define TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk /*!<GROUP5_IO2 channel mode */ 13052 #define TSC_IOCCR_G5_IO3_Pos (18U) 13053 #define TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */ 13054 #define TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk /*!<GROUP5_IO3 channel mode */ 13055 #define TSC_IOCCR_G5_IO4_Pos (19U) 13056 #define TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */ 13057 #define TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk /*!<GROUP5_IO4 channel mode */ 13058 #define TSC_IOCCR_G6_IO1_Pos (20U) 13059 #define TSC_IOCCR_G6_IO1_Msk (0x1UL << TSC_IOCCR_G6_IO1_Pos) /*!< 0x00100000 */ 13060 #define TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk /*!<GROUP6_IO1 channel mode */ 13061 #define TSC_IOCCR_G6_IO2_Pos (21U) 13062 #define TSC_IOCCR_G6_IO2_Msk (0x1UL << TSC_IOCCR_G6_IO2_Pos) /*!< 0x00200000 */ 13063 #define TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk /*!<GROUP6_IO2 channel mode */ 13064 #define TSC_IOCCR_G6_IO3_Pos (22U) 13065 #define TSC_IOCCR_G6_IO3_Msk (0x1UL << TSC_IOCCR_G6_IO3_Pos) /*!< 0x00400000 */ 13066 #define TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk /*!<GROUP6_IO3 channel mode */ 13067 #define TSC_IOCCR_G6_IO4_Pos (23U) 13068 #define TSC_IOCCR_G6_IO4_Msk (0x1UL << TSC_IOCCR_G6_IO4_Pos) /*!< 0x00800000 */ 13069 #define TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk /*!<GROUP6_IO4 channel mode */ 13070 #define TSC_IOCCR_G7_IO1_Pos (24U) 13071 #define TSC_IOCCR_G7_IO1_Msk (0x1UL << TSC_IOCCR_G7_IO1_Pos) /*!< 0x01000000 */ 13072 #define TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk /*!<GROUP7_IO1 channel mode */ 13073 #define TSC_IOCCR_G7_IO2_Pos (25U) 13074 #define TSC_IOCCR_G7_IO2_Msk (0x1UL << TSC_IOCCR_G7_IO2_Pos) /*!< 0x02000000 */ 13075 #define TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk /*!<GROUP7_IO2 channel mode */ 13076 #define TSC_IOCCR_G7_IO3_Pos (26U) 13077 #define TSC_IOCCR_G7_IO3_Msk (0x1UL << TSC_IOCCR_G7_IO3_Pos) /*!< 0x04000000 */ 13078 #define TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk /*!<GROUP7_IO3 channel mode */ 13079 #define TSC_IOCCR_G7_IO4_Pos (27U) 13080 #define TSC_IOCCR_G7_IO4_Msk (0x1UL << TSC_IOCCR_G7_IO4_Pos) /*!< 0x08000000 */ 13081 #define TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk /*!<GROUP7_IO4 channel mode */ 13082 13083 /******************* Bit definition for TSC_IOGCSR register *****************/ 13084 #define TSC_IOGCSR_G1E_Pos (0U) 13085 #define TSC_IOGCSR_G1E_Msk (0x1UL << TSC_IOGCSR_G1E_Pos) /*!< 0x00000001 */ 13086 #define TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk /*!<Analog IO GROUP1 enable */ 13087 #define TSC_IOGCSR_G2E_Pos (1U) 13088 #define TSC_IOGCSR_G2E_Msk (0x1UL << TSC_IOGCSR_G2E_Pos) /*!< 0x00000002 */ 13089 #define TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk /*!<Analog IO GROUP2 enable */ 13090 #define TSC_IOGCSR_G3E_Pos (2U) 13091 #define TSC_IOGCSR_G3E_Msk (0x1UL << TSC_IOGCSR_G3E_Pos) /*!< 0x00000004 */ 13092 #define TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk /*!<Analog IO GROUP3 enable */ 13093 #define TSC_IOGCSR_G4E_Pos (3U) 13094 #define TSC_IOGCSR_G4E_Msk (0x1UL << TSC_IOGCSR_G4E_Pos) /*!< 0x00000008 */ 13095 #define TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk /*!<Analog IO GROUP4 enable */ 13096 #define TSC_IOGCSR_G5E_Pos (4U) 13097 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */ 13098 #define TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk /*!<Analog IO GROUP5 enable */ 13099 #define TSC_IOGCSR_G6E_Pos (5U) 13100 #define TSC_IOGCSR_G6E_Msk (0x1UL << TSC_IOGCSR_G6E_Pos) /*!< 0x00000020 */ 13101 #define TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk /*!<Analog IO GROUP6 enable */ 13102 #define TSC_IOGCSR_G7E_Pos (6U) 13103 #define TSC_IOGCSR_G7E_Msk (0x1UL << TSC_IOGCSR_G7E_Pos) /*!< 0x00000040 */ 13104 #define TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk /*!<Analog IO GROUP7 enable */ 13105 #define TSC_IOGCSR_G1S_Pos (16U) 13106 #define TSC_IOGCSR_G1S_Msk (0x1UL << TSC_IOGCSR_G1S_Pos) /*!< 0x00010000 */ 13107 #define TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk /*!<Analog IO GROUP1 status */ 13108 #define TSC_IOGCSR_G2S_Pos (17U) 13109 #define TSC_IOGCSR_G2S_Msk (0x1UL << TSC_IOGCSR_G2S_Pos) /*!< 0x00020000 */ 13110 #define TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk /*!<Analog IO GROUP2 status */ 13111 #define TSC_IOGCSR_G3S_Pos (18U) 13112 #define TSC_IOGCSR_G3S_Msk (0x1UL << TSC_IOGCSR_G3S_Pos) /*!< 0x00040000 */ 13113 #define TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk /*!<Analog IO GROUP3 status */ 13114 #define TSC_IOGCSR_G4S_Pos (19U) 13115 #define TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */ 13116 #define TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk /*!<Analog IO GROUP4 status */ 13117 #define TSC_IOGCSR_G5S_Pos (20U) 13118 #define TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */ 13119 #define TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk /*!<Analog IO GROUP5 status */ 13120 #define TSC_IOGCSR_G6S_Pos (21U) 13121 #define TSC_IOGCSR_G6S_Msk (0x1UL << TSC_IOGCSR_G6S_Pos) /*!< 0x00200000 */ 13122 #define TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk /*!<Analog IO GROUP6 status */ 13123 #define TSC_IOGCSR_G7S_Pos (22U) 13124 #define TSC_IOGCSR_G7S_Msk (0x1UL << TSC_IOGCSR_G7S_Pos) /*!< 0x00400000 */ 13125 #define TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk /*!<Analog IO GROUP7 status */ 13126 13127 /******************* Bit definition for TSC_IOGXCR register *****************/ 13128 #define TSC_IOGXCR_CNT_Pos (0U) 13129 #define TSC_IOGXCR_CNT_Msk (0x3FFFUL << TSC_IOGXCR_CNT_Pos) /*!< 0x00003FFF */ 13130 #define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk /*!<CNT[13:0] bits (Counter value) */ 13131 13132 /******************************************************************************/ 13133 /* */ 13134 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */ 13135 /* */ 13136 /******************************************************************************/ 13137 13138 /* 13139 * @brief Specific device feature definitions (not present on all devices in the STM32L4 series) 13140 */ 13141 #define USART_TCBGT_SUPPORT 13142 13143 /****************** Bit definition for USART_CR1 register *******************/ 13144 #define USART_CR1_UE_Pos (0U) 13145 #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */ 13146 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */ 13147 #define USART_CR1_UESM_Pos (1U) 13148 #define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */ 13149 #define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */ 13150 #define USART_CR1_RE_Pos (2U) 13151 #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */ 13152 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */ 13153 #define USART_CR1_TE_Pos (3U) 13154 #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */ 13155 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */ 13156 #define USART_CR1_IDLEIE_Pos (4U) 13157 #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */ 13158 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */ 13159 #define USART_CR1_RXNEIE_Pos (5U) 13160 #define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */ 13161 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */ 13162 #define USART_CR1_TCIE_Pos (6U) 13163 #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */ 13164 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */ 13165 #define USART_CR1_TXEIE_Pos (7U) 13166 #define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ 13167 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */ 13168 #define USART_CR1_PEIE_Pos (8U) 13169 #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ 13170 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */ 13171 #define USART_CR1_PS_Pos (9U) 13172 #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */ 13173 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */ 13174 #define USART_CR1_PCE_Pos (10U) 13175 #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */ 13176 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */ 13177 #define USART_CR1_WAKE_Pos (11U) 13178 #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */ 13179 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */ 13180 #define USART_CR1_M_Pos (12U) 13181 #define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */ 13182 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */ 13183 #define USART_CR1_M0_Pos (12U) 13184 #define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */ 13185 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */ 13186 #define USART_CR1_MME_Pos (13U) 13187 #define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */ 13188 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */ 13189 #define USART_CR1_CMIE_Pos (14U) 13190 #define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */ 13191 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */ 13192 #define USART_CR1_OVER8_Pos (15U) 13193 #define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */ 13194 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */ 13195 #define USART_CR1_DEDT_Pos (16U) 13196 #define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */ 13197 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */ 13198 #define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */ 13199 #define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */ 13200 #define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */ 13201 #define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */ 13202 #define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */ 13203 #define USART_CR1_DEAT_Pos (21U) 13204 #define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */ 13205 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */ 13206 #define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */ 13207 #define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */ 13208 #define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */ 13209 #define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */ 13210 #define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */ 13211 #define USART_CR1_RTOIE_Pos (26U) 13212 #define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */ 13213 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */ 13214 #define USART_CR1_EOBIE_Pos (27U) 13215 #define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */ 13216 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */ 13217 #define USART_CR1_M1_Pos (28U) 13218 #define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */ 13219 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */ 13220 13221 /****************** Bit definition for USART_CR2 register *******************/ 13222 #define USART_CR2_ADDM7_Pos (4U) 13223 #define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */ 13224 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */ 13225 #define USART_CR2_LBDL_Pos (5U) 13226 #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */ 13227 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */ 13228 #define USART_CR2_LBDIE_Pos (6U) 13229 #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */ 13230 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */ 13231 #define USART_CR2_LBCL_Pos (8U) 13232 #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */ 13233 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */ 13234 #define USART_CR2_CPHA_Pos (9U) 13235 #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */ 13236 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */ 13237 #define USART_CR2_CPOL_Pos (10U) 13238 #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */ 13239 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */ 13240 #define USART_CR2_CLKEN_Pos (11U) 13241 #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */ 13242 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */ 13243 #define USART_CR2_STOP_Pos (12U) 13244 #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */ 13245 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */ 13246 #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */ 13247 #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */ 13248 #define USART_CR2_LINEN_Pos (14U) 13249 #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */ 13250 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */ 13251 #define USART_CR2_SWAP_Pos (15U) 13252 #define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */ 13253 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */ 13254 #define USART_CR2_RXINV_Pos (16U) 13255 #define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */ 13256 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */ 13257 #define USART_CR2_TXINV_Pos (17U) 13258 #define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */ 13259 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */ 13260 #define USART_CR2_DATAINV_Pos (18U) 13261 #define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */ 13262 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */ 13263 #define USART_CR2_MSBFIRST_Pos (19U) 13264 #define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */ 13265 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */ 13266 #define USART_CR2_ABREN_Pos (20U) 13267 #define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */ 13268 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/ 13269 #define USART_CR2_ABRMODE_Pos (21U) 13270 #define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */ 13271 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */ 13272 #define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */ 13273 #define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */ 13274 #define USART_CR2_RTOEN_Pos (23U) 13275 #define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */ 13276 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */ 13277 #define USART_CR2_ADD_Pos (24U) 13278 #define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */ 13279 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */ 13280 13281 /****************** Bit definition for USART_CR3 register *******************/ 13282 #define USART_CR3_EIE_Pos (0U) 13283 #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */ 13284 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */ 13285 #define USART_CR3_IREN_Pos (1U) 13286 #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */ 13287 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */ 13288 #define USART_CR3_IRLP_Pos (2U) 13289 #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */ 13290 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */ 13291 #define USART_CR3_HDSEL_Pos (3U) 13292 #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */ 13293 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */ 13294 #define USART_CR3_NACK_Pos (4U) 13295 #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */ 13296 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */ 13297 #define USART_CR3_SCEN_Pos (5U) 13298 #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */ 13299 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */ 13300 #define USART_CR3_DMAR_Pos (6U) 13301 #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */ 13302 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */ 13303 #define USART_CR3_DMAT_Pos (7U) 13304 #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */ 13305 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */ 13306 #define USART_CR3_RTSE_Pos (8U) 13307 #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */ 13308 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */ 13309 #define USART_CR3_CTSE_Pos (9U) 13310 #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */ 13311 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */ 13312 #define USART_CR3_CTSIE_Pos (10U) 13313 #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */ 13314 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */ 13315 #define USART_CR3_ONEBIT_Pos (11U) 13316 #define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */ 13317 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */ 13318 #define USART_CR3_OVRDIS_Pos (12U) 13319 #define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */ 13320 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */ 13321 #define USART_CR3_DDRE_Pos (13U) 13322 #define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */ 13323 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */ 13324 #define USART_CR3_DEM_Pos (14U) 13325 #define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */ 13326 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */ 13327 #define USART_CR3_DEP_Pos (15U) 13328 #define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */ 13329 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */ 13330 #define USART_CR3_SCARCNT_Pos (17U) 13331 #define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */ 13332 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */ 13333 #define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */ 13334 #define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */ 13335 #define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */ 13336 #define USART_CR3_WUS_Pos (20U) 13337 #define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */ 13338 #define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */ 13339 #define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */ 13340 #define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */ 13341 #define USART_CR3_WUFIE_Pos (22U) 13342 #define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */ 13343 #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */ 13344 #define USART_CR3_UCESM_Pos (23U) 13345 #define USART_CR3_UCESM_Msk (0x1UL << USART_CR3_UCESM_Pos) /*!< 0x02000000 */ 13346 #define USART_CR3_UCESM USART_CR3_UCESM_Msk /*!< USART Clock enable in Stop mode */ 13347 #define USART_CR3_TCBGTIE_Pos (24U) 13348 #define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */ 13349 #define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete Before Guard Time Interrupt Enable */ 13350 13351 /****************** Bit definition for USART_BRR register *******************/ 13352 #define USART_BRR_DIV_FRACTION_Pos (0U) 13353 #define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */ 13354 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */ 13355 #define USART_BRR_DIV_MANTISSA_Pos (4U) 13356 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */ 13357 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */ 13358 13359 /****************** Bit definition for USART_GTPR register ******************/ 13360 #define USART_GTPR_PSC_Pos (0U) 13361 #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */ 13362 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */ 13363 #define USART_GTPR_GT_Pos (8U) 13364 #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */ 13365 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */ 13366 13367 /******************* Bit definition for USART_RTOR register *****************/ 13368 #define USART_RTOR_RTO_Pos (0U) 13369 #define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */ 13370 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */ 13371 #define USART_RTOR_BLEN_Pos (24U) 13372 #define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */ 13373 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */ 13374 13375 /******************* Bit definition for USART_RQR register ******************/ 13376 #define USART_RQR_ABRRQ_Pos (0U) 13377 #define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */ 13378 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */ 13379 #define USART_RQR_SBKRQ_Pos (1U) 13380 #define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */ 13381 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */ 13382 #define USART_RQR_MMRQ_Pos (2U) 13383 #define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */ 13384 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */ 13385 #define USART_RQR_RXFRQ_Pos (3U) 13386 #define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */ 13387 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */ 13388 #define USART_RQR_TXFRQ_Pos (4U) 13389 #define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */ 13390 #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */ 13391 13392 /******************* Bit definition for USART_ISR register ******************/ 13393 #define USART_ISR_PE_Pos (0U) 13394 #define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */ 13395 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */ 13396 #define USART_ISR_FE_Pos (1U) 13397 #define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */ 13398 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */ 13399 #define USART_ISR_NE_Pos (2U) 13400 #define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */ 13401 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise Error detected Flag */ 13402 #define USART_ISR_ORE_Pos (3U) 13403 #define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */ 13404 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */ 13405 #define USART_ISR_IDLE_Pos (4U) 13406 #define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */ 13407 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */ 13408 #define USART_ISR_RXNE_Pos (5U) 13409 #define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */ 13410 #define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */ 13411 #define USART_ISR_TC_Pos (6U) 13412 #define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */ 13413 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */ 13414 #define USART_ISR_TXE_Pos (7U) 13415 #define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */ 13416 #define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */ 13417 #define USART_ISR_LBDF_Pos (8U) 13418 #define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */ 13419 #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */ 13420 #define USART_ISR_CTSIF_Pos (9U) 13421 #define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */ 13422 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */ 13423 #define USART_ISR_CTS_Pos (10U) 13424 #define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */ 13425 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */ 13426 #define USART_ISR_RTOF_Pos (11U) 13427 #define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */ 13428 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */ 13429 #define USART_ISR_EOBF_Pos (12U) 13430 #define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */ 13431 #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */ 13432 #define USART_ISR_ABRE_Pos (14U) 13433 #define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */ 13434 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */ 13435 #define USART_ISR_ABRF_Pos (15U) 13436 #define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */ 13437 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */ 13438 #define USART_ISR_BUSY_Pos (16U) 13439 #define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */ 13440 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */ 13441 #define USART_ISR_CMF_Pos (17U) 13442 #define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */ 13443 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */ 13444 #define USART_ISR_SBKF_Pos (18U) 13445 #define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */ 13446 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */ 13447 #define USART_ISR_RWU_Pos (19U) 13448 #define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */ 13449 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */ 13450 #define USART_ISR_WUF_Pos (20U) 13451 #define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */ 13452 #define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */ 13453 #define USART_ISR_TEACK_Pos (21U) 13454 #define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */ 13455 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */ 13456 #define USART_ISR_REACK_Pos (22U) 13457 #define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */ 13458 #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */ 13459 #define USART_ISR_TCBGT_Pos (25U) 13460 #define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */ 13461 #define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission Complete Before Guard Time Completion Flag */ 13462 13463 /******************* Bit definition for USART_ICR register ******************/ 13464 #define USART_ICR_PECF_Pos (0U) 13465 #define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */ 13466 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */ 13467 #define USART_ICR_FECF_Pos (1U) 13468 #define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */ 13469 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */ 13470 #define USART_ICR_NECF_Pos (2U) 13471 #define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos) /*!< 0x00000004 */ 13472 #define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise Error detected Clear Flag */ 13473 #define USART_ICR_ORECF_Pos (3U) 13474 #define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */ 13475 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */ 13476 #define USART_ICR_IDLECF_Pos (4U) 13477 #define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */ 13478 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */ 13479 #define USART_ICR_TCCF_Pos (6U) 13480 #define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */ 13481 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */ 13482 #define USART_ICR_TCBGTCF_Pos (7U) 13483 #define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */ 13484 #define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission Complete Before Guard Time Clear Flag */ 13485 #define USART_ICR_LBDCF_Pos (8U) 13486 #define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */ 13487 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */ 13488 #define USART_ICR_CTSCF_Pos (9U) 13489 #define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */ 13490 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */ 13491 #define USART_ICR_RTOCF_Pos (11U) 13492 #define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */ 13493 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */ 13494 #define USART_ICR_EOBCF_Pos (12U) 13495 #define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */ 13496 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */ 13497 #define USART_ICR_CMCF_Pos (17U) 13498 #define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */ 13499 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */ 13500 #define USART_ICR_WUCF_Pos (20U) 13501 #define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */ 13502 #define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */ 13503 13504 /* Legacy defines */ 13505 #define USART_ICR_NCF_Pos USART_ICR_NECF_Pos 13506 #define USART_ICR_NCF_Msk USART_ICR_NECF_Msk 13507 #define USART_ICR_NCF USART_ICR_NECF 13508 13509 /******************* Bit definition for USART_RDR register ******************/ 13510 #define USART_RDR_RDR_Pos (0U) 13511 #define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */ 13512 #define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */ 13513 13514 /******************* Bit definition for USART_TDR register ******************/ 13515 #define USART_TDR_TDR_Pos (0U) 13516 #define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */ 13517 #define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */ 13518 13519 /******************************************************************************/ 13520 /* */ 13521 /* Single Wire Protocol Master Interface (SWPMI) */ 13522 /* */ 13523 /******************************************************************************/ 13524 13525 /******************* Bit definition for SWPMI_CR register ********************/ 13526 #define SWPMI_CR_RXDMA_Pos (0U) 13527 #define SWPMI_CR_RXDMA_Msk (0x1UL << SWPMI_CR_RXDMA_Pos) /*!< 0x00000001 */ 13528 #define SWPMI_CR_RXDMA SWPMI_CR_RXDMA_Msk /*!<Reception DMA enable */ 13529 #define SWPMI_CR_TXDMA_Pos (1U) 13530 #define SWPMI_CR_TXDMA_Msk (0x1UL << SWPMI_CR_TXDMA_Pos) /*!< 0x00000002 */ 13531 #define SWPMI_CR_TXDMA SWPMI_CR_TXDMA_Msk /*!<Transmission DMA enable */ 13532 #define SWPMI_CR_RXMODE_Pos (2U) 13533 #define SWPMI_CR_RXMODE_Msk (0x1UL << SWPMI_CR_RXMODE_Pos) /*!< 0x00000004 */ 13534 #define SWPMI_CR_RXMODE SWPMI_CR_RXMODE_Msk /*!<Reception buffering mode */ 13535 #define SWPMI_CR_TXMODE_Pos (3U) 13536 #define SWPMI_CR_TXMODE_Msk (0x1UL << SWPMI_CR_TXMODE_Pos) /*!< 0x00000008 */ 13537 #define SWPMI_CR_TXMODE SWPMI_CR_TXMODE_Msk /*!<Transmission buffering mode */ 13538 #define SWPMI_CR_LPBK_Pos (4U) 13539 #define SWPMI_CR_LPBK_Msk (0x1UL << SWPMI_CR_LPBK_Pos) /*!< 0x00000010 */ 13540 #define SWPMI_CR_LPBK SWPMI_CR_LPBK_Msk /*!<Loopback mode enable */ 13541 #define SWPMI_CR_SWPACT_Pos (5U) 13542 #define SWPMI_CR_SWPACT_Msk (0x1UL << SWPMI_CR_SWPACT_Pos) /*!< 0x00000020 */ 13543 #define SWPMI_CR_SWPACT SWPMI_CR_SWPACT_Msk /*!<Single wire protocol master interface activate */ 13544 #define SWPMI_CR_DEACT_Pos (10U) 13545 #define SWPMI_CR_DEACT_Msk (0x1UL << SWPMI_CR_DEACT_Pos) /*!< 0x00000400 */ 13546 #define SWPMI_CR_DEACT SWPMI_CR_DEACT_Msk /*!<Single wire protocol master interface deactivate */ 13547 13548 /******************* Bit definition for SWPMI_BRR register ********************/ 13549 #define SWPMI_BRR_BR_Pos (0U) 13550 #define SWPMI_BRR_BR_Msk (0x3FUL << SWPMI_BRR_BR_Pos) /*!< 0x0000003F */ 13551 #define SWPMI_BRR_BR SWPMI_BRR_BR_Msk /*!<BR[5:0] bits (Bitrate prescaler) */ 13552 13553 /******************* Bit definition for SWPMI_ISR register ********************/ 13554 #define SWPMI_ISR_RXBFF_Pos (0U) 13555 #define SWPMI_ISR_RXBFF_Msk (0x1UL << SWPMI_ISR_RXBFF_Pos) /*!< 0x00000001 */ 13556 #define SWPMI_ISR_RXBFF SWPMI_ISR_RXBFF_Msk /*!<Receive buffer full flag */ 13557 #define SWPMI_ISR_TXBEF_Pos (1U) 13558 #define SWPMI_ISR_TXBEF_Msk (0x1UL << SWPMI_ISR_TXBEF_Pos) /*!< 0x00000002 */ 13559 #define SWPMI_ISR_TXBEF SWPMI_ISR_TXBEF_Msk /*!<Transmit buffer empty flag */ 13560 #define SWPMI_ISR_RXBERF_Pos (2U) 13561 #define SWPMI_ISR_RXBERF_Msk (0x1UL << SWPMI_ISR_RXBERF_Pos) /*!< 0x00000004 */ 13562 #define SWPMI_ISR_RXBERF SWPMI_ISR_RXBERF_Msk /*!<Receive CRC error flag */ 13563 #define SWPMI_ISR_RXOVRF_Pos (3U) 13564 #define SWPMI_ISR_RXOVRF_Msk (0x1UL << SWPMI_ISR_RXOVRF_Pos) /*!< 0x00000008 */ 13565 #define SWPMI_ISR_RXOVRF SWPMI_ISR_RXOVRF_Msk /*!<Receive overrun error flag */ 13566 #define SWPMI_ISR_TXUNRF_Pos (4U) 13567 #define SWPMI_ISR_TXUNRF_Msk (0x1UL << SWPMI_ISR_TXUNRF_Pos) /*!< 0x00000010 */ 13568 #define SWPMI_ISR_TXUNRF SWPMI_ISR_TXUNRF_Msk /*!<Transmit underrun error flag */ 13569 #define SWPMI_ISR_RXNE_Pos (5U) 13570 #define SWPMI_ISR_RXNE_Msk (0x1UL << SWPMI_ISR_RXNE_Pos) /*!< 0x00000020 */ 13571 #define SWPMI_ISR_RXNE SWPMI_ISR_RXNE_Msk /*!<Receive data register not empty */ 13572 #define SWPMI_ISR_TXE_Pos (6U) 13573 #define SWPMI_ISR_TXE_Msk (0x1UL << SWPMI_ISR_TXE_Pos) /*!< 0x00000040 */ 13574 #define SWPMI_ISR_TXE SWPMI_ISR_TXE_Msk /*!<Transmit data register empty */ 13575 #define SWPMI_ISR_TCF_Pos (7U) 13576 #define SWPMI_ISR_TCF_Msk (0x1UL << SWPMI_ISR_TCF_Pos) /*!< 0x00000080 */ 13577 #define SWPMI_ISR_TCF SWPMI_ISR_TCF_Msk /*!<Transfer complete flag */ 13578 #define SWPMI_ISR_SRF_Pos (8U) 13579 #define SWPMI_ISR_SRF_Msk (0x1UL << SWPMI_ISR_SRF_Pos) /*!< 0x00000100 */ 13580 #define SWPMI_ISR_SRF SWPMI_ISR_SRF_Msk /*!<Slave resume flag */ 13581 #define SWPMI_ISR_SUSP_Pos (9U) 13582 #define SWPMI_ISR_SUSP_Msk (0x1UL << SWPMI_ISR_SUSP_Pos) /*!< 0x00000200 */ 13583 #define SWPMI_ISR_SUSP SWPMI_ISR_SUSP_Msk /*!<SUSPEND flag */ 13584 #define SWPMI_ISR_DEACTF_Pos (10U) 13585 #define SWPMI_ISR_DEACTF_Msk (0x1UL << SWPMI_ISR_DEACTF_Pos) /*!< 0x00000400 */ 13586 #define SWPMI_ISR_DEACTF SWPMI_ISR_DEACTF_Msk /*!<DEACTIVATED flag */ 13587 13588 /******************* Bit definition for SWPMI_ICR register ********************/ 13589 #define SWPMI_ICR_CRXBFF_Pos (0U) 13590 #define SWPMI_ICR_CRXBFF_Msk (0x1UL << SWPMI_ICR_CRXBFF_Pos) /*!< 0x00000001 */ 13591 #define SWPMI_ICR_CRXBFF SWPMI_ICR_CRXBFF_Msk /*!<Clear receive buffer full flag */ 13592 #define SWPMI_ICR_CTXBEF_Pos (1U) 13593 #define SWPMI_ICR_CTXBEF_Msk (0x1UL << SWPMI_ICR_CTXBEF_Pos) /*!< 0x00000002 */ 13594 #define SWPMI_ICR_CTXBEF SWPMI_ICR_CTXBEF_Msk /*!<Clear transmit buffer empty flag */ 13595 #define SWPMI_ICR_CRXBERF_Pos (2U) 13596 #define SWPMI_ICR_CRXBERF_Msk (0x1UL << SWPMI_ICR_CRXBERF_Pos) /*!< 0x00000004 */ 13597 #define SWPMI_ICR_CRXBERF SWPMI_ICR_CRXBERF_Msk /*!<Clear receive CRC error flag */ 13598 #define SWPMI_ICR_CRXOVRF_Pos (3U) 13599 #define SWPMI_ICR_CRXOVRF_Msk (0x1UL << SWPMI_ICR_CRXOVRF_Pos) /*!< 0x00000008 */ 13600 #define SWPMI_ICR_CRXOVRF SWPMI_ICR_CRXOVRF_Msk /*!<Clear receive overrun error flag */ 13601 #define SWPMI_ICR_CTXUNRF_Pos (4U) 13602 #define SWPMI_ICR_CTXUNRF_Msk (0x1UL << SWPMI_ICR_CTXUNRF_Pos) /*!< 0x00000010 */ 13603 #define SWPMI_ICR_CTXUNRF SWPMI_ICR_CTXUNRF_Msk /*!<Clear transmit underrun error flag */ 13604 #define SWPMI_ICR_CTCF_Pos (7U) 13605 #define SWPMI_ICR_CTCF_Msk (0x1UL << SWPMI_ICR_CTCF_Pos) /*!< 0x00000080 */ 13606 #define SWPMI_ICR_CTCF SWPMI_ICR_CTCF_Msk /*!<Clear transfer complete flag */ 13607 #define SWPMI_ICR_CSRF_Pos (8U) 13608 #define SWPMI_ICR_CSRF_Msk (0x1UL << SWPMI_ICR_CSRF_Pos) /*!< 0x00000100 */ 13609 #define SWPMI_ICR_CSRF SWPMI_ICR_CSRF_Msk /*!<Clear slave resume flag */ 13610 13611 /******************* Bit definition for SWPMI_IER register ********************/ 13612 #define SWPMI_IER_SRIE_Pos (8U) 13613 #define SWPMI_IER_SRIE_Msk (0x1UL << SWPMI_IER_SRIE_Pos) /*!< 0x00000100 */ 13614 #define SWPMI_IER_SRIE SWPMI_IER_SRIE_Msk /*!<Slave resume interrupt enable */ 13615 #define SWPMI_IER_TCIE_Pos (7U) 13616 #define SWPMI_IER_TCIE_Msk (0x1UL << SWPMI_IER_TCIE_Pos) /*!< 0x00000080 */ 13617 #define SWPMI_IER_TCIE SWPMI_IER_TCIE_Msk /*!<Transmit complete interrupt enable */ 13618 #define SWPMI_IER_TIE_Pos (6U) 13619 #define SWPMI_IER_TIE_Msk (0x1UL << SWPMI_IER_TIE_Pos) /*!< 0x00000040 */ 13620 #define SWPMI_IER_TIE SWPMI_IER_TIE_Msk /*!<Transmit interrupt enable */ 13621 #define SWPMI_IER_RIE_Pos (5U) 13622 #define SWPMI_IER_RIE_Msk (0x1UL << SWPMI_IER_RIE_Pos) /*!< 0x00000020 */ 13623 #define SWPMI_IER_RIE SWPMI_IER_RIE_Msk /*!<Receive interrupt enable */ 13624 #define SWPMI_IER_TXUNRIE_Pos (4U) 13625 #define SWPMI_IER_TXUNRIE_Msk (0x1UL << SWPMI_IER_TXUNRIE_Pos) /*!< 0x00000010 */ 13626 #define SWPMI_IER_TXUNRIE SWPMI_IER_TXUNRIE_Msk /*!<Transmit underrun error interrupt enable */ 13627 #define SWPMI_IER_RXOVRIE_Pos (3U) 13628 #define SWPMI_IER_RXOVRIE_Msk (0x1UL << SWPMI_IER_RXOVRIE_Pos) /*!< 0x00000008 */ 13629 #define SWPMI_IER_RXOVRIE SWPMI_IER_RXOVRIE_Msk /*!<Receive overrun error interrupt enable */ 13630 #define SWPMI_IER_RXBERIE_Pos (2U) 13631 #define SWPMI_IER_RXBERIE_Msk (0x1UL << SWPMI_IER_RXBERIE_Pos) /*!< 0x00000004 */ 13632 #define SWPMI_IER_RXBERIE SWPMI_IER_RXBERIE_Msk /*!<Receive CRC error interrupt enable */ 13633 #define SWPMI_IER_TXBEIE_Pos (1U) 13634 #define SWPMI_IER_TXBEIE_Msk (0x1UL << SWPMI_IER_TXBEIE_Pos) /*!< 0x00000002 */ 13635 #define SWPMI_IER_TXBEIE SWPMI_IER_TXBEIE_Msk /*!<Transmit buffer empty interrupt enable */ 13636 #define SWPMI_IER_RXBFIE_Pos (0U) 13637 #define SWPMI_IER_RXBFIE_Msk (0x1UL << SWPMI_IER_RXBFIE_Pos) /*!< 0x00000001 */ 13638 #define SWPMI_IER_RXBFIE SWPMI_IER_RXBFIE_Msk /*!<Receive buffer full interrupt enable */ 13639 13640 /******************* Bit definition for SWPMI_RFL register ********************/ 13641 #define SWPMI_RFL_RFL_Pos (0U) 13642 #define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */ 13643 #define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */ 13644 #define SWPMI_RFL_RFL_0_1_Pos (0U) 13645 #define SWPMI_RFL_RFL_0_1_Msk (0x3UL << SWPMI_RFL_RFL_0_1_Pos) /*!< 0x00000003 */ 13646 #define SWPMI_RFL_RFL_0_1 SWPMI_RFL_RFL_0_1_Msk /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ 13647 13648 /******************* Bit definition for SWPMI_TDR register ********************/ 13649 #define SWPMI_TDR_TD_Pos (0U) 13650 #define SWPMI_TDR_TD_Msk (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos) /*!< 0xFFFFFFFF */ 13651 #define SWPMI_TDR_TD SWPMI_TDR_TD_Msk /*!<Transmit Data Register */ 13652 13653 /******************* Bit definition for SWPMI_RDR register ********************/ 13654 #define SWPMI_RDR_RD_Pos (0U) 13655 #define SWPMI_RDR_RD_Msk (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos) /*!< 0xFFFFFFFF */ 13656 #define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Receive Data Register */ 13657 13658 /******************* Bit definition for SWPMI_OR register ********************/ 13659 #define SWPMI_OR_TBYP_Pos (0U) 13660 #define SWPMI_OR_TBYP_Msk (0x1UL << SWPMI_OR_TBYP_Pos) /*!< 0x00000001 */ 13661 #define SWPMI_OR_TBYP SWPMI_OR_TBYP_Msk /*!<SWP Transceiver Bypass */ 13662 #define SWPMI_OR_CLASS_Pos (1U) 13663 #define SWPMI_OR_CLASS_Msk (0x1UL << SWPMI_OR_CLASS_Pos) /*!< 0x00000002 */ 13664 #define SWPMI_OR_CLASS SWPMI_OR_CLASS_Msk /*!<SWP Voltage Class selection */ 13665 13666 13667 /******************************************************************************/ 13668 /* */ 13669 /* Window WATCHDOG */ 13670 /* */ 13671 /******************************************************************************/ 13672 /******************* Bit definition for WWDG_CR register ********************/ 13673 #define WWDG_CR_T_Pos (0U) 13674 #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */ 13675 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */ 13676 #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */ 13677 #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */ 13678 #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */ 13679 #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */ 13680 #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */ 13681 #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */ 13682 #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */ 13683 13684 #define WWDG_CR_WDGA_Pos (7U) 13685 #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */ 13686 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */ 13687 13688 /******************* Bit definition for WWDG_CFR register *******************/ 13689 #define WWDG_CFR_W_Pos (0U) 13690 #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */ 13691 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */ 13692 #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */ 13693 #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */ 13694 #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */ 13695 #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */ 13696 #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */ 13697 #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */ 13698 #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */ 13699 13700 #define WWDG_CFR_WDGTB_Pos (7U) 13701 #define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */ 13702 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */ 13703 #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */ 13704 #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */ 13705 13706 #define WWDG_CFR_EWI_Pos (9U) 13707 #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */ 13708 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */ 13709 13710 /******************* Bit definition for WWDG_SR register ********************/ 13711 #define WWDG_SR_EWIF_Pos (0U) 13712 #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ 13713 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */ 13714 13715 13716 /******************************************************************************/ 13717 /* */ 13718 /* Debug MCU */ 13719 /* */ 13720 /******************************************************************************/ 13721 /******************** Bit definition for DBGMCU_IDCODE register *************/ 13722 #define DBGMCU_IDCODE_DEV_ID_Pos (0U) 13723 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ 13724 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk 13725 #define DBGMCU_IDCODE_REV_ID_Pos (16U) 13726 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ 13727 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk 13728 13729 /******************** Bit definition for DBGMCU_CR register *****************/ 13730 #define DBGMCU_CR_DBG_SLEEP_Pos (0U) 13731 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ 13732 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk 13733 #define DBGMCU_CR_DBG_STOP_Pos (1U) 13734 #define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ 13735 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk 13736 #define DBGMCU_CR_DBG_STANDBY_Pos (2U) 13737 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ 13738 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk 13739 #define DBGMCU_CR_TRACE_IOEN_Pos (5U) 13740 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */ 13741 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk 13742 13743 #define DBGMCU_CR_TRACE_MODE_Pos (6U) 13744 #define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */ 13745 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk 13746 #define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */ 13747 #define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */ 13748 13749 /******************** Bit definition for DBGMCU_APB1FZR1 register ***********/ 13750 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U) 13751 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ 13752 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk 13753 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos (4U) 13754 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */ 13755 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk 13756 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos (5U) 13757 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */ 13758 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk 13759 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos (10U) 13760 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ 13761 #define DBGMCU_APB1FZR1_DBG_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk 13762 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos (11U) 13763 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ 13764 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk 13765 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos (12U) 13766 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ 13767 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk 13768 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos (21U) 13769 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */ 13770 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk 13771 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos (23U) 13772 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */ 13773 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk 13774 #define DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos (25U) 13775 #define DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos) /*!< 0x02000000 */ 13776 #define DBGMCU_APB1FZR1_DBG_CAN_STOP DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk 13777 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos (31U) 13778 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos) /*!< 0x80000000 */ 13779 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk 13780 13781 /******************** Bit definition for DBGMCU_APB1FZR2 register **********/ 13782 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos (5U) 13783 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos) /*!< 0x00000020 */ 13784 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk 13785 13786 /******************** Bit definition for DBGMCU_APB2FZ register ************/ 13787 #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U) 13788 #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */ 13789 #define DBGMCU_APB2FZ_DBG_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk 13790 #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos (16U) 13791 #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */ 13792 #define DBGMCU_APB2FZ_DBG_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk 13793 #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos (17U) 13794 #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */ 13795 #define DBGMCU_APB2FZ_DBG_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk 13796 13797 /******************************************************************************/ 13798 /* */ 13799 /* USB Device FS Endpoint registers */ 13800 /* */ 13801 /******************************************************************************/ 13802 #define USB_EP0R USB_BASE /*!< endpoint 0 register address */ 13803 #define USB_EP1R (USB_BASE + 0x00000004UL) /*!< endpoint 1 register address */ 13804 #define USB_EP2R (USB_BASE + 0x00000008UL) /*!< endpoint 2 register address */ 13805 #define USB_EP3R (USB_BASE + 0x0000000CUL) /*!< endpoint 3 register address */ 13806 #define USB_EP4R (USB_BASE + 0x00000010UL) /*!< endpoint 4 register address */ 13807 #define USB_EP5R (USB_BASE + 0x00000014UL) /*!< endpoint 5 register address */ 13808 #define USB_EP6R (USB_BASE + 0x00000018UL) /*!< endpoint 6 register address */ 13809 #define USB_EP7R (USB_BASE + 0x0000001CUL) /*!< endpoint 7 register address */ 13810 13811 /* bit positions */ 13812 #define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */ 13813 #define USB_EP_DTOG_RX ((uint16_t)0x4000U) /*!< EndPoint Data TOGGLE RX */ 13814 #define USB_EPRX_STAT ((uint16_t)0x3000U) /*!< EndPoint RX STATus bit field */ 13815 #define USB_EP_SETUP ((uint16_t)0x0800U) /*!< EndPoint SETUP */ 13816 #define USB_EP_T_FIELD ((uint16_t)0x0600U) /*!< EndPoint TYPE */ 13817 #define USB_EP_KIND ((uint16_t)0x0100U) /*!< EndPoint KIND */ 13818 #define USB_EP_CTR_TX ((uint16_t)0x0080U) /*!< EndPoint Correct TRansfer TX */ 13819 #define USB_EP_DTOG_TX ((uint16_t)0x0040U) /*!< EndPoint Data TOGGLE TX */ 13820 #define USB_EPTX_STAT ((uint16_t)0x0030U) /*!< EndPoint TX STATus bit field */ 13821 #define USB_EPADDR_FIELD ((uint16_t)0x000FU) /*!< EndPoint ADDRess FIELD */ 13822 13823 /* EndPoint REGister MASK (no toggle fields) */ 13824 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD) 13825 /*!< EP_TYPE[1:0] EndPoint TYPE */ 13826 #define USB_EP_TYPE_MASK ((uint16_t)0x0600U) /*!< EndPoint TYPE Mask */ 13827 #define USB_EP_BULK ((uint16_t)0x0000U) /*!< EndPoint BULK */ 13828 #define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */ 13829 #define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */ 13830 #define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */ 13831 #define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK) 13832 13833 #define USB_EPKIND_MASK ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */ 13834 /*!< STAT_TX[1:0] STATus for TX transfer */ 13835 #define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */ 13836 #define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */ 13837 #define USB_EP_TX_NAK ((uint16_t)0x0020U) /*!< EndPoint TX NAKed */ 13838 #define USB_EP_TX_VALID ((uint16_t)0x0030U) /*!< EndPoint TX VALID */ 13839 #define USB_EPTX_DTOG1 ((uint16_t)0x0010U) /*!< EndPoint TX Data TOGgle bit1 */ 13840 #define USB_EPTX_DTOG2 ((uint16_t)0x0020U) /*!< EndPoint TX Data TOGgle bit2 */ 13841 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK) 13842 /*!< STAT_RX[1:0] STATus for RX transfer */ 13843 #define USB_EP_RX_DIS ((uint16_t)0x0000U) /*!< EndPoint RX DISabled */ 13844 #define USB_EP_RX_STALL ((uint16_t)0x1000U) /*!< EndPoint RX STALLed */ 13845 #define USB_EP_RX_NAK ((uint16_t)0x2000U) /*!< EndPoint RX NAKed */ 13846 #define USB_EP_RX_VALID ((uint16_t)0x3000U) /*!< EndPoint RX VALID */ 13847 #define USB_EPRX_DTOG1 ((uint16_t)0x1000U) /*!< EndPoint RX Data TOGgle bit1 */ 13848 #define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */ 13849 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK) 13850 13851 /******************************************************************************/ 13852 /* */ 13853 /* USB Device FS General registers */ 13854 /* */ 13855 /******************************************************************************/ 13856 #define USB_CNTR (USB_BASE + 0x00000040UL) /*!< Control register */ 13857 #define USB_ISTR (USB_BASE + 0x00000044UL) /*!< Interrupt status register */ 13858 #define USB_FNR (USB_BASE + 0x00000048UL) /*!< Frame number register */ 13859 #define USB_DADDR (USB_BASE + 0x0000004CUL) /*!< Device address register */ 13860 #define USB_BTABLE (USB_BASE + 0x00000050UL) /*!< Buffer Table address register */ 13861 #define USB_LPMCSR (USB_BASE + 0x00000054UL) /*!< LPM Control and Status register */ 13862 #define USB_BCDR (USB_BASE + 0x00000058UL) /*!< Battery Charging detector register*/ 13863 13864 /****************** Bits definition for USB_CNTR register *******************/ 13865 #define USB_CNTR_CTRM ((uint16_t)0x8000U) /*!< Correct TRansfer Mask */ 13866 #define USB_CNTR_PMAOVRM ((uint16_t)0x4000U) /*!< DMA OVeR/underrun Mask */ 13867 #define USB_CNTR_ERRM ((uint16_t)0x2000U) /*!< ERRor Mask */ 13868 #define USB_CNTR_WKUPM ((uint16_t)0x1000U) /*!< WaKe UP Mask */ 13869 #define USB_CNTR_SUSPM ((uint16_t)0x0800U) /*!< SUSPend Mask */ 13870 #define USB_CNTR_RESETM ((uint16_t)0x0400U) /*!< RESET Mask */ 13871 #define USB_CNTR_SOFM ((uint16_t)0x0200U) /*!< Start Of Frame Mask */ 13872 #define USB_CNTR_ESOFM ((uint16_t)0x0100U) /*!< Expected Start Of Frame Mask */ 13873 #define USB_CNTR_L1REQM ((uint16_t)0x0080U) /*!< LPM L1 state request interrupt mask */ 13874 #define USB_CNTR_L1RESUME ((uint16_t)0x0020U) /*!< LPM L1 Resume request */ 13875 #define USB_CNTR_RESUME ((uint16_t)0x0010U) /*!< RESUME request */ 13876 #define USB_CNTR_FSUSP ((uint16_t)0x0008U) /*!< Force SUSPend */ 13877 #define USB_CNTR_LPMODE ((uint16_t)0x0004U) /*!< Low-power MODE */ 13878 #define USB_CNTR_PDWN ((uint16_t)0x0002U) /*!< Power DoWN */ 13879 #define USB_CNTR_FRES ((uint16_t)0x0001U) /*!< Force USB RESet */ 13880 13881 /****************** Bits definition for USB_ISTR register *******************/ 13882 #define USB_ISTR_EP_ID ((uint16_t)0x000FU) /*!< EndPoint IDentifier (read-only bit) */ 13883 #define USB_ISTR_DIR ((uint16_t)0x0010U) /*!< DIRection of transaction (read-only bit) */ 13884 #define USB_ISTR_L1REQ ((uint16_t)0x0080U) /*!< LPM L1 state request */ 13885 #define USB_ISTR_ESOF ((uint16_t)0x0100U) /*!< Expected Start Of Frame (clear-only bit) */ 13886 #define USB_ISTR_SOF ((uint16_t)0x0200U) /*!< Start Of Frame (clear-only bit) */ 13887 #define USB_ISTR_RESET ((uint16_t)0x0400U) /*!< RESET (clear-only bit) */ 13888 #define USB_ISTR_SUSP ((uint16_t)0x0800U) /*!< SUSPend (clear-only bit) */ 13889 #define USB_ISTR_WKUP ((uint16_t)0x1000U) /*!< WaKe UP (clear-only bit) */ 13890 #define USB_ISTR_ERR ((uint16_t)0x2000U) /*!< ERRor (clear-only bit) */ 13891 #define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun (clear-only bit) */ 13892 #define USB_ISTR_CTR ((uint16_t)0x8000U) /*!< Correct TRansfer (clear-only bit) */ 13893 13894 #define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */ 13895 #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */ 13896 #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */ 13897 #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */ 13898 #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */ 13899 #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */ 13900 #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */ 13901 #define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/ 13902 #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */ 13903 13904 /****************** Bits definition for USB_FNR register ********************/ 13905 #define USB_FNR_FN ((uint16_t)0x07FFU) /*!< Frame Number */ 13906 #define USB_FNR_LSOF ((uint16_t)0x1800U) /*!< Lost SOF */ 13907 #define USB_FNR_LCK ((uint16_t)0x2000U) /*!< LoCKed */ 13908 #define USB_FNR_RXDM ((uint16_t)0x4000U) /*!< status of D- data line */ 13909 #define USB_FNR_RXDP ((uint16_t)0x8000U) /*!< status of D+ data line */ 13910 13911 /****************** Bits definition for USB_DADDR register ****************/ 13912 #define USB_DADDR_ADD ((uint8_t)0x7FU) /*!< ADD[6:0] bits (Device Address) */ 13913 #define USB_DADDR_ADD0 ((uint8_t)0x01U) /*!< Bit 0 */ 13914 #define USB_DADDR_ADD1 ((uint8_t)0x02U) /*!< Bit 1 */ 13915 #define USB_DADDR_ADD2 ((uint8_t)0x04U) /*!< Bit 2 */ 13916 #define USB_DADDR_ADD3 ((uint8_t)0x08U) /*!< Bit 3 */ 13917 #define USB_DADDR_ADD4 ((uint8_t)0x10U) /*!< Bit 4 */ 13918 #define USB_DADDR_ADD5 ((uint8_t)0x20U) /*!< Bit 5 */ 13919 #define USB_DADDR_ADD6 ((uint8_t)0x40U) /*!< Bit 6 */ 13920 13921 #define USB_DADDR_EF ((uint8_t)0x80U) /*!< Enable Function */ 13922 13923 /****************** Bit definition for USB_BTABLE register ******************/ 13924 #define USB_BTABLE_BTABLE ((uint16_t)0xFFF8U) /*!< Buffer Table */ 13925 13926 /****************** Bits definition for USB_BCDR register *******************/ 13927 #define USB_BCDR_BCDEN ((uint16_t)0x0001U) /*!< Battery charging detector (BCD) enable */ 13928 #define USB_BCDR_DCDEN ((uint16_t)0x0002U) /*!< Data contact detection (DCD) mode enable */ 13929 #define USB_BCDR_PDEN ((uint16_t)0x0004U) /*!< Primary detection (PD) mode enable */ 13930 #define USB_BCDR_SDEN ((uint16_t)0x0008U) /*!< Secondary detection (SD) mode enable */ 13931 #define USB_BCDR_DCDET ((uint16_t)0x0010U) /*!< Data contact detection (DCD) status */ 13932 #define USB_BCDR_PDET ((uint16_t)0x0020U) /*!< Primary detection (PD) status */ 13933 #define USB_BCDR_SDET ((uint16_t)0x0040U) /*!< Secondary detection (SD) status */ 13934 #define USB_BCDR_PS2DET ((uint16_t)0x0080U) /*!< PS2 port or proprietary charger detected */ 13935 #define USB_BCDR_DPPU ((uint16_t)0x8000U) /*!< DP Pull-up Enable */ 13936 13937 /******************* Bit definition for LPMCSR register *********************/ 13938 #define USB_LPMCSR_LMPEN ((uint16_t)0x0001U) /*!< LPM support enable */ 13939 #define USB_LPMCSR_LPMACK ((uint16_t)0x0002U) /*!< LPM Token acknowledge enable*/ 13940 #define USB_LPMCSR_REMWAKE ((uint16_t)0x0008U) /*!< bRemoteWake value received with last ACKed LPM Token */ 13941 #define USB_LPMCSR_BESL ((uint16_t)0x00F0U) /*!< BESL value received with last ACKed LPM Token */ 13942 13943 /*!< Buffer descriptor table */ 13944 /***************** Bit definition for USB_ADDR0_TX register *****************/ 13945 #define USB_ADDR0_TX_ADDR0_TX_Pos (1U) 13946 #define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */ 13947 #define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */ 13948 13949 /***************** Bit definition for USB_ADDR1_TX register *****************/ 13950 #define USB_ADDR1_TX_ADDR1_TX_Pos (1U) 13951 #define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */ 13952 #define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */ 13953 13954 /***************** Bit definition for USB_ADDR2_TX register *****************/ 13955 #define USB_ADDR2_TX_ADDR2_TX_Pos (1U) 13956 #define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */ 13957 #define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */ 13958 13959 /***************** Bit definition for USB_ADDR3_TX register *****************/ 13960 #define USB_ADDR3_TX_ADDR3_TX_Pos (1U) 13961 #define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */ 13962 #define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */ 13963 13964 /***************** Bit definition for USB_ADDR4_TX register *****************/ 13965 #define USB_ADDR4_TX_ADDR4_TX_Pos (1U) 13966 #define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */ 13967 #define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */ 13968 13969 /***************** Bit definition for USB_ADDR5_TX register *****************/ 13970 #define USB_ADDR5_TX_ADDR5_TX_Pos (1U) 13971 #define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */ 13972 #define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */ 13973 13974 /***************** Bit definition for USB_ADDR6_TX register *****************/ 13975 #define USB_ADDR6_TX_ADDR6_TX_Pos (1U) 13976 #define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */ 13977 #define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */ 13978 13979 /***************** Bit definition for USB_ADDR7_TX register *****************/ 13980 #define USB_ADDR7_TX_ADDR7_TX_Pos (1U) 13981 #define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */ 13982 #define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */ 13983 13984 /*----------------------------------------------------------------------------*/ 13985 13986 /***************** Bit definition for USB_COUNT0_TX register ****************/ 13987 #define USB_COUNT0_TX_COUNT0_TX_Pos (0U) 13988 #define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */ 13989 #define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */ 13990 13991 /***************** Bit definition for USB_COUNT1_TX register ****************/ 13992 #define USB_COUNT1_TX_COUNT1_TX_Pos (0U) 13993 #define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */ 13994 #define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */ 13995 13996 /***************** Bit definition for USB_COUNT2_TX register ****************/ 13997 #define USB_COUNT2_TX_COUNT2_TX_Pos (0U) 13998 #define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */ 13999 #define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */ 14000 14001 /***************** Bit definition for USB_COUNT3_TX register ****************/ 14002 #define USB_COUNT3_TX_COUNT3_TX_Pos (0U) 14003 #define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */ 14004 #define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */ 14005 14006 /***************** Bit definition for USB_COUNT4_TX register ****************/ 14007 #define USB_COUNT4_TX_COUNT4_TX_Pos (0U) 14008 #define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */ 14009 #define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */ 14010 14011 /***************** Bit definition for USB_COUNT5_TX register ****************/ 14012 #define USB_COUNT5_TX_COUNT5_TX_Pos (0U) 14013 #define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */ 14014 #define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */ 14015 14016 /***************** Bit definition for USB_COUNT6_TX register ****************/ 14017 #define USB_COUNT6_TX_COUNT6_TX_Pos (0U) 14018 #define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */ 14019 #define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */ 14020 14021 /***************** Bit definition for USB_COUNT7_TX register ****************/ 14022 #define USB_COUNT7_TX_COUNT7_TX_Pos (0U) 14023 #define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */ 14024 #define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */ 14025 14026 /*----------------------------------------------------------------------------*/ 14027 14028 /**************** Bit definition for USB_COUNT0_TX_0 register ***************/ 14029 #define USB_COUNT0_TX_0_COUNT0_TX_0 (0x000003FFUL) /*!< Transmission Byte Count 0 (low) */ 14030 14031 /**************** Bit definition for USB_COUNT0_TX_1 register ***************/ 14032 #define USB_COUNT0_TX_1_COUNT0_TX_1 (0x03FF0000UL) /*!< Transmission Byte Count 0 (high) */ 14033 14034 /**************** Bit definition for USB_COUNT1_TX_0 register ***************/ 14035 #define USB_COUNT1_TX_0_COUNT1_TX_0 (0x000003FFUL) /*!< Transmission Byte Count 1 (low) */ 14036 14037 /**************** Bit definition for USB_COUNT1_TX_1 register ***************/ 14038 #define USB_COUNT1_TX_1_COUNT1_TX_1 (0x03FF0000UL) /*!< Transmission Byte Count 1 (high) */ 14039 14040 /**************** Bit definition for USB_COUNT2_TX_0 register ***************/ 14041 #define USB_COUNT2_TX_0_COUNT2_TX_0 (0x000003FFUL) /*!< Transmission Byte Count 2 (low) */ 14042 14043 /**************** Bit definition for USB_COUNT2_TX_1 register ***************/ 14044 #define USB_COUNT2_TX_1_COUNT2_TX_1 (0x03FF0000UL) /*!< Transmission Byte Count 2 (high) */ 14045 14046 /**************** Bit definition for USB_COUNT3_TX_0 register ***************/ 14047 #define USB_COUNT3_TX_0_COUNT3_TX_0 (0x000003FFUL) /*!< Transmission Byte Count 3 (low) */ 14048 14049 /**************** Bit definition for USB_COUNT3_TX_1 register ***************/ 14050 #define USB_COUNT3_TX_1_COUNT3_TX_1 (0x03FF0000UL) /*!< Transmission Byte Count 3 (high) */ 14051 14052 /**************** Bit definition for USB_COUNT4_TX_0 register ***************/ 14053 #define USB_COUNT4_TX_0_COUNT4_TX_0 (0x000003FFUL) /*!< Transmission Byte Count 4 (low) */ 14054 14055 /**************** Bit definition for USB_COUNT4_TX_1 register ***************/ 14056 #define USB_COUNT4_TX_1_COUNT4_TX_1 (0x03FF0000UL) /*!< Transmission Byte Count 4 (high) */ 14057 14058 /**************** Bit definition for USB_COUNT5_TX_0 register ***************/ 14059 #define USB_COUNT5_TX_0_COUNT5_TX_0 (0x000003FFUL) /*!< Transmission Byte Count 5 (low) */ 14060 14061 /**************** Bit definition for USB_COUNT5_TX_1 register ***************/ 14062 #define USB_COUNT5_TX_1_COUNT5_TX_1 (0x03FF0000UL) /*!< Transmission Byte Count 5 (high) */ 14063 14064 /**************** Bit definition for USB_COUNT6_TX_0 register ***************/ 14065 #define USB_COUNT6_TX_0_COUNT6_TX_0 (0x000003FFUL) /*!< Transmission Byte Count 6 (low) */ 14066 14067 /**************** Bit definition for USB_COUNT6_TX_1 register ***************/ 14068 #define USB_COUNT6_TX_1_COUNT6_TX_1 (0x03FF0000UL) /*!< Transmission Byte Count 6 (high) */ 14069 14070 /**************** Bit definition for USB_COUNT7_TX_0 register ***************/ 14071 #define USB_COUNT7_TX_0_COUNT7_TX_0 (0x000003FFUL) /*!< Transmission Byte Count 7 (low) */ 14072 14073 /**************** Bit definition for USB_COUNT7_TX_1 register ***************/ 14074 #define USB_COUNT7_TX_1_COUNT7_TX_1 (0x03FF0000UL) /*!< Transmission Byte Count 7 (high) */ 14075 14076 /*----------------------------------------------------------------------------*/ 14077 14078 /***************** Bit definition for USB_ADDR0_RX register *****************/ 14079 #define USB_ADDR0_RX_ADDR0_RX_Pos (1U) 14080 #define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */ 14081 #define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */ 14082 14083 /***************** Bit definition for USB_ADDR1_RX register *****************/ 14084 #define USB_ADDR1_RX_ADDR1_RX_Pos (1U) 14085 #define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */ 14086 #define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */ 14087 14088 /***************** Bit definition for USB_ADDR2_RX register *****************/ 14089 #define USB_ADDR2_RX_ADDR2_RX_Pos (1U) 14090 #define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */ 14091 #define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */ 14092 14093 /***************** Bit definition for USB_ADDR3_RX register *****************/ 14094 #define USB_ADDR3_RX_ADDR3_RX_Pos (1U) 14095 #define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */ 14096 #define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */ 14097 14098 /***************** Bit definition for USB_ADDR4_RX register *****************/ 14099 #define USB_ADDR4_RX_ADDR4_RX_Pos (1U) 14100 #define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */ 14101 #define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */ 14102 14103 /***************** Bit definition for USB_ADDR5_RX register *****************/ 14104 #define USB_ADDR5_RX_ADDR5_RX_Pos (1U) 14105 #define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */ 14106 #define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */ 14107 14108 /***************** Bit definition for USB_ADDR6_RX register *****************/ 14109 #define USB_ADDR6_RX_ADDR6_RX_Pos (1U) 14110 #define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */ 14111 #define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */ 14112 14113 /***************** Bit definition for USB_ADDR7_RX register *****************/ 14114 #define USB_ADDR7_RX_ADDR7_RX_Pos (1U) 14115 #define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */ 14116 #define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */ 14117 14118 /*----------------------------------------------------------------------------*/ 14119 14120 /***************** Bit definition for USB_COUNT0_RX register ****************/ 14121 #define USB_COUNT0_RX_COUNT0_RX_Pos (0U) 14122 #define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */ 14123 #define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */ 14124 14125 #define USB_COUNT0_RX_NUM_BLOCK_Pos (10U) 14126 #define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 14127 #define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 14128 #define USB_COUNT0_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 14129 #define USB_COUNT0_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 14130 #define USB_COUNT0_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 14131 #define USB_COUNT0_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 14132 #define USB_COUNT0_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 14133 14134 #define USB_COUNT0_RX_BLSIZE_Pos (15U) 14135 #define USB_COUNT0_RX_BLSIZE_Msk (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */ 14136 #define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */ 14137 14138 /***************** Bit definition for USB_COUNT1_RX register ****************/ 14139 #define USB_COUNT1_RX_COUNT1_RX_Pos (0U) 14140 #define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */ 14141 #define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */ 14142 14143 #define USB_COUNT1_RX_NUM_BLOCK_Pos (10U) 14144 #define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 14145 #define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 14146 #define USB_COUNT1_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 14147 #define USB_COUNT1_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 14148 #define USB_COUNT1_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 14149 #define USB_COUNT1_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 14150 #define USB_COUNT1_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 14151 14152 #define USB_COUNT1_RX_BLSIZE_Pos (15U) 14153 #define USB_COUNT1_RX_BLSIZE_Msk (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */ 14154 #define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */ 14155 14156 /***************** Bit definition for USB_COUNT2_RX register ****************/ 14157 #define USB_COUNT2_RX_COUNT2_RX_Pos (0U) 14158 #define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */ 14159 #define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */ 14160 14161 #define USB_COUNT2_RX_NUM_BLOCK_Pos (10U) 14162 #define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 14163 #define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 14164 #define USB_COUNT2_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 14165 #define USB_COUNT2_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 14166 #define USB_COUNT2_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 14167 #define USB_COUNT2_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 14168 #define USB_COUNT2_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 14169 14170 #define USB_COUNT2_RX_BLSIZE_Pos (15U) 14171 #define USB_COUNT2_RX_BLSIZE_Msk (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */ 14172 #define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */ 14173 14174 /***************** Bit definition for USB_COUNT3_RX register ****************/ 14175 #define USB_COUNT3_RX_COUNT3_RX_Pos (0U) 14176 #define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */ 14177 #define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */ 14178 14179 #define USB_COUNT3_RX_NUM_BLOCK_Pos (10U) 14180 #define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 14181 #define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 14182 #define USB_COUNT3_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 14183 #define USB_COUNT3_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 14184 #define USB_COUNT3_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 14185 #define USB_COUNT3_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 14186 #define USB_COUNT3_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 14187 14188 #define USB_COUNT3_RX_BLSIZE_Pos (15U) 14189 #define USB_COUNT3_RX_BLSIZE_Msk (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */ 14190 #define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */ 14191 14192 /***************** Bit definition for USB_COUNT4_RX register ****************/ 14193 #define USB_COUNT4_RX_COUNT4_RX_Pos (0U) 14194 #define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */ 14195 #define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */ 14196 14197 #define USB_COUNT4_RX_NUM_BLOCK_Pos (10U) 14198 #define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 14199 #define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 14200 #define USB_COUNT4_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 14201 #define USB_COUNT4_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 14202 #define USB_COUNT4_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 14203 #define USB_COUNT4_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 14204 #define USB_COUNT4_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 14205 14206 #define USB_COUNT4_RX_BLSIZE_Pos (15U) 14207 #define USB_COUNT4_RX_BLSIZE_Msk (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */ 14208 #define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */ 14209 14210 /***************** Bit definition for USB_COUNT5_RX register ****************/ 14211 #define USB_COUNT5_RX_COUNT5_RX_Pos (0U) 14212 #define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */ 14213 #define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */ 14214 14215 #define USB_COUNT5_RX_NUM_BLOCK_Pos (10U) 14216 #define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 14217 #define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 14218 #define USB_COUNT5_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 14219 #define USB_COUNT5_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 14220 #define USB_COUNT5_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 14221 #define USB_COUNT5_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 14222 #define USB_COUNT5_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 14223 14224 #define USB_COUNT5_RX_BLSIZE_Pos (15U) 14225 #define USB_COUNT5_RX_BLSIZE_Msk (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */ 14226 #define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */ 14227 14228 /***************** Bit definition for USB_COUNT6_RX register ****************/ 14229 #define USB_COUNT6_RX_COUNT6_RX_Pos (0U) 14230 #define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */ 14231 #define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */ 14232 14233 #define USB_COUNT6_RX_NUM_BLOCK_Pos (10U) 14234 #define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 14235 #define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 14236 #define USB_COUNT6_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 14237 #define USB_COUNT6_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 14238 #define USB_COUNT6_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 14239 #define USB_COUNT6_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 14240 #define USB_COUNT6_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 14241 14242 #define USB_COUNT6_RX_BLSIZE_Pos (15U) 14243 #define USB_COUNT6_RX_BLSIZE_Msk (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */ 14244 #define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */ 14245 14246 /***************** Bit definition for USB_COUNT7_RX register ****************/ 14247 #define USB_COUNT7_RX_COUNT7_RX_Pos (0U) 14248 #define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */ 14249 #define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */ 14250 14251 #define USB_COUNT7_RX_NUM_BLOCK_Pos (10U) 14252 #define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 14253 #define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 14254 #define USB_COUNT7_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 14255 #define USB_COUNT7_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 14256 #define USB_COUNT7_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 14257 #define USB_COUNT7_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 14258 #define USB_COUNT7_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 14259 14260 #define USB_COUNT7_RX_BLSIZE_Pos (15U) 14261 #define USB_COUNT7_RX_BLSIZE_Msk (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */ 14262 #define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */ 14263 14264 /*----------------------------------------------------------------------------*/ 14265 14266 /**************** Bit definition for USB_COUNT0_RX_0 register ***************/ 14267 #define USB_COUNT0_RX_0_COUNT0_RX_0 (0x000003FFUL) /*!< Reception Byte Count (low) */ 14268 14269 #define USB_COUNT0_RX_0_NUM_BLOCK_0 (0x00007C00UL) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 14270 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0 (0x00000400UL) /*!< Bit 0 */ 14271 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1 (0x00000800UL) /*!< Bit 1 */ 14272 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2 (0x00001000UL) /*!< Bit 2 */ 14273 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3 (0x00002000UL) /*!< Bit 3 */ 14274 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4 (0x00004000UL) /*!< Bit 4 */ 14275 14276 #define USB_COUNT0_RX_0_BLSIZE_0 (0x00008000UL) /*!< BLock SIZE (low) */ 14277 14278 /**************** Bit definition for USB_COUNT0_RX_1 register ***************/ 14279 #define USB_COUNT0_RX_1_COUNT0_RX_1 (0x03FF0000UL) /*!< Reception Byte Count (high) */ 14280 14281 #define USB_COUNT0_RX_1_NUM_BLOCK_1 (0x7C000000UL) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 14282 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0 (0x04000000UL) /*!< Bit 1 */ 14283 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1 (0x08000000UL) /*!< Bit 1 */ 14284 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2 (0x10000000UL) /*!< Bit 2 */ 14285 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3 (0x20000000UL) /*!< Bit 3 */ 14286 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4 (0x40000000UL) /*!< Bit 4 */ 14287 14288 #define USB_COUNT0_RX_1_BLSIZE_1 (0x80000000UL) /*!< BLock SIZE (high) */ 14289 14290 /**************** Bit definition for USB_COUNT1_RX_0 register ***************/ 14291 #define USB_COUNT1_RX_0_COUNT1_RX_0 (0x000003FFUL) /*!< Reception Byte Count (low) */ 14292 14293 #define USB_COUNT1_RX_0_NUM_BLOCK_0 (0x00007C00UL) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 14294 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0 (0x00000400UL) /*!< Bit 0 */ 14295 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1 (0x00000800UL) /*!< Bit 1 */ 14296 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2 (0x00001000UL) /*!< Bit 2 */ 14297 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3 (0x00002000UL) /*!< Bit 3 */ 14298 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4 (0x00004000UL) /*!< Bit 4 */ 14299 14300 #define USB_COUNT1_RX_0_BLSIZE_0 (0x00008000UL) /*!< BLock SIZE (low) */ 14301 14302 /**************** Bit definition for USB_COUNT1_RX_1 register ***************/ 14303 #define USB_COUNT1_RX_1_COUNT1_RX_1 (0x03FF0000UL) /*!< Reception Byte Count (high) */ 14304 14305 #define USB_COUNT1_RX_1_NUM_BLOCK_1 (0x7C000000UL) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 14306 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0 (0x04000000UL) /*!< Bit 0 */ 14307 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1 (0x08000000UL) /*!< Bit 1 */ 14308 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2 (0x10000000UL) /*!< Bit 2 */ 14309 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3 (0x20000000UL) /*!< Bit 3 */ 14310 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4 (0x40000000UL) /*!< Bit 4 */ 14311 14312 #define USB_COUNT1_RX_1_BLSIZE_1 (0x80000000UL) /*!< BLock SIZE (high) */ 14313 14314 /**************** Bit definition for USB_COUNT2_RX_0 register ***************/ 14315 #define USB_COUNT2_RX_0_COUNT2_RX_0 (0x000003FFUL) /*!< Reception Byte Count (low) */ 14316 14317 #define USB_COUNT2_RX_0_NUM_BLOCK_0 (0x00007C00UL) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 14318 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0 (0x00000400UL) /*!< Bit 0 */ 14319 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1 (0x00000800UL) /*!< Bit 1 */ 14320 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2 (0x00001000UL) /*!< Bit 2 */ 14321 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3 (0x00002000UL) /*!< Bit 3 */ 14322 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4 (0x00004000UL) /*!< Bit 4 */ 14323 14324 #define USB_COUNT2_RX_0_BLSIZE_0 (0x00008000UL) /*!< BLock SIZE (low) */ 14325 14326 /**************** Bit definition for USB_COUNT2_RX_1 register ***************/ 14327 #define USB_COUNT2_RX_1_COUNT2_RX_1 (0x03FF0000UL) /*!< Reception Byte Count (high) */ 14328 14329 #define USB_COUNT2_RX_1_NUM_BLOCK_1 (0x7C000000UL) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 14330 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0 (0x04000000UL) /*!< Bit 0 */ 14331 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1 (0x08000000UL) /*!< Bit 1 */ 14332 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2 (0x10000000UL) /*!< Bit 2 */ 14333 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3 (0x20000000UL) /*!< Bit 3 */ 14334 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4 (0x40000000UL) /*!< Bit 4 */ 14335 14336 #define USB_COUNT2_RX_1_BLSIZE_1 (0x80000000UL) /*!< BLock SIZE (high) */ 14337 14338 /**************** Bit definition for USB_COUNT3_RX_0 register ***************/ 14339 #define USB_COUNT3_RX_0_COUNT3_RX_0 (0x000003FFUL) /*!< Reception Byte Count (low) */ 14340 14341 #define USB_COUNT3_RX_0_NUM_BLOCK_0 (0x00007C00UL) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 14342 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0 (0x00000400UL) /*!< Bit 0 */ 14343 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1 (0x00000800UL) /*!< Bit 1 */ 14344 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2 (0x00001000UL) /*!< Bit 2 */ 14345 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3 (0x00002000UL) /*!< Bit 3 */ 14346 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4 (0x00004000UL) /*!< Bit 4 */ 14347 14348 #define USB_COUNT3_RX_0_BLSIZE_0 (0x00008000UL) /*!< BLock SIZE (low) */ 14349 14350 /**************** Bit definition for USB_COUNT3_RX_1 register ***************/ 14351 #define USB_COUNT3_RX_1_COUNT3_RX_1 (0x03FF0000UL) /*!< Reception Byte Count (high) */ 14352 14353 #define USB_COUNT3_RX_1_NUM_BLOCK_1 (0x7C000000UL) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 14354 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0 (0x04000000UL) /*!< Bit 0 */ 14355 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1 (0x08000000UL) /*!< Bit 1 */ 14356 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2 (0x10000000UL) /*!< Bit 2 */ 14357 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3 (0x20000000UL) /*!< Bit 3 */ 14358 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4 (0x40000000UL) /*!< Bit 4 */ 14359 14360 #define USB_COUNT3_RX_1_BLSIZE_1 (0x80000000UL) /*!< BLock SIZE (high) */ 14361 14362 /**************** Bit definition for USB_COUNT4_RX_0 register ***************/ 14363 #define USB_COUNT4_RX_0_COUNT4_RX_0 (0x000003FFUL) /*!< Reception Byte Count (low) */ 14364 14365 #define USB_COUNT4_RX_0_NUM_BLOCK_0 (0x00007C00UL) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 14366 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0 (0x00000400UL) /*!< Bit 0 */ 14367 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1 (0x00000800UL) /*!< Bit 1 */ 14368 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2 (0x00001000UL) /*!< Bit 2 */ 14369 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3 (0x00002000UL) /*!< Bit 3 */ 14370 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4 (0x00004000UL) /*!< Bit 4 */ 14371 14372 #define USB_COUNT4_RX_0_BLSIZE_0 (0x00008000UL) /*!< BLock SIZE (low) */ 14373 14374 /**************** Bit definition for USB_COUNT4_RX_1 register ***************/ 14375 #define USB_COUNT4_RX_1_COUNT4_RX_1 (0x03FF0000UL) /*!< Reception Byte Count (high) */ 14376 14377 #define USB_COUNT4_RX_1_NUM_BLOCK_1 (0x7C000000UL) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 14378 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0 (0x04000000UL) /*!< Bit 0 */ 14379 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1 (0x08000000UL) /*!< Bit 1 */ 14380 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2 (0x10000000UL) /*!< Bit 2 */ 14381 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3 (0x20000000UL) /*!< Bit 3 */ 14382 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4 (0x40000000UL) /*!< Bit 4 */ 14383 14384 #define USB_COUNT4_RX_1_BLSIZE_1 (0x80000000UL) /*!< BLock SIZE (high) */ 14385 14386 /**************** Bit definition for USB_COUNT5_RX_0 register ***************/ 14387 #define USB_COUNT5_RX_0_COUNT5_RX_0 (0x000003FFUL) /*!< Reception Byte Count (low) */ 14388 14389 #define USB_COUNT5_RX_0_NUM_BLOCK_0 (0x00007C00UL) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 14390 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0 (0x00000400UL) /*!< Bit 0 */ 14391 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1 (0x00000800UL) /*!< Bit 1 */ 14392 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2 (0x00001000UL) /*!< Bit 2 */ 14393 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3 (0x00002000UL) /*!< Bit 3 */ 14394 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4 (0x00004000UL) /*!< Bit 4 */ 14395 14396 #define USB_COUNT5_RX_0_BLSIZE_0 (0x00008000UL) /*!< BLock SIZE (low) */ 14397 14398 /**************** Bit definition for USB_COUNT5_RX_1 register ***************/ 14399 #define USB_COUNT5_RX_1_COUNT5_RX_1 (0x03FF0000UL) /*!< Reception Byte Count (high) */ 14400 14401 #define USB_COUNT5_RX_1_NUM_BLOCK_1 (0x7C000000UL) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 14402 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0 (0x04000000UL) /*!< Bit 0 */ 14403 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1 (0x08000000UL) /*!< Bit 1 */ 14404 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2 (0x10000000UL) /*!< Bit 2 */ 14405 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3 (0x20000000UL) /*!< Bit 3 */ 14406 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4 (0x40000000UL) /*!< Bit 4 */ 14407 14408 #define USB_COUNT5_RX_1_BLSIZE_1 (0x80000000UL) /*!< BLock SIZE (high) */ 14409 14410 /*************** Bit definition for USB_COUNT6_RX_0 register ***************/ 14411 #define USB_COUNT6_RX_0_COUNT6_RX_0 (0x000003FFUL) /*!< Reception Byte Count (low) */ 14412 14413 #define USB_COUNT6_RX_0_NUM_BLOCK_0 (0x00007C00UL) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 14414 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0 (0x00000400UL) /*!< Bit 0 */ 14415 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1 (0x00000800UL) /*!< Bit 1 */ 14416 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2 (0x00001000UL) /*!< Bit 2 */ 14417 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3 (0x00002000UL) /*!< Bit 3 */ 14418 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4 (0x00004000UL) /*!< Bit 4 */ 14419 14420 #define USB_COUNT6_RX_0_BLSIZE_0 (0x00008000UL) /*!< BLock SIZE (low) */ 14421 14422 /**************** Bit definition for USB_COUNT6_RX_1 register ***************/ 14423 #define USB_COUNT6_RX_1_COUNT6_RX_1 (0x03FF0000UL) /*!< Reception Byte Count (high) */ 14424 14425 #define USB_COUNT6_RX_1_NUM_BLOCK_1 (0x7C000000UL) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 14426 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0 (0x04000000UL) /*!< Bit 0 */ 14427 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1 (0x08000000UL) /*!< Bit 1 */ 14428 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2 (0x10000000UL) /*!< Bit 2 */ 14429 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3 (0x20000000UL) /*!< Bit 3 */ 14430 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4 (0x40000000UL) /*!< Bit 4 */ 14431 14432 #define USB_COUNT6_RX_1_BLSIZE_1 (0x80000000UL) /*!< BLock SIZE (high) */ 14433 14434 /*************** Bit definition for USB_COUNT7_RX_0 register ****************/ 14435 #define USB_COUNT7_RX_0_COUNT7_RX_0 (0x000003FFUL) /*!< Reception Byte Count (low) */ 14436 14437 #define USB_COUNT7_RX_0_NUM_BLOCK_0 (0x00007C00UL) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 14438 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0 (0x00000400UL) /*!< Bit 0 */ 14439 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1 (0x00000800UL) /*!< Bit 1 */ 14440 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2 (0x00001000UL) /*!< Bit 2 */ 14441 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3 (0x00002000UL) /*!< Bit 3 */ 14442 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4 (0x00004000UL) /*!< Bit 4 */ 14443 14444 #define USB_COUNT7_RX_0_BLSIZE_0 (0x00008000UL) /*!< BLock SIZE (low) */ 14445 14446 /*************** Bit definition for USB_COUNT7_RX_1 register ****************/ 14447 #define USB_COUNT7_RX_1_COUNT7_RX_1 (0x03FF0000UL) /*!< Reception Byte Count (high) */ 14448 14449 #define USB_COUNT7_RX_1_NUM_BLOCK_1 (0x7C000000UL) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 14450 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0 (0x04000000UL) /*!< Bit 0 */ 14451 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1 (0x08000000UL) /*!< Bit 1 */ 14452 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2 (0x10000000UL) /*!< Bit 2 */ 14453 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3 (0x20000000UL) /*!< Bit 3 */ 14454 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4 (0x40000000UL) /*!< Bit 4 */ 14455 14456 #define USB_COUNT7_RX_1_BLSIZE_1 (0x80000000UL) /*!< BLock SIZE (high) */ 14457 14458 14459 /** 14460 * @} 14461 */ 14462 14463 /** 14464 * @} 14465 */ 14466 14467 /** @addtogroup Exported_macros 14468 * @{ 14469 */ 14470 14471 /******************************* ADC Instances ********************************/ 14472 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) 14473 14474 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON) 14475 14476 /******************************** CAN Instances ******************************/ 14477 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1) 14478 14479 /******************************** COMP Instances ******************************/ 14480 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \ 14481 ((INSTANCE) == COMP2)) 14482 14483 #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON) 14484 14485 /******************** COMP Instances with window mode capability **************/ 14486 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2) 14487 14488 /******************************* CRC Instances ********************************/ 14489 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) 14490 14491 /******************************* DAC Instances ********************************/ 14492 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1) 14493 14494 /******************************** DMA Instances *******************************/ 14495 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ 14496 ((INSTANCE) == DMA1_Channel2) || \ 14497 ((INSTANCE) == DMA1_Channel3) || \ 14498 ((INSTANCE) == DMA1_Channel4) || \ 14499 ((INSTANCE) == DMA1_Channel5) || \ 14500 ((INSTANCE) == DMA1_Channel6) || \ 14501 ((INSTANCE) == DMA1_Channel7) || \ 14502 ((INSTANCE) == DMA2_Channel1) || \ 14503 ((INSTANCE) == DMA2_Channel2) || \ 14504 ((INSTANCE) == DMA2_Channel3) || \ 14505 ((INSTANCE) == DMA2_Channel4) || \ 14506 ((INSTANCE) == DMA2_Channel5) || \ 14507 ((INSTANCE) == DMA2_Channel6) || \ 14508 ((INSTANCE) == DMA2_Channel7)) 14509 14510 /******************************* GPIO Instances *******************************/ 14511 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ 14512 ((INSTANCE) == GPIOB) || \ 14513 ((INSTANCE) == GPIOC) || \ 14514 ((INSTANCE) == GPIOH)) 14515 14516 /******************************* GPIO AF Instances ****************************/ 14517 /* On L4, all GPIO Bank support AF */ 14518 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) 14519 14520 /**************************** GPIO Lock Instances *****************************/ 14521 /* On L4, all GPIO Bank support the Lock mechanism */ 14522 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) 14523 14524 /******************************** I2C Instances *******************************/ 14525 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ 14526 ((INSTANCE) == I2C3)) 14527 14528 /****************** I2C Instances : wakeup capability from stop modes *********/ 14529 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) 14530 14531 /****************************** OPAMP Instances *******************************/ 14532 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP1) 14533 14534 #define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP1_COMMON) 14535 14536 /******************************* QSPI Instances *******************************/ 14537 #define IS_QSPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == QUADSPI) 14538 14539 /******************************* RNG Instances ********************************/ 14540 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG) 14541 14542 /****************************** RTC Instances *********************************/ 14543 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) 14544 14545 /******************************** SAI Instances *******************************/ 14546 #define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \ 14547 ((INSTANCE) == SAI1_Block_B)) 14548 14549 /****************************** SMBUS Instances *******************************/ 14550 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ 14551 ((INSTANCE) == I2C3)) 14552 14553 /******************************** SPI Instances *******************************/ 14554 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ 14555 ((INSTANCE) == SPI3)) 14556 14557 /******************************** SWPMI Instances *****************************/ 14558 #define IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1) 14559 14560 /****************** LPTIM Instances : All supported instances *****************/ 14561 #define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \ 14562 ((INSTANCE) == LPTIM2)) 14563 14564 /****************** LPTIM Instances : supporting the encoder mode *************/ 14565 #define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1) 14566 14567 /****************** TIM Instances : All supported instances *******************/ 14568 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 14569 ((INSTANCE) == TIM2) || \ 14570 ((INSTANCE) == TIM6) || \ 14571 ((INSTANCE) == TIM7) || \ 14572 ((INSTANCE) == TIM15) || \ 14573 ((INSTANCE) == TIM16)) 14574 14575 /****************** TIM Instances : supporting 32 bits counter ****************/ 14576 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2) 14577 14578 /****************** TIM Instances : supporting the break function *************/ 14579 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 14580 ((INSTANCE) == TIM15) || \ 14581 ((INSTANCE) == TIM16)) 14582 14583 /************** TIM Instances : supporting Break source selection *************/ 14584 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 14585 ((INSTANCE) == TIM15) || \ 14586 ((INSTANCE) == TIM16)) 14587 14588 /****************** TIM Instances : supporting 2 break inputs *****************/ 14589 #define IS_TIM_BKIN2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) 14590 14591 /************* TIM Instances : at least 1 capture/compare channel *************/ 14592 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 14593 ((INSTANCE) == TIM2) || \ 14594 ((INSTANCE) == TIM15) || \ 14595 ((INSTANCE) == TIM16)) 14596 14597 /************ TIM Instances : at least 2 capture/compare channels *************/ 14598 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 14599 ((INSTANCE) == TIM2) || \ 14600 ((INSTANCE) == TIM15)) 14601 14602 /************ TIM Instances : at least 3 capture/compare channels *************/ 14603 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 14604 ((INSTANCE) == TIM2)) 14605 14606 /************ TIM Instances : at least 4 capture/compare channels *************/ 14607 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 14608 ((INSTANCE) == TIM2)) 14609 14610 /****************** TIM Instances : at least 5 capture/compare channels *******/ 14611 #define IS_TIM_CC5_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) 14612 14613 /****************** TIM Instances : at least 6 capture/compare channels *******/ 14614 #define IS_TIM_CC6_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) 14615 14616 /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/ 14617 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 14618 ((INSTANCE) == TIM15) || \ 14619 ((INSTANCE) == TIM16)) 14620 14621 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ 14622 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 14623 ((INSTANCE) == TIM2) || \ 14624 ((INSTANCE) == TIM6) || \ 14625 ((INSTANCE) == TIM7) || \ 14626 ((INSTANCE) == TIM15) || \ 14627 ((INSTANCE) == TIM16)) 14628 14629 /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ 14630 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 14631 ((INSTANCE) == TIM2) || \ 14632 ((INSTANCE) == TIM15) || \ 14633 ((INSTANCE) == TIM16)) 14634 14635 /******************** TIM Instances : DMA burst feature ***********************/ 14636 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 14637 ((INSTANCE) == TIM2) || \ 14638 ((INSTANCE) == TIM15) || \ 14639 ((INSTANCE) == TIM16)) 14640 14641 /******************* TIM Instances : output(s) available **********************/ 14642 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ 14643 ((((INSTANCE) == TIM1) && \ 14644 (((CHANNEL) == TIM_CHANNEL_1) || \ 14645 ((CHANNEL) == TIM_CHANNEL_2) || \ 14646 ((CHANNEL) == TIM_CHANNEL_3) || \ 14647 ((CHANNEL) == TIM_CHANNEL_4) || \ 14648 ((CHANNEL) == TIM_CHANNEL_5) || \ 14649 ((CHANNEL) == TIM_CHANNEL_6))) \ 14650 || \ 14651 (((INSTANCE) == TIM2) && \ 14652 (((CHANNEL) == TIM_CHANNEL_1) || \ 14653 ((CHANNEL) == TIM_CHANNEL_2) || \ 14654 ((CHANNEL) == TIM_CHANNEL_3) || \ 14655 ((CHANNEL) == TIM_CHANNEL_4))) \ 14656 || \ 14657 (((INSTANCE) == TIM15) && \ 14658 (((CHANNEL) == TIM_CHANNEL_1) || \ 14659 ((CHANNEL) == TIM_CHANNEL_2))) \ 14660 || \ 14661 (((INSTANCE) == TIM16) && \ 14662 (((CHANNEL) == TIM_CHANNEL_1)))) 14663 14664 /****************** TIM Instances : supporting complementary output(s) ********/ 14665 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ 14666 ((((INSTANCE) == TIM1) && \ 14667 (((CHANNEL) == TIM_CHANNEL_1) || \ 14668 ((CHANNEL) == TIM_CHANNEL_2) || \ 14669 ((CHANNEL) == TIM_CHANNEL_3))) \ 14670 || \ 14671 (((INSTANCE) == TIM15) && \ 14672 ((CHANNEL) == TIM_CHANNEL_1)) \ 14673 || \ 14674 (((INSTANCE) == TIM16) && \ 14675 ((CHANNEL) == TIM_CHANNEL_1))) 14676 14677 /****************** TIM Instances : supporting clock division *****************/ 14678 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 14679 ((INSTANCE) == TIM2) || \ 14680 ((INSTANCE) == TIM15) || \ 14681 ((INSTANCE) == TIM16)) 14682 14683 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ 14684 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 14685 ((INSTANCE) == TIM2) || \ 14686 ((INSTANCE) == TIM15)) 14687 14688 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ 14689 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 14690 ((INSTANCE) == TIM2)) 14691 14692 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ 14693 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 14694 ((INSTANCE) == TIM2) || \ 14695 ((INSTANCE) == TIM15)) 14696 14697 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ 14698 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 14699 ((INSTANCE) == TIM2) || \ 14700 ((INSTANCE) == TIM15)) 14701 14702 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/ 14703 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) 14704 14705 /****************** TIM Instances : supporting commutation event generation ***/ 14706 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 14707 ((INSTANCE) == TIM15) || \ 14708 ((INSTANCE) == TIM16)) 14709 14710 /****************** TIM Instances : supporting counting mode selection ********/ 14711 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 14712 ((INSTANCE) == TIM2)) 14713 14714 /****************** TIM Instances : supporting encoder interface **************/ 14715 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 14716 ((INSTANCE) == TIM2)) 14717 14718 /****************** TIM Instances : supporting Hall sensor interface **********/ 14719 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 14720 ((INSTANCE) == TIM2)) 14721 14722 /**************** TIM Instances : external trigger input available ************/ 14723 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 14724 ((INSTANCE) == TIM2)) 14725 14726 /************* TIM Instances : supporting ETR source selection ***************/ 14727 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 14728 ((INSTANCE) == TIM2)) 14729 14730 /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ 14731 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 14732 ((INSTANCE) == TIM2) || \ 14733 ((INSTANCE) == TIM6) || \ 14734 ((INSTANCE) == TIM7) || \ 14735 ((INSTANCE) == TIM15)) 14736 14737 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ 14738 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 14739 ((INSTANCE) == TIM2) || \ 14740 ((INSTANCE) == TIM15)) 14741 14742 /****************** TIM Instances : supporting OCxREF clear *******************/ 14743 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 14744 ((INSTANCE) == TIM2)) 14745 14746 /****************** TIM Instances : remapping capability **********************/ 14747 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 14748 ((INSTANCE) == TIM2) || \ 14749 ((INSTANCE) == TIM15) || \ 14750 ((INSTANCE) == TIM16)) 14751 14752 /****************** TIM Instances : supporting repetition counter *************/ 14753 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 14754 ((INSTANCE) == TIM15) || \ 14755 ((INSTANCE) == TIM16)) 14756 14757 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ 14758 #define IS_TIM_TRGO2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) 14759 14760 /******************* TIM Instances : Timer input XOR function *****************/ 14761 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 14762 ((INSTANCE) == TIM2) || \ 14763 ((INSTANCE) == TIM15)) 14764 14765 /****************** TIM Instances : Advanced timer instances *******************/ 14766 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) 14767 14768 /****************************** TSC Instances *********************************/ 14769 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC) 14770 14771 /******************** USART Instances : Synchronous mode **********************/ 14772 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 14773 ((INSTANCE) == USART2)) 14774 14775 /******************** UART Instances : Asynchronous mode **********************/ 14776 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 14777 ((INSTANCE) == USART2)) 14778 14779 /****************** UART Instances : Auto Baud Rate detection ****************/ 14780 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 14781 ((INSTANCE) == USART2)) 14782 14783 /****************** UART Instances : Driver Enable *****************/ 14784 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 14785 ((INSTANCE) == USART2) || \ 14786 ((INSTANCE) == LPUART1)) 14787 14788 /******************** UART Instances : Half-Duplex mode **********************/ 14789 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 14790 ((INSTANCE) == USART2) || \ 14791 ((INSTANCE) == LPUART1)) 14792 14793 /****************** UART Instances : Hardware Flow control ********************/ 14794 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 14795 ((INSTANCE) == USART2) || \ 14796 ((INSTANCE) == LPUART1)) 14797 14798 /******************** UART Instances : LIN mode **********************/ 14799 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 14800 ((INSTANCE) == USART2)) 14801 14802 /******************** UART Instances : Wake-up from Stop mode **********************/ 14803 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 14804 ((INSTANCE) == USART2) || \ 14805 ((INSTANCE) == LPUART1)) 14806 14807 /*********************** UART Instances : IRDA mode ***************************/ 14808 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 14809 ((INSTANCE) == USART2)) 14810 14811 /********************* USART Instances : Smard card mode ***********************/ 14812 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 14813 ((INSTANCE) == USART2)) 14814 14815 /******************** LPUART Instance *****************************************/ 14816 #define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1) 14817 14818 /****************************** IWDG Instances ********************************/ 14819 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) 14820 14821 /****************************** WWDG Instances ********************************/ 14822 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) 14823 14824 /******************************* USB Instances *******************************/ 14825 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) 14826 #define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE 14827 /** 14828 * @} 14829 */ 14830 14831 14832 /******************************************************************************/ 14833 /* For a painless codes migration between the STM32L4xx device product */ 14834 /* lines, the aliases defined below are put in place to overcome the */ 14835 /* differences in the interrupt handlers and IRQn definitions. */ 14836 /* No need to update developed interrupt code when moving across */ 14837 /* product lines within the same STM32L4 Family */ 14838 /******************************************************************************/ 14839 14840 /* Aliases for __IRQn */ 14841 #define TIM6_IRQn TIM6_DAC_IRQn 14842 #define ADC1_2_IRQn ADC1_IRQn 14843 #define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn 14844 #define HASH_RNG_IRQn RNG_IRQn 14845 #define HASH_CRS_IRQn CRS_IRQn 14846 #define USB_FS_IRQn USB_IRQn 14847 14848 /* Aliases for __IRQHandler */ 14849 #define TIM6_IRQHandler TIM6_DAC_IRQHandler 14850 #define ADC1_2_IRQHandler ADC1_IRQHandler 14851 #define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler 14852 #define HASH_RNG_IRQHandler RNG_IRQHandler 14853 #define HASH_CRS_IRQHandler CRS_IRQHandler 14854 #define USB_FS_IRQHandler USB_IRQHandler 14855 14856 #ifdef __cplusplus 14857 } 14858 #endif /* __cplusplus */ 14859 14860 #endif /* __STM32L432xx_H */ 14861 14862 /** 14863 * @} 14864 */ 14865 14866 /** 14867 * @} 14868 */ 14869 14870