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Searched refs:GFXTIM_EVSR_FES1_Pos (Results 1 – 15 of 15) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_hal_gfxtim.h492 #define GFXTIM_FRAME_EVENT_NONE (0U << GFXTIM_EVSR_FES1_Pos ) /*!< None */
493 #define GFXTIM_FRAME_EVENT_AFC_OVERFLOW (1U << GFXTIM_EVSR_FES1_Pos ) /*!< Absolute frame counte…
494 #define GFXTIM_FRAME_EVENT_AFC_COMPARE (2U << GFXTIM_EVSR_FES1_Pos ) /*!< Absolute frame counte…
495 #define GFXTIM_FRAME_EVENT_RFC1_RELOAD (4U << GFXTIM_EVSR_FES1_Pos ) /*!< Relative frame counte…
496 #define GFXTIM_FRAME_EVENT_RFC2_RELOAD (5U << GFXTIM_EVSR_FES1_Pos ) /*!< Relative frame counte…
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_hal_gfxtim.h492 #define GFXTIM_FRAME_EVENT_NONE (0U << GFXTIM_EVSR_FES1_Pos ) /*!< None */
493 #define GFXTIM_FRAME_EVENT_AFC_OVERFLOW (1U << GFXTIM_EVSR_FES1_Pos ) /*!< Absolute frame counte…
494 #define GFXTIM_FRAME_EVENT_AFC_COMPARE (2U << GFXTIM_EVSR_FES1_Pos ) /*!< Absolute frame counte…
495 #define GFXTIM_FRAME_EVENT_RFC1_RELOAD (4U << GFXTIM_EVSR_FES1_Pos ) /*!< Relative frame counte…
496 #define GFXTIM_FRAME_EVENT_RFC2_RELOAD (5U << GFXTIM_EVSR_FES1_Pos ) /*!< Relative frame counte…
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_hal_gfxtim.h492 #define GFXTIM_FRAME_EVENT_NONE (0U << GFXTIM_EVSR_FES1_Pos ) /*!< None */
493 #define GFXTIM_FRAME_EVENT_AFC_OVERFLOW (1U << GFXTIM_EVSR_FES1_Pos ) /*!< Absolute frame counte…
494 #define GFXTIM_FRAME_EVENT_AFC_COMPARE (2U << GFXTIM_EVSR_FES1_Pos ) /*!< Absolute frame counte…
495 #define GFXTIM_FRAME_EVENT_RFC1_RELOAD (4U << GFXTIM_EVSR_FES1_Pos ) /*!< Relative frame counte…
496 #define GFXTIM_FRAME_EVENT_RFC2_RELOAD (5U << GFXTIM_EVSR_FES1_Pos ) /*!< Relative frame counte…
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h10080 #define GFXTIM_EVSR_FES1_Pos (4U) macro
10081 #define GFXTIM_EVSR_FES1_Msk (0x7UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000070 */
10083 #define GFXTIM_EVSR_FES1_0 (0x1UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000010 */
10084 #define GFXTIM_EVSR_FES1_1 (0x2UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000020 */
10085 #define GFXTIM_EVSR_FES1_2 (0x4UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000040 */
Dstm32h7s7xx.h10604 #define GFXTIM_EVSR_FES1_Pos (4U) macro
10605 #define GFXTIM_EVSR_FES1_Msk (0x7UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000070 */
10607 #define GFXTIM_EVSR_FES1_0 (0x1UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000010 */
10608 #define GFXTIM_EVSR_FES1_1 (0x2UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000020 */
10609 #define GFXTIM_EVSR_FES1_2 (0x4UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000040 */
Dstm32h7s3xx.h10525 #define GFXTIM_EVSR_FES1_Pos (4U) macro
10526 #define GFXTIM_EVSR_FES1_Msk (0x7UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000070 */
10528 #define GFXTIM_EVSR_FES1_0 (0x1UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000010 */
10529 #define GFXTIM_EVSR_FES1_1 (0x2UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000020 */
10530 #define GFXTIM_EVSR_FES1_2 (0x4UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000040 */
Dstm32h7r7xx.h10157 #define GFXTIM_EVSR_FES1_Pos (4U) macro
10158 #define GFXTIM_EVSR_FES1_Msk (0x7UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000070 */
10160 #define GFXTIM_EVSR_FES1_0 (0x1UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000010 */
10161 #define GFXTIM_EVSR_FES1_1 (0x2UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000020 */
10162 #define GFXTIM_EVSR_FES1_2 (0x4UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000040 */
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u5f7xx.h9929 #define GFXTIM_EVSR_FES1_Pos (4U) macro
9930 #define GFXTIM_EVSR_FES1_Msk (0x7UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000070 */
9932 #define GFXTIM_EVSR_FES1_0 (0x1UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000010 */
9933 #define GFXTIM_EVSR_FES1_1 (0x2UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000020 */
9934 #define GFXTIM_EVSR_FES1_2 (0x4UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000040 */
Dstm32u5g7xx.h10378 #define GFXTIM_EVSR_FES1_Pos (4U) macro
10379 #define GFXTIM_EVSR_FES1_Msk (0x7UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000070 */
10381 #define GFXTIM_EVSR_FES1_0 (0x1UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000010 */
10382 #define GFXTIM_EVSR_FES1_1 (0x2UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000020 */
10383 #define GFXTIM_EVSR_FES1_2 (0x4UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000040 */
Dstm32u5f9xx.h13055 #define GFXTIM_EVSR_FES1_Pos (4U) macro
13056 #define GFXTIM_EVSR_FES1_Msk (0x7UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000070 */
13058 #define GFXTIM_EVSR_FES1_0 (0x1UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000010 */
13059 #define GFXTIM_EVSR_FES1_1 (0x2UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000020 */
13060 #define GFXTIM_EVSR_FES1_2 (0x4UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000040 */
Dstm32u5g9xx.h13504 #define GFXTIM_EVSR_FES1_Pos (4U) macro
13505 #define GFXTIM_EVSR_FES1_Msk (0x7UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000070 */
13507 #define GFXTIM_EVSR_FES1_0 (0x1UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000010 */
13508 #define GFXTIM_EVSR_FES1_1 (0x2UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000020 */
13509 #define GFXTIM_EVSR_FES1_2 (0x4UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000040 */
/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dstm32n645xx.h18829 #define GFXTIM_EVSR_FES1_Pos (4U) macro
18830 #define GFXTIM_EVSR_FES1_Msk (0x7UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000070 */
18832 #define GFXTIM_EVSR_FES1_0 (0x1UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000010 */
18833 #define GFXTIM_EVSR_FES1_1 (0x2UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000020 */
18834 #define GFXTIM_EVSR_FES1_2 (0x4UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000040 */
Dstm32n657xx.h19771 #define GFXTIM_EVSR_FES1_Pos (4U) macro
19772 #define GFXTIM_EVSR_FES1_Msk (0x7UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000070 */
19774 #define GFXTIM_EVSR_FES1_0 (0x1UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000010 */
19775 #define GFXTIM_EVSR_FES1_1 (0x2UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000020 */
19776 #define GFXTIM_EVSR_FES1_2 (0x4UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000040 */
Dstm32n655xx.h19529 #define GFXTIM_EVSR_FES1_Pos (4U) macro
19530 #define GFXTIM_EVSR_FES1_Msk (0x7UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000070 */
19532 #define GFXTIM_EVSR_FES1_0 (0x1UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000010 */
19533 #define GFXTIM_EVSR_FES1_1 (0x2UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000020 */
19534 #define GFXTIM_EVSR_FES1_2 (0x4UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000040 */
Dstm32n647xx.h19071 #define GFXTIM_EVSR_FES1_Pos (4U) macro
19072 #define GFXTIM_EVSR_FES1_Msk (0x7UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000070 */
19074 #define GFXTIM_EVSR_FES1_0 (0x1UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000010 */
19075 #define GFXTIM_EVSR_FES1_1 (0x2UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000020 */
19076 #define GFXTIM_EVSR_FES1_2 (0x4UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000040 */