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Searched refs:GFXMMU_DVR_DV_Pos (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32l4xx/soc/
Dstm32l4r7xx.h9292 #define GFXMMU_DVR_DV_Pos (0U) macro
9293 #define GFXMMU_DVR_DV_Msk (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos) /*!< 0xFFFFFFFF */
Dstm32l4s7xx.h9544 #define GFXMMU_DVR_DV_Pos (0U) macro
9545 #define GFXMMU_DVR_DV_Msk (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos) /*!< 0xFFFFFFFF */
Dstm32l4r9xx.h12411 #define GFXMMU_DVR_DV_Pos (0U) macro
12412 #define GFXMMU_DVR_DV_Msk (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos) /*!< 0xFFFFFFFF */
Dstm32l4s9xx.h12663 #define GFXMMU_DVR_DV_Pos (0U) macro
12664 #define GFXMMU_DVR_DV_Msk (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos) /*!< 0xFFFFFFFF */
/hal_stm32-latest/stm32cube/stm32h7xx/soc/
Dstm32h7a3xx.h9569 #define GFXMMU_DVR_DV_Pos (0U) macro
9570 #define GFXMMU_DVR_DV_Msk (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos) /*!< 0xFFFFFFFF */
Dstm32h7b0xx.h9816 #define GFXMMU_DVR_DV_Pos (0U) macro
9817 #define GFXMMU_DVR_DV_Msk (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos) /*!< 0xFFFFFFFF */
Dstm32h7b0xxq.h9817 #define GFXMMU_DVR_DV_Pos (0U) macro
9818 #define GFXMMU_DVR_DV_Msk (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos) /*!< 0xFFFFFFFF */
Dstm32h7a3xxq.h9570 #define GFXMMU_DVR_DV_Pos (0U) macro
9571 #define GFXMMU_DVR_DV_Msk (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos) /*!< 0xFFFFFFFF */
Dstm32h7b3xx.h9823 #define GFXMMU_DVR_DV_Pos (0U) macro
9824 #define GFXMMU_DVR_DV_Msk (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos) /*!< 0xFFFFFFFF */
Dstm32h7b3xxq.h9824 #define GFXMMU_DVR_DV_Pos (0U) macro
9825 #define GFXMMU_DVR_DV_Msk (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos) /*!< 0xFFFFFFFF */
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h9861 #define GFXMMU_DVR_DV_Pos (0U) macro
9862 #define GFXMMU_DVR_DV_Msk (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos) /*!< 0xFFFFFFFF */
Dstm32h7s7xx.h10385 #define GFXMMU_DVR_DV_Pos (0U) macro
10386 #define GFXMMU_DVR_DV_Msk (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos) /*!< 0xFFFFFFFF */
Dstm32h7s3xx.h10306 #define GFXMMU_DVR_DV_Pos (0U) macro
10307 #define GFXMMU_DVR_DV_Msk (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos) /*!< 0xFFFFFFFF */
Dstm32h7r7xx.h9938 #define GFXMMU_DVR_DV_Pos (0U) macro
9939 #define GFXMMU_DVR_DV_Msk (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos) /*!< 0xFFFFFFFF */
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u5f7xx.h9716 #define GFXMMU_DVR_DV_Pos (0U) macro
9717 #define GFXMMU_DVR_DV_Msk (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos) /*!< 0xFFFFFFFF */
Dstm32u599xx.h12724 #define GFXMMU_DVR_DV_Pos (0U) macro
12725 #define GFXMMU_DVR_DV_Msk (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos) /*!< 0xFFFFFFFF */
Dstm32u5g7xx.h10165 #define GFXMMU_DVR_DV_Pos (0U) macro
10166 #define GFXMMU_DVR_DV_Msk (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos) /*!< 0xFFFFFFFF */
Dstm32u5f9xx.h12842 #define GFXMMU_DVR_DV_Pos (0U) macro
12843 #define GFXMMU_DVR_DV_Msk (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos) /*!< 0xFFFFFFFF */
Dstm32u5a9xx.h13173 #define GFXMMU_DVR_DV_Pos (0U) macro
13174 #define GFXMMU_DVR_DV_Msk (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos) /*!< 0xFFFFFFFF */
Dstm32u5g9xx.h13291 #define GFXMMU_DVR_DV_Pos (0U) macro
13292 #define GFXMMU_DVR_DV_Msk (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos) /*!< 0xFFFFFFFF */
/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dstm32n645xx.h18610 #define GFXMMU_DVR_DV_Pos (0U) macro
18611 #define GFXMMU_DVR_DV_Msk (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos) /*!< 0xFFFFFFFF */
Dstm32n657xx.h19552 #define GFXMMU_DVR_DV_Pos (0U) macro
19553 #define GFXMMU_DVR_DV_Msk (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos) /*!< 0xFFFFFFFF */
Dstm32n655xx.h19310 #define GFXMMU_DVR_DV_Pos (0U) macro
19311 #define GFXMMU_DVR_DV_Msk (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos) /*!< 0xFFFFFFFF */
Dstm32n647xx.h18852 #define GFXMMU_DVR_DV_Pos (0U) macro
18853 #define GFXMMU_DVR_DV_Msk (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos) /*!< 0xFFFFFFFF */