Home
last modified time | relevance | path

Searched refs:DMA_IFCR_CHTIF5 (Results 1 – 25 of 172) sorted by relevance

1234567

/hal_stm32-latest/stm32cube/stm32c0xx/drivers/include/
Dstm32c0xx_ll_dma.h187 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag …
1657 #if defined(DMA_IFCR_CHTIF5)
1666 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); in LL_DMA_ClearFlag_HT5()
/hal_stm32-latest/stm32cube/stm32wb0x/drivers/include/
Dstm32wb0x_ll_dma.h172 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag …
1752 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); in LL_DMA_ClearFlag_HT5()
/hal_stm32-latest/stm32cube/stm32f1xx/drivers/include/
Dstm32f1xx_ll_dma.h168 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag …
1637 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); in LL_DMA_ClearFlag_HT5()
/hal_stm32-latest/stm32cube/stm32l0xx/drivers/include/
Dstm32l0xx_ll_dma.h191 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag …
1801 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); in LL_DMA_ClearFlag_HT5()
/hal_stm32-latest/stm32cube/stm32wbxx/drivers/include/
Dstm32wbxx_ll_dma.h185 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag …
1841 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); in LL_DMA_ClearFlag_HT5()
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/include/
Dstm32u0xx_ll_dma.h191 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag …
1935 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); in LL_DMA_ClearFlag_HT5()
/hal_stm32-latest/stm32cube/stm32g0xx/drivers/include/
Dstm32g0xx_ll_dma.h186 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag …
1934 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); in LL_DMA_ClearFlag_HT5()
/hal_stm32-latest/stm32cube/stm32f3xx/drivers/include/
Dstm32f3xx_ll_dma.h169 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag …
1674 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); in LL_DMA_ClearFlag_HT5()
/hal_stm32-latest/stm32cube/stm32l1xx/drivers/include/
Dstm32l1xx_ll_dma.h170 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag …
1675 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF5); in LL_DMA_ClearFlag_HT5()
/hal_stm32-latest/stm32cube/stm32wlxx/drivers/include/
Dstm32wlxx_ll_dma.h182 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag …
2161 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); in LL_DMA_ClearFlag_HT5()
/hal_stm32-latest/stm32cube/stm32f0xx/drivers/include/
Dstm32f0xx_ll_dma.h192 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag …
1906 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); in LL_DMA_ClearFlag_HT5()
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/include/
Dstm32l4xx_ll_dma.h217 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag …
2103 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); in LL_DMA_ClearFlag_HT5()
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_ll_dma.h176 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag …
2529 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); in LL_DMA_ClearFlag_HT5()
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_ll_dma.h194 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag …
2201 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); in LL_DMA_ClearFlag_HT5()
/hal_stm32-latest/stm32cube/stm32f1xx/soc/
Dstm32f101x6.h2973 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half … macro
Dstm32f101xb.h3035 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half … macro
Dstm32f100xb.h3187 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half … macro
/hal_stm32-latest/stm32cube/stm32f0xx/soc/
Dstm32f030x6.h1078 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half … macro
Dstm32f030x8.h1100 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half … macro
Dstm32f070x6.h1123 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half … macro
/hal_stm32-latest/stm32cube/stm32l0xx/soc/
Dstm32l041xx.h1360 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half … macro
Dstm32l010x8.h1123 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half … macro
Dstm32l010xb.h1131 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half … macro
Dstm32l011xx.h1196 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half … macro
Dstm32l021xx.h1324 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half … macro

1234567