1 /**
2 ******************************************************************************
3 * @file stm32wb0x_ll_dma.h
4 * @author MCD Application Team
5 * @brief Header file of DMA LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2024 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32WB0x_LL_DMA_H
21 #define STM32WB0x_LL_DMA_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32wb0x.h"
29 #include "stm32wb0x_ll_dmamux.h"
30
31 /** @addtogroup STM32WB0x_LL_Driver
32 * @{
33 */
34
35 #if defined (DMA1)
36
37 /** @defgroup DMA_LL DMA
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private constants ---------------------------------------------------------*/
44 /* Private macros ------------------------------------------------------------*/
45 /** @defgroup DMA_LL_Private_Macros DMA Private Macros
46 * @{
47 */
48
49 /**
50 * @brief Helper macro to convert DMA Instance and index into DMA channel
51 * @param __DMA_INSTANCE__ DMAx
52 * @param __CHANNEL_INDEX__ 0 to 7 to map DMAx_Channel1 to DMAx_Channel8
53 * @retval Pointer to the DMA channel
54 */
55 #define __LL_DMA_INSTANCE_TO_CHANNEL(__DMA_INSTANCE__, __CHANNEL_INDEX__) (DMA1_Channel1 + (__CHANNEL_INDEX__))
56
57 /**
58 * @brief Helper macro to convert DMA Instance and index into DMAMUX channel
59 * @note DMAMUX channel 0 to 7 are mapped to DMA1 channel 1 to 8.
60 * @param __DMA_INSTANCE__ DMAx
61 * @param __CHANNEL_INDEX__ 0 to 7 to map DMAx_Channel1 to DMAx_Channel8
62 * @retval Pointer to the DMA channel
63 */
64 #define __LL_DMA_INSTANCE_TO_DMAMUX_CCR(__DMA_INSTANCE__, __CHANNEL_INDEX__) (DMAMUX1_Channel0 + (__CHANNEL_INDEX__))
65 /**
66 * @}
67 */
68
69 /* Exported types ------------------------------------------------------------*/
70 #if defined(USE_FULL_LL_DRIVER)
71 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
72 * @{
73 */
74 typedef struct
75 {
76 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
77 or as Source base address in case of memory to memory transfer direction.
78
79 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
80
81 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
82 or as Destination base address in case of memory to memory transfer direction.
83
84 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
85
86 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
87 from memory to memory or from peripheral to memory.
88 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
89
90 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
91
92 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
93 This parameter can be a value of @ref DMA_LL_EC_MODE
94 @note: The circular buffer mode cannot be used if the memory to memory
95 data transfer direction is configured on the selected Channel
96
97 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
98
99 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
100 is incremented or not.
101 This parameter can be a value of @ref DMA_LL_EC_PERIPH
102
103 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
104
105 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
106 is incremented or not.
107 This parameter can be a value of @ref DMA_LL_EC_MEMORY
108
109 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
110
111 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
112 in case of memory to memory transfer direction.
113 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
114
115 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
116
117 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
118 in case of memory to memory transfer direction.
119 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
120
121 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
122
123 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
124 The data unit is equal to the source buffer configuration set in PeripheralSize
125 or MemorySize parameters depending in the transfer direction.
126 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
127
128 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
129
130 uint32_t PeriphRequest; /*!< Specifies the peripheral request.
131 This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST
132
133 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
134
135 uint32_t Priority; /*!< Specifies the channel priority level.
136 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
137
138 This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
139
140 } LL_DMA_InitTypeDef;
141 /**
142 * @}
143 */
144 #endif /*USE_FULL_LL_DRIVER*/
145
146 /* Exported constants --------------------------------------------------------*/
147 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
148 * @{
149 */
150 /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
151 * @brief Flags defines which can be used with LL_DMA_WriteReg function
152 * @{
153 */
154 #define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */
155 #define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
156 #define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
157 #define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
158 #define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */
159 #define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
160 #define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
161 #define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
162 #define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */
163 #define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
164 #define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
165 #define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
166 #define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */
167 #define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
168 #define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
169 #define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
170 #define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */
171 #define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */
172 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */
173 #define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */
174 #define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */
175 #define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */
176 #define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */
177 #define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */
178 #define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */
179 #define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */
180 #define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */
181 #define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */
182 #define LL_DMA_IFCR_CGIF8 DMA_IFCR_CGIF8 /*!< Channel 8 global flag */
183 #define LL_DMA_IFCR_CTCIF8 DMA_IFCR_CTCIF8 /*!< Channel 8 transfer complete flag */
184 #define LL_DMA_IFCR_CHTIF8 DMA_IFCR_CHTIF8 /*!< Channel 8 half transfer flag */
185 #define LL_DMA_IFCR_CTEIF8 DMA_IFCR_CTEIF8 /*!< Channel 8 transfer error flag */
186 /**
187 * @}
188 */
189
190 /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
191 * @brief Flags defines which can be used with LL_DMA_ReadReg function
192 * @{
193 */
194 #define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */
195 #define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
196 #define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
197 #define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
198 #define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */
199 #define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
200 #define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
201 #define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
202 #define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */
203 #define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
204 #define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
205 #define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
206 #define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */
207 #define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */
208 #define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
209 #define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
210 #define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */
211 #define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */
212 #define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
213 #define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
214 #define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */
215 #define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */
216 #define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
217 #define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
218 #define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */
219 #define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */
220 #define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
221 #define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
222 #define LL_DMA_ISR_GIF8 DMA_ISR_GIF8 /*!< Channel 8 global flag */
223 #define LL_DMA_ISR_TCIF8 DMA_ISR_TCIF8 /*!< Channel 8 transfer complete flag */
224 #define LL_DMA_ISR_HTIF8 DMA_ISR_HTIF8 /*!< Channel 8 half transfer flag */
225 #define LL_DMA_ISR_TEIF8 DMA_ISR_TEIF8 /*!< Channel 8 transfer error flag */
226 /**
227 * @}
228 */
229
230 /** @defgroup DMA_LL_EC_IT IT Defines
231 * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
232 * @{
233 */
234 #define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */
235 #define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */
236 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
237 /**
238 * @}
239 */
240
241 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
242 * @{
243 */
244 #define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */
245 #define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */
246 #define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */
247 #define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */
248 #define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */
249 #define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */
250 #define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */
251 #define LL_DMA_CHANNEL_8 0x00000008U /*!< DMA Channel 8 */
252 #if defined(USE_FULL_LL_DRIVER)
253 #define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
254 #endif /*USE_FULL_LL_DRIVER*/
255 /**
256 * @}
257 */
258
259 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
260 * @{
261 */
262 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
263 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
264 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
265 /**
266 * @}
267 */
268
269 /** @defgroup DMA_LL_EC_MODE Transfer mode
270 * @{
271 */
272 #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
273 #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */
274 /**
275 * @}
276 */
277
278 /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
279 * @{
280 */
281 #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */
282 #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
283 /**
284 * @}
285 */
286
287 /** @defgroup DMA_LL_EC_MEMORY Memory increment mode
288 * @{
289 */
290 #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */
291 #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
292 /**
293 * @}
294 */
295
296 /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
297 * @{
298 */
299 #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
300 #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
301 #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
302 /**
303 * @}
304 */
305
306 /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
307 * @{
308 */
309 #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
310 #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
311 #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
312 /**
313 * @}
314 */
315
316 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
317 * @{
318 */
319 #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
320 #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
321 #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
322 #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */
323 /**
324 * @}
325 */
326
327 /**
328 * @}
329 */
330
331 /* Exported macro ------------------------------------------------------------*/
332 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
333 * @{
334 */
335
336 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
337 * @{
338 */
339 /**
340 * @brief Write a value in DMA register
341 * @param __INSTANCE__ DMA Instance
342 * @param __REG__ Register to be written
343 * @param __VALUE__ Value to be written in the register
344 * @retval None
345 */
346 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
347
348 /**
349 * @brief Read a value in DMA register
350 * @param __INSTANCE__ DMA Instance
351 * @param __REG__ Register to be read
352 * @retval Register value
353 */
354 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
355 /**
356 * @}
357 */
358
359 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
360 * @{
361 */
362 /**
363 * @brief Convert DMAx_Channely into DMAx
364 * @param __CHANNEL_INSTANCE__ DMAx_Channely
365 * @retval DMAx
366 */
367 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
368
369 /**
370 * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
371 * @param __CHANNEL_INSTANCE__ DMAx_Channely
372 * @retval LL_DMA_CHANNEL_y
373 */
374 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
375 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
376 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
377 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
378 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
379 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
380 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
381 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel7)) ? LL_DMA_CHANNEL_7 : \
382 LL_DMA_CHANNEL_8)
383
384 /**
385 * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
386 * @param __DMA_INSTANCE__ DMAx
387 * @param __CHANNEL__ LL_DMA_CHANNEL_y
388 * @retval DMAx_Channely
389 */
390 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
391 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
392 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
393 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
394 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
395 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
396 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
397 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
398 DMA1_Channel8)
399
400 /**
401 * @}
402 */
403
404 /**
405 * @}
406 */
407
408 /* Exported functions --------------------------------------------------------*/
409 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
410 * @{
411 */
412
413 /** @defgroup DMA_LL_EF_Configuration Configuration
414 * @{
415 */
416 /**
417 * @brief Enable DMA channel.
418 * @rmtoll CCR EN LL_DMA_EnableChannel
419 * @param DMAx DMAx Instance
420 * @param Channel This parameter can be one of the following values:
421 * @arg LL_DMA_CHANNEL_1
422 * @arg LL_DMA_CHANNEL_2
423 * @arg LL_DMA_CHANNEL_3
424 * @arg LL_DMA_CHANNEL_4
425 * @arg LL_DMA_CHANNEL_5
426 * @arg LL_DMA_CHANNEL_6
427 * @arg LL_DMA_CHANNEL_7
428 * @arg LL_DMA_CHANNEL_8
429 * @retval None
430 */
LL_DMA_EnableChannel(DMA_TypeDef * DMAx,uint32_t Channel)431 __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
432 {
433 SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_EN);
434 }
435
436 /**
437 * @brief Disable DMA channel.
438 * @rmtoll CCR EN LL_DMA_DisableChannel
439 * @param DMAx DMAx Instance
440 * @param Channel This parameter can be one of the following values:
441 * @arg LL_DMA_CHANNEL_1
442 * @arg LL_DMA_CHANNEL_2
443 * @arg LL_DMA_CHANNEL_3
444 * @arg LL_DMA_CHANNEL_4
445 * @arg LL_DMA_CHANNEL_5
446 * @arg LL_DMA_CHANNEL_6
447 * @arg LL_DMA_CHANNEL_7
448 * @arg LL_DMA_CHANNEL_8
449 * @retval None
450 */
LL_DMA_DisableChannel(DMA_TypeDef * DMAx,uint32_t Channel)451 __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
452 {
453 CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_EN);
454 }
455
456 /**
457 * @brief Check if DMA channel is enabled or disabled.
458 * @rmtoll CCR EN LL_DMA_IsEnabledChannel
459 * @param DMAx DMAx Instance
460 * @param Channel This parameter can be one of the following values:
461 * @arg LL_DMA_CHANNEL_1
462 * @arg LL_DMA_CHANNEL_2
463 * @arg LL_DMA_CHANNEL_3
464 * @arg LL_DMA_CHANNEL_4
465 * @arg LL_DMA_CHANNEL_5
466 * @arg LL_DMA_CHANNEL_6
467 * @arg LL_DMA_CHANNEL_7
468 * @arg LL_DMA_CHANNEL_8
469 * @retval State of bit (1 or 0).
470 */
LL_DMA_IsEnabledChannel(DMA_TypeDef * DMAx,uint32_t Channel)471 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
472 {
473 return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
474 DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL);
475 }
476
477 /**
478 * @brief Configure all parameters link to DMA transfer.
479 * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
480 * CCR MEM2MEM LL_DMA_ConfigTransfer\n
481 * CCR CIRC LL_DMA_ConfigTransfer\n
482 * CCR PINC LL_DMA_ConfigTransfer\n
483 * CCR MINC LL_DMA_ConfigTransfer\n
484 * CCR PSIZE LL_DMA_ConfigTransfer\n
485 * CCR MSIZE LL_DMA_ConfigTransfer\n
486 * CCR PL LL_DMA_ConfigTransfer
487 * @param DMAx DMAx Instance
488 * @param Channel This parameter can be one of the following values:
489 * @arg LL_DMA_CHANNEL_1
490 * @arg LL_DMA_CHANNEL_2
491 * @arg LL_DMA_CHANNEL_3
492 * @arg LL_DMA_CHANNEL_4
493 * @arg LL_DMA_CHANNEL_5
494 * @arg LL_DMA_CHANNEL_6
495 * @arg LL_DMA_CHANNEL_7
496 * @arg LL_DMA_CHANNEL_8
497 * @param Configuration This parameter must be a combination of all the following values:
498 * @arg LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH or LL_DMA_DIRECTION_MEMORY_TO_MEMORY
499 * @arg LL_DMA_MODE_NORMAL or LL_DMA_MODE_CIRCULAR
500 * @arg LL_DMA_PERIPH_INCREMENT or LL_DMA_PERIPH_NOINCREMENT
501 * @arg LL_DMA_MEMORY_INCREMENT or LL_DMA_MEMORY_NOINCREMENT
502 * @arg LL_DMA_PDATAALIGN_BYTE or LL_DMA_PDATAALIGN_HALFWORD or LL_DMA_PDATAALIGN_WORD
503 * @arg LL_DMA_MDATAALIGN_BYTE or LL_DMA_MDATAALIGN_HALFWORD or LL_DMA_MDATAALIGN_WORD
504 * @arg LL_DMA_PRIORITY_LOW or LL_DMA_PRIORITY_MEDIUM or LL_DMA_PRIORITY_HIGH or LL_DMA_PRIORITY_VERYHIGH
505 * @retval None
506 */
LL_DMA_ConfigTransfer(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)507 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
508 {
509 MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
510 DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
511 Configuration);
512 }
513
514 /**
515 * @brief Set Data transfer direction (read from peripheral or from memory).
516 * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
517 * CCR MEM2MEM LL_DMA_SetDataTransferDirection
518 * @param DMAx DMAx Instance
519 * @param Channel This parameter can be one of the following values:
520 * @arg LL_DMA_CHANNEL_1
521 * @arg LL_DMA_CHANNEL_2
522 * @arg LL_DMA_CHANNEL_3
523 * @arg LL_DMA_CHANNEL_4
524 * @arg LL_DMA_CHANNEL_5
525 * @arg LL_DMA_CHANNEL_6
526 * @arg LL_DMA_CHANNEL_7
527 * @arg LL_DMA_CHANNEL_8
528 * @param Direction This parameter can be one of the following values:
529 * @arg LL_DMA_DIRECTION_PERIPH_TO_MEMORY
530 * @arg LL_DMA_DIRECTION_MEMORY_TO_PERIPH
531 * @arg LL_DMA_DIRECTION_MEMORY_TO_MEMORY
532 * @retval None
533 */
LL_DMA_SetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Direction)534 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
535 {
536 MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
537 DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
538 }
539
540 /**
541 * @brief Get Data transfer direction (read from peripheral or from memory).
542 * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
543 * CCR MEM2MEM LL_DMA_GetDataTransferDirection
544 * @param DMAx DMAx Instance
545 * @param Channel This parameter can be one of the following values:
546 * @arg LL_DMA_CHANNEL_1
547 * @arg LL_DMA_CHANNEL_2
548 * @arg LL_DMA_CHANNEL_3
549 * @arg LL_DMA_CHANNEL_4
550 * @arg LL_DMA_CHANNEL_5
551 * @arg LL_DMA_CHANNEL_6
552 * @arg LL_DMA_CHANNEL_7
553 * @arg LL_DMA_CHANNEL_8
554 * @retval Returned value can be one of the following values:
555 * @arg LL_DMA_DIRECTION_PERIPH_TO_MEMORY
556 * @arg LL_DMA_DIRECTION_MEMORY_TO_PERIPH
557 * @arg LL_DMA_DIRECTION_MEMORY_TO_MEMORY
558 */
LL_DMA_GetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Channel)559 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
560 {
561 return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
562 DMA_CCR_DIR | DMA_CCR_MEM2MEM));
563 }
564
565 /**
566 * @brief Set DMA mode circular or normal.
567 * @note The circular buffer mode cannot be used if the memory-to-memory
568 * data transfer is configured on the selected Channel.
569 * @rmtoll CCR CIRC LL_DMA_SetMode
570 * @param DMAx DMAx Instance
571 * @param Channel This parameter can be one of the following values:
572 * @arg LL_DMA_CHANNEL_1
573 * @arg LL_DMA_CHANNEL_2
574 * @arg LL_DMA_CHANNEL_3
575 * @arg LL_DMA_CHANNEL_4
576 * @arg LL_DMA_CHANNEL_5
577 * @arg LL_DMA_CHANNEL_6
578 * @arg LL_DMA_CHANNEL_7
579 * @arg LL_DMA_CHANNEL_8
580 * @param Mode This parameter can be one of the following values:
581 * @arg LL_DMA_MODE_NORMAL
582 * @arg LL_DMA_MODE_CIRCULAR
583 * @retval None
584 */
LL_DMA_SetMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Mode)585 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
586 {
587 MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_CIRC,
588 Mode);
589 }
590
591 /**
592 * @brief Get DMA mode circular or normal.
593 * @rmtoll CCR CIRC LL_DMA_GetMode
594 * @param DMAx DMAx Instance
595 * @param Channel This parameter can be one of the following values:
596 * @arg LL_DMA_CHANNEL_1
597 * @arg LL_DMA_CHANNEL_2
598 * @arg LL_DMA_CHANNEL_3
599 * @arg LL_DMA_CHANNEL_4
600 * @arg LL_DMA_CHANNEL_5
601 * @arg LL_DMA_CHANNEL_6
602 * @arg LL_DMA_CHANNEL_7
603 * @arg LL_DMA_CHANNEL_8
604 * @retval Returned value can be one of the following values:
605 * @arg LL_DMA_MODE_NORMAL
606 * @arg LL_DMA_MODE_CIRCULAR
607 */
LL_DMA_GetMode(DMA_TypeDef * DMAx,uint32_t Channel)608 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
609 {
610 return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
611 DMA_CCR_CIRC));
612 }
613
614 /**
615 * @brief Set Peripheral increment mode.
616 * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
617 * @param DMAx DMAx Instance
618 * @param Channel This parameter can be one of the following values:
619 * @arg LL_DMA_CHANNEL_1
620 * @arg LL_DMA_CHANNEL_2
621 * @arg LL_DMA_CHANNEL_3
622 * @arg LL_DMA_CHANNEL_4
623 * @arg LL_DMA_CHANNEL_5
624 * @arg LL_DMA_CHANNEL_6
625 * @arg LL_DMA_CHANNEL_7
626 * @arg LL_DMA_CHANNEL_8
627 * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
628 * @arg LL_DMA_PERIPH_INCREMENT
629 * @arg LL_DMA_PERIPH_NOINCREMENT
630 * @retval None
631 */
LL_DMA_SetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphOrM2MSrcIncMode)632 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
633 {
634 MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PINC,
635 PeriphOrM2MSrcIncMode);
636 }
637
638 /**
639 * @brief Get Peripheral increment mode.
640 * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
641 * @param DMAx DMAx Instance
642 * @param Channel This parameter can be one of the following values:
643 * @arg LL_DMA_CHANNEL_1
644 * @arg LL_DMA_CHANNEL_2
645 * @arg LL_DMA_CHANNEL_3
646 * @arg LL_DMA_CHANNEL_4
647 * @arg LL_DMA_CHANNEL_5
648 * @arg LL_DMA_CHANNEL_6
649 * @arg LL_DMA_CHANNEL_7
650 * @arg LL_DMA_CHANNEL_8
651 * @retval Returned value can be one of the following values:
652 * @arg LL_DMA_PERIPH_INCREMENT
653 * @arg LL_DMA_PERIPH_NOINCREMENT
654 */
LL_DMA_GetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Channel)655 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
656 {
657 return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
658 DMA_CCR_PINC));
659 }
660
661 /**
662 * @brief Set Memory increment mode.
663 * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
664 * @param DMAx DMAx Instance
665 * @param Channel This parameter can be one of the following values:
666 * @arg LL_DMA_CHANNEL_1
667 * @arg LL_DMA_CHANNEL_2
668 * @arg LL_DMA_CHANNEL_3
669 * @arg LL_DMA_CHANNEL_4
670 * @arg LL_DMA_CHANNEL_5
671 * @arg LL_DMA_CHANNEL_6
672 * @arg LL_DMA_CHANNEL_7
673 * @arg LL_DMA_CHANNEL_8
674 * @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
675 * @arg LL_DMA_MEMORY_INCREMENT
676 * @arg LL_DMA_MEMORY_NOINCREMENT
677 * @retval None
678 */
LL_DMA_SetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryOrM2MDstIncMode)679 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
680 {
681 MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_MINC,
682 MemoryOrM2MDstIncMode);
683 }
684
685 /**
686 * @brief Get Memory increment mode.
687 * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
688 * @param DMAx DMAx Instance
689 * @param Channel This parameter can be one of the following values:
690 * @arg LL_DMA_CHANNEL_1
691 * @arg LL_DMA_CHANNEL_2
692 * @arg LL_DMA_CHANNEL_3
693 * @arg LL_DMA_CHANNEL_4
694 * @arg LL_DMA_CHANNEL_5
695 * @arg LL_DMA_CHANNEL_6
696 * @arg LL_DMA_CHANNEL_7
697 * @arg LL_DMA_CHANNEL_8
698 * @retval Returned value can be one of the following values:
699 * @arg LL_DMA_MEMORY_INCREMENT
700 * @arg LL_DMA_MEMORY_NOINCREMENT
701 */
LL_DMA_GetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Channel)702 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
703 {
704 return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
705 DMA_CCR_MINC));
706 }
707
708 /**
709 * @brief Set Peripheral size.
710 * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
711 * @param DMAx DMAx Instance
712 * @param Channel This parameter can be one of the following values:
713 * @arg LL_DMA_CHANNEL_1
714 * @arg LL_DMA_CHANNEL_2
715 * @arg LL_DMA_CHANNEL_3
716 * @arg LL_DMA_CHANNEL_4
717 * @arg LL_DMA_CHANNEL_5
718 * @arg LL_DMA_CHANNEL_6
719 * @arg LL_DMA_CHANNEL_7
720 * @arg LL_DMA_CHANNEL_8
721 * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
722 * @arg LL_DMA_PDATAALIGN_BYTE
723 * @arg LL_DMA_PDATAALIGN_HALFWORD
724 * @arg LL_DMA_PDATAALIGN_WORD
725 * @retval None
726 */
LL_DMA_SetPeriphSize(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphOrM2MSrcDataSize)727 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
728 {
729 MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PSIZE,
730 PeriphOrM2MSrcDataSize);
731 }
732
733 /**
734 * @brief Get Peripheral size.
735 * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
736 * @param DMAx DMAx Instance
737 * @param Channel This parameter can be one of the following values:
738 * @arg LL_DMA_CHANNEL_1
739 * @arg LL_DMA_CHANNEL_2
740 * @arg LL_DMA_CHANNEL_3
741 * @arg LL_DMA_CHANNEL_4
742 * @arg LL_DMA_CHANNEL_5
743 * @arg LL_DMA_CHANNEL_6
744 * @arg LL_DMA_CHANNEL_7
745 * @arg LL_DMA_CHANNEL_8
746 * @retval Returned value can be one of the following values:
747 * @arg LL_DMA_PDATAALIGN_BYTE
748 * @arg LL_DMA_PDATAALIGN_HALFWORD
749 * @arg LL_DMA_PDATAALIGN_WORD
750 */
LL_DMA_GetPeriphSize(DMA_TypeDef * DMAx,uint32_t Channel)751 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
752 {
753 return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
754 DMA_CCR_PSIZE));
755 }
756
757 /**
758 * @brief Set Memory size.
759 * @rmtoll CCR MSIZE LL_DMA_SetMemorySize
760 * @param DMAx DMAx Instance
761 * @param Channel This parameter can be one of the following values:
762 * @arg LL_DMA_CHANNEL_1
763 * @arg LL_DMA_CHANNEL_2
764 * @arg LL_DMA_CHANNEL_3
765 * @arg LL_DMA_CHANNEL_4
766 * @arg LL_DMA_CHANNEL_5
767 * @arg LL_DMA_CHANNEL_6
768 * @arg LL_DMA_CHANNEL_7
769 * @arg LL_DMA_CHANNEL_8
770 * @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
771 * @arg LL_DMA_MDATAALIGN_BYTE
772 * @arg LL_DMA_MDATAALIGN_HALFWORD
773 * @arg LL_DMA_MDATAALIGN_WORD
774 * @retval None
775 */
LL_DMA_SetMemorySize(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryOrM2MDstDataSize)776 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
777 {
778 MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_MSIZE,
779 MemoryOrM2MDstDataSize);
780 }
781
782 /**
783 * @brief Get Memory size.
784 * @rmtoll CCR MSIZE LL_DMA_GetMemorySize
785 * @param DMAx DMAx Instance
786 * @param Channel This parameter can be one of the following values:
787 * @arg LL_DMA_CHANNEL_1
788 * @arg LL_DMA_CHANNEL_2
789 * @arg LL_DMA_CHANNEL_3
790 * @arg LL_DMA_CHANNEL_4
791 * @arg LL_DMA_CHANNEL_5
792 * @arg LL_DMA_CHANNEL_6
793 * @arg LL_DMA_CHANNEL_7
794 * @arg LL_DMA_CHANNEL_8
795 * @retval Returned value can be one of the following values:
796 * @arg LL_DMA_MDATAALIGN_BYTE
797 * @arg LL_DMA_MDATAALIGN_HALFWORD
798 * @arg LL_DMA_MDATAALIGN_WORD
799 */
LL_DMA_GetMemorySize(DMA_TypeDef * DMAx,uint32_t Channel)800 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
801 {
802 return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
803 DMA_CCR_MSIZE));
804 }
805
806 /**
807 * @brief Set Channel priority level.
808 * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
809 * @param DMAx DMAx Instance
810 * @param Channel This parameter can be one of the following values:
811 * @arg LL_DMA_CHANNEL_1
812 * @arg LL_DMA_CHANNEL_2
813 * @arg LL_DMA_CHANNEL_3
814 * @arg LL_DMA_CHANNEL_4
815 * @arg LL_DMA_CHANNEL_5
816 * @arg LL_DMA_CHANNEL_6
817 * @arg LL_DMA_CHANNEL_7
818 * @arg LL_DMA_CHANNEL_8
819 * @param Priority This parameter can be one of the following values:
820 * @arg LL_DMA_PRIORITY_LOW
821 * @arg LL_DMA_PRIORITY_MEDIUM
822 * @arg LL_DMA_PRIORITY_HIGH
823 * @arg LL_DMA_PRIORITY_VERYHIGH
824 * @retval None
825 */
LL_DMA_SetChannelPriorityLevel(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Priority)826 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
827 {
828 MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PL,
829 Priority);
830 }
831
832 /**
833 * @brief Get Channel priority level.
834 * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
835 * @param DMAx DMAx Instance
836 * @param Channel This parameter can be one of the following values:
837 * @arg LL_DMA_CHANNEL_1
838 * @arg LL_DMA_CHANNEL_2
839 * @arg LL_DMA_CHANNEL_3
840 * @arg LL_DMA_CHANNEL_4
841 * @arg LL_DMA_CHANNEL_5
842 * @arg LL_DMA_CHANNEL_6
843 * @arg LL_DMA_CHANNEL_7
844 * @arg LL_DMA_CHANNEL_8
845 * @retval Returned value can be one of the following values:
846 * @arg LL_DMA_PRIORITY_LOW
847 * @arg LL_DMA_PRIORITY_MEDIUM
848 * @arg LL_DMA_PRIORITY_HIGH
849 * @arg LL_DMA_PRIORITY_VERYHIGH
850 */
LL_DMA_GetChannelPriorityLevel(DMA_TypeDef * DMAx,uint32_t Channel)851 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
852 {
853 return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
854 DMA_CCR_PL));
855 }
856
857 /**
858 * @brief Set Number of data to transfer.
859 * @note This action has no effect if
860 * channel is enabled.
861 * @rmtoll CNDTR NDT LL_DMA_SetDataLength
862 * @param DMAx DMAx Instance
863 * @param Channel This parameter can be one of the following values:
864 * @arg LL_DMA_CHANNEL_1
865 * @arg LL_DMA_CHANNEL_2
866 * @arg LL_DMA_CHANNEL_3
867 * @arg LL_DMA_CHANNEL_4
868 * @arg LL_DMA_CHANNEL_5
869 * @arg LL_DMA_CHANNEL_6
870 * @arg LL_DMA_CHANNEL_7
871 * @arg LL_DMA_CHANNEL_8
872 * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
873 * @retval None
874 */
LL_DMA_SetDataLength(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t NbData)875 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
876 {
877 MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CNDTR,
878 DMA_CNDTR_NDT, NbData);
879 }
880
881 /**
882 * @brief Get Number of data to transfer.
883 * @note Once the channel is enabled, the return value indicate the
884 * remaining bytes to be transmitted.
885 * @rmtoll CNDTR NDT LL_DMA_GetDataLength
886 * @param DMAx DMAx Instance
887 * @param Channel This parameter can be one of the following values:
888 * @arg LL_DMA_CHANNEL_1
889 * @arg LL_DMA_CHANNEL_2
890 * @arg LL_DMA_CHANNEL_3
891 * @arg LL_DMA_CHANNEL_4
892 * @arg LL_DMA_CHANNEL_5
893 * @arg LL_DMA_CHANNEL_6
894 * @arg LL_DMA_CHANNEL_7
895 * @arg LL_DMA_CHANNEL_8
896 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
897 */
LL_DMA_GetDataLength(DMA_TypeDef * DMAx,uint32_t Channel)898 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
899 {
900 return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CNDTR,
901 DMA_CNDTR_NDT));
902 }
903
904 /**
905 * @brief Configure the Source and Destination addresses.
906 * @note This API must not be called when the DMA channel is enabled.
907 * @note Each IP using DMA provides an API to get directly the register address (LL_PPP_DMA_GetRegAddr).
908 * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
909 * CMAR MA LL_DMA_ConfigAddresses
910 * @param DMAx DMAx Instance
911 * @param Channel This parameter can be one of the following values:
912 * @arg LL_DMA_CHANNEL_1
913 * @arg LL_DMA_CHANNEL_2
914 * @arg LL_DMA_CHANNEL_3
915 * @arg LL_DMA_CHANNEL_4
916 * @arg LL_DMA_CHANNEL_5
917 * @arg LL_DMA_CHANNEL_6
918 * @arg LL_DMA_CHANNEL_7
919 * @arg LL_DMA_CHANNEL_8
920 * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
921 * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
922 * @param Direction This parameter can be one of the following values:
923 * @arg LL_DMA_DIRECTION_PERIPH_TO_MEMORY
924 * @arg LL_DMA_DIRECTION_MEMORY_TO_PERIPH
925 * @arg LL_DMA_DIRECTION_MEMORY_TO_MEMORY
926 * @retval None
927 */
LL_DMA_ConfigAddresses(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddress,uint32_t DstAddress,uint32_t Direction)928 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
929 uint32_t DstAddress, uint32_t Direction)
930 {
931 /* Direction Memory to Periph */
932 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
933 {
934 WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, SrcAddress);
935 WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, DstAddress);
936 }
937 /* Direction Periph to Memory and Memory to Memory */
938 else
939 {
940 WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, SrcAddress);
941 WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, DstAddress);
942 }
943 }
944
945 /**
946 * @brief Set the Memory address.
947 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
948 * @note This API must not be called when the DMA channel is enabled.
949 * @rmtoll CMAR MA LL_DMA_SetMemoryAddress
950 * @param DMAx DMAx Instance
951 * @param Channel This parameter can be one of the following values:
952 * @arg LL_DMA_CHANNEL_1
953 * @arg LL_DMA_CHANNEL_2
954 * @arg LL_DMA_CHANNEL_3
955 * @arg LL_DMA_CHANNEL_4
956 * @arg LL_DMA_CHANNEL_5
957 * @arg LL_DMA_CHANNEL_6
958 * @arg LL_DMA_CHANNEL_7
959 * @arg LL_DMA_CHANNEL_8
960 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
961 * @retval None
962 */
LL_DMA_SetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)963 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
964 {
965 WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, MemoryAddress);
966 }
967
968 /**
969 * @brief Set the Peripheral address.
970 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
971 * @note This API must not be called when the DMA channel is enabled.
972 * @rmtoll CPAR PA LL_DMA_SetPeriphAddress
973 * @param DMAx DMAx Instance
974 * @param Channel This parameter can be one of the following values:
975 * @arg LL_DMA_CHANNEL_1
976 * @arg LL_DMA_CHANNEL_2
977 * @arg LL_DMA_CHANNEL_3
978 * @arg LL_DMA_CHANNEL_4
979 * @arg LL_DMA_CHANNEL_5
980 * @arg LL_DMA_CHANNEL_6
981 * @arg LL_DMA_CHANNEL_7
982 * @arg LL_DMA_CHANNEL_8
983 * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
984 * @retval None
985 */
LL_DMA_SetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphAddress)986 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
987 {
988 WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, PeriphAddress);
989 }
990
991 /**
992 * @brief Get Memory address.
993 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
994 * @rmtoll CMAR MA LL_DMA_GetMemoryAddress
995 * @param DMAx DMAx Instance
996 * @param Channel This parameter can be one of the following values:
997 * @arg LL_DMA_CHANNEL_1
998 * @arg LL_DMA_CHANNEL_2
999 * @arg LL_DMA_CHANNEL_3
1000 * @arg LL_DMA_CHANNEL_4
1001 * @arg LL_DMA_CHANNEL_5
1002 * @arg LL_DMA_CHANNEL_6
1003 * @arg LL_DMA_CHANNEL_7
1004 * @arg LL_DMA_CHANNEL_8
1005 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1006 */
LL_DMA_GetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Channel)1007 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1008 {
1009 return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR));
1010 }
1011
1012 /**
1013 * @brief Get Peripheral address.
1014 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1015 * @rmtoll CPAR PA LL_DMA_GetPeriphAddress
1016 * @param DMAx DMAx Instance
1017 * @param Channel This parameter can be one of the following values:
1018 * @arg LL_DMA_CHANNEL_1
1019 * @arg LL_DMA_CHANNEL_2
1020 * @arg LL_DMA_CHANNEL_3
1021 * @arg LL_DMA_CHANNEL_4
1022 * @arg LL_DMA_CHANNEL_5
1023 * @arg LL_DMA_CHANNEL_6
1024 * @arg LL_DMA_CHANNEL_7
1025 * @arg LL_DMA_CHANNEL_8
1026 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1027 */
LL_DMA_GetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Channel)1028 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1029 {
1030 return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR));
1031 }
1032
1033 /**
1034 * @brief Set the Memory to Memory Source address.
1035 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1036 * @note This API must not be called when the DMA channel is enabled.
1037 * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
1038 * @param DMAx DMAx Instance
1039 * @param Channel This parameter can be one of the following values:
1040 * @arg LL_DMA_CHANNEL_1
1041 * @arg LL_DMA_CHANNEL_2
1042 * @arg LL_DMA_CHANNEL_3
1043 * @arg LL_DMA_CHANNEL_4
1044 * @arg LL_DMA_CHANNEL_5
1045 * @arg LL_DMA_CHANNEL_6
1046 * @arg LL_DMA_CHANNEL_7
1047 * @arg LL_DMA_CHANNEL_8
1048 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1049 * @retval None
1050 */
LL_DMA_SetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1051 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1052 {
1053 WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, MemoryAddress);
1054 }
1055
1056 /**
1057 * @brief Set the Memory to Memory Destination address.
1058 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1059 * @note This API must not be called when the DMA channel is enabled.
1060 * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
1061 * @param DMAx DMAx Instance
1062 * @param Channel This parameter can be one of the following values:
1063 * @arg LL_DMA_CHANNEL_1
1064 * @arg LL_DMA_CHANNEL_2
1065 * @arg LL_DMA_CHANNEL_3
1066 * @arg LL_DMA_CHANNEL_4
1067 * @arg LL_DMA_CHANNEL_5
1068 * @arg LL_DMA_CHANNEL_6
1069 * @arg LL_DMA_CHANNEL_7
1070 * @arg LL_DMA_CHANNEL_8
1071 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1072 * @retval None
1073 */
LL_DMA_SetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1074 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1075 {
1076 WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, MemoryAddress);
1077 }
1078
1079 /**
1080 * @brief Get the Memory to Memory Source address.
1081 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1082 * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
1083 * @param DMAx DMAx Instance
1084 * @param Channel This parameter can be one of the following values:
1085 * @arg LL_DMA_CHANNEL_1
1086 * @arg LL_DMA_CHANNEL_2
1087 * @arg LL_DMA_CHANNEL_3
1088 * @arg LL_DMA_CHANNEL_4
1089 * @arg LL_DMA_CHANNEL_5
1090 * @arg LL_DMA_CHANNEL_6
1091 * @arg LL_DMA_CHANNEL_7
1092 * @arg LL_DMA_CHANNEL_8
1093 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1094 */
LL_DMA_GetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Channel)1095 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1096 {
1097 return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR));
1098 }
1099
1100 /**
1101 * @brief Get the Memory to Memory Destination address.
1102 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1103 * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
1104 * @param DMAx DMAx Instance
1105 * @param Channel This parameter can be one of the following values:
1106 * @arg LL_DMA_CHANNEL_1
1107 * @arg LL_DMA_CHANNEL_2
1108 * @arg LL_DMA_CHANNEL_3
1109 * @arg LL_DMA_CHANNEL_4
1110 * @arg LL_DMA_CHANNEL_5
1111 * @arg LL_DMA_CHANNEL_6
1112 * @arg LL_DMA_CHANNEL_7
1113 * @arg LL_DMA_CHANNEL_8
1114 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1115 */
LL_DMA_GetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Channel)1116 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1117 {
1118 return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR));
1119 }
1120
1121 /**
1122 * @brief Set DMA request for DMA Channels on DMAMUX Channel x.
1123 * @note DMAMUX channel 0 to 7 are mapped to DMA1 channel 1 to 8.
1124 * @rmtoll CxCR DMAREQ_ID LL_DMA_SetPeriphRequest
1125 * @param DMAx DMAx Instance
1126 * @param Channel This parameter can be one of the following values:
1127 * @arg LL_DMA_CHANNEL_1
1128 * @arg LL_DMA_CHANNEL_2
1129 * @arg LL_DMA_CHANNEL_3
1130 * @arg LL_DMA_CHANNEL_4
1131 * @arg LL_DMA_CHANNEL_5
1132 * @arg LL_DMA_CHANNEL_6
1133 * @arg LL_DMA_CHANNEL_7
1134 * @arg LL_DMA_CHANNEL_8
1135 * @param Request This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST
1136 * @retval None
1137 */
LL_DMA_SetPeriphRequest(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Request)1138 __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request)
1139 {
1140 MODIFY_REG(__LL_DMA_INSTANCE_TO_DMAMUX_CCR(DMAx, Channel - 1U)->CxCR, DMAMUX_CxCR_DMAREQ_ID, Request);
1141 }
1142
1143 /**
1144 * @brief Get DMA request for DMA Channels on DMAMUX Channel x.
1145 * @note DMAMUX channel 0 to 7 are mapped to DMA1 channel 1 to 8.
1146 * @rmtoll CxCR DMAREQ_ID LL_DMA_GetPeriphRequest
1147 * @param DMAx DMAx Instance
1148 * @param Channel This parameter can be one of the following values:
1149 * @arg LL_DMA_CHANNEL_1
1150 * @arg LL_DMA_CHANNEL_2
1151 * @arg LL_DMA_CHANNEL_3
1152 * @arg LL_DMA_CHANNEL_4
1153 * @arg LL_DMA_CHANNEL_5
1154 * @arg LL_DMA_CHANNEL_6
1155 * @arg LL_DMA_CHANNEL_7
1156 * @arg LL_DMA_CHANNEL_8
1157 * @retval Returned This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST
1158 */
LL_DMA_GetPeriphRequest(DMA_TypeDef * DMAx,uint32_t Channel)1159 __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
1160 {
1161 return (READ_BIT(__LL_DMA_INSTANCE_TO_DMAMUX_CCR(DMAx, Channel - 1U)->CxCR, DMAMUX_CxCR_DMAREQ_ID));
1162 }
1163
1164 /**
1165 * @}
1166 */
1167
1168 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
1169 * @{
1170 */
1171
1172 /**
1173 * @brief Get Channel 1 global interrupt flag.
1174 * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
1175 * @param DMAx DMAx Instance
1176 * @retval State of bit (1 or 0).
1177 */
LL_DMA_IsActiveFlag_GI1(DMA_TypeDef * DMAx)1178 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
1179 {
1180 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)) ? 1UL : 0UL);
1181 }
1182
1183 /**
1184 * @brief Get Channel 2 global interrupt flag.
1185 * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
1186 * @param DMAx DMAx Instance
1187 * @retval State of bit (1 or 0).
1188 */
LL_DMA_IsActiveFlag_GI2(DMA_TypeDef * DMAx)1189 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
1190 {
1191 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)) ? 1UL : 0UL);
1192 }
1193
1194 /**
1195 * @brief Get Channel 3 global interrupt flag.
1196 * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
1197 * @param DMAx DMAx Instance
1198 * @retval State of bit (1 or 0).
1199 */
LL_DMA_IsActiveFlag_GI3(DMA_TypeDef * DMAx)1200 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
1201 {
1202 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)) ? 1UL : 0UL);
1203 }
1204
1205 /**
1206 * @brief Get Channel 4 global interrupt flag.
1207 * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
1208 * @param DMAx DMAx Instance
1209 * @retval State of bit (1 or 0).
1210 */
LL_DMA_IsActiveFlag_GI4(DMA_TypeDef * DMAx)1211 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
1212 {
1213 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)) ? 1UL : 0UL);
1214 }
1215
1216 /**
1217 * @brief Get Channel 5 global interrupt flag.
1218 * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
1219 * @param DMAx DMAx Instance
1220 * @retval State of bit (1 or 0).
1221 */
LL_DMA_IsActiveFlag_GI5(DMA_TypeDef * DMAx)1222 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
1223 {
1224 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)) ? 1UL : 0UL);
1225 }
1226
1227 /**
1228 * @brief Get Channel 6 global interrupt flag.
1229 * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
1230 * @param DMAx DMAx Instance
1231 * @retval State of bit (1 or 0).
1232 */
LL_DMA_IsActiveFlag_GI6(DMA_TypeDef * DMAx)1233 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
1234 {
1235 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)) ? 1UL : 0UL);
1236 }
1237
1238 /**
1239 * @brief Get Channel 7 global interrupt flag.
1240 * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
1241 * @param DMAx DMAx Instance
1242 * @retval State of bit (1 or 0).
1243 */
LL_DMA_IsActiveFlag_GI7(DMA_TypeDef * DMAx)1244 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
1245 {
1246 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)) ? 1UL : 0UL);
1247 }
1248
1249 /**
1250 * @brief Get Channel 8 global interrupt flag.
1251 * @rmtoll ISR GIF8 LL_DMA_IsActiveFlag_GI8
1252 * @param DMAx DMAx Instance
1253 * @retval State of bit (1 or 0).
1254 */
LL_DMA_IsActiveFlag_GI8(DMA_TypeDef * DMAx)1255 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI8(DMA_TypeDef *DMAx)
1256 {
1257 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF8) == (DMA_ISR_GIF8)) ? 1UL : 0UL);
1258 }
1259
1260 /**
1261 * @brief Get Channel 1 transfer complete flag.
1262 * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
1263 * @param DMAx DMAx Instance
1264 * @retval State of bit (1 or 0).
1265 */
LL_DMA_IsActiveFlag_TC1(DMA_TypeDef * DMAx)1266 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
1267 {
1268 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)) ? 1UL : 0UL);
1269 }
1270
1271 /**
1272 * @brief Get Channel 2 transfer complete flag.
1273 * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
1274 * @param DMAx DMAx Instance
1275 * @retval State of bit (1 or 0).
1276 */
LL_DMA_IsActiveFlag_TC2(DMA_TypeDef * DMAx)1277 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
1278 {
1279 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)) ? 1UL : 0UL);
1280 }
1281
1282 /**
1283 * @brief Get Channel 3 transfer complete flag.
1284 * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
1285 * @param DMAx DMAx Instance
1286 * @retval State of bit (1 or 0).
1287 */
LL_DMA_IsActiveFlag_TC3(DMA_TypeDef * DMAx)1288 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
1289 {
1290 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)) ? 1UL : 0UL);
1291 }
1292
1293 /**
1294 * @brief Get Channel 4 transfer complete flag.
1295 * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
1296 * @param DMAx DMAx Instance
1297 * @retval State of bit (1 or 0).
1298 */
LL_DMA_IsActiveFlag_TC4(DMA_TypeDef * DMAx)1299 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
1300 {
1301 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)) ? 1UL : 0UL);
1302 }
1303
1304 /**
1305 * @brief Get Channel 5 transfer complete flag.
1306 * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
1307 * @param DMAx DMAx Instance
1308 * @retval State of bit (1 or 0).
1309 */
LL_DMA_IsActiveFlag_TC5(DMA_TypeDef * DMAx)1310 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
1311 {
1312 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)) ? 1UL : 0UL);
1313 }
1314
1315 /**
1316 * @brief Get Channel 6 transfer complete flag.
1317 * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
1318 * @param DMAx DMAx Instance
1319 * @retval State of bit (1 or 0).
1320 */
LL_DMA_IsActiveFlag_TC6(DMA_TypeDef * DMAx)1321 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
1322 {
1323 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)) ? 1UL : 0UL);
1324 }
1325
1326 /**
1327 * @brief Get Channel 7 transfer complete flag.
1328 * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
1329 * @param DMAx DMAx Instance
1330 * @retval State of bit (1 or 0).
1331 */
LL_DMA_IsActiveFlag_TC7(DMA_TypeDef * DMAx)1332 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
1333 {
1334 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)) ? 1UL : 0UL);
1335 }
1336
1337 /**
1338 * @brief Get Channel 8 transfer complete flag.
1339 * @rmtoll ISR TCIF8 LL_DMA_IsActiveFlag_TC8
1340 * @param DMAx DMAx Instance
1341 * @retval State of bit (1 or 0).
1342 */
LL_DMA_IsActiveFlag_TC8(DMA_TypeDef * DMAx)1343 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC8(DMA_TypeDef *DMAx)
1344 {
1345 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF8) == (DMA_ISR_TCIF8)) ? 1UL : 0UL);
1346 }
1347
1348 /**
1349 * @brief Get Channel 1 half transfer flag.
1350 * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
1351 * @param DMAx DMAx Instance
1352 * @retval State of bit (1 or 0).
1353 */
LL_DMA_IsActiveFlag_HT1(DMA_TypeDef * DMAx)1354 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
1355 {
1356 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)) ? 1UL : 0UL);
1357 }
1358
1359 /**
1360 * @brief Get Channel 2 half transfer flag.
1361 * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
1362 * @param DMAx DMAx Instance
1363 * @retval State of bit (1 or 0).
1364 */
LL_DMA_IsActiveFlag_HT2(DMA_TypeDef * DMAx)1365 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
1366 {
1367 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)) ? 1UL : 0UL);
1368 }
1369
1370 /**
1371 * @brief Get Channel 3 half transfer flag.
1372 * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
1373 * @param DMAx DMAx Instance
1374 * @retval State of bit (1 or 0).
1375 */
LL_DMA_IsActiveFlag_HT3(DMA_TypeDef * DMAx)1376 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
1377 {
1378 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)) ? 1UL : 0UL);
1379 }
1380
1381 /**
1382 * @brief Get Channel 4 half transfer flag.
1383 * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
1384 * @param DMAx DMAx Instance
1385 * @retval State of bit (1 or 0).
1386 */
LL_DMA_IsActiveFlag_HT4(DMA_TypeDef * DMAx)1387 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
1388 {
1389 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)) ? 1UL : 0UL);
1390 }
1391
1392 /**
1393 * @brief Get Channel 5 half transfer flag.
1394 * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
1395 * @param DMAx DMAx Instance
1396 * @retval State of bit (1 or 0).
1397 */
LL_DMA_IsActiveFlag_HT5(DMA_TypeDef * DMAx)1398 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
1399 {
1400 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)) ? 1UL : 0UL);
1401 }
1402
1403 /**
1404 * @brief Get Channel 6 half transfer flag.
1405 * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
1406 * @param DMAx DMAx Instance
1407 * @retval State of bit (1 or 0).
1408 */
LL_DMA_IsActiveFlag_HT6(DMA_TypeDef * DMAx)1409 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
1410 {
1411 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)) ? 1UL : 0UL);
1412 }
1413
1414 /**
1415 * @brief Get Channel 7 half transfer flag.
1416 * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
1417 * @param DMAx DMAx Instance
1418 * @retval State of bit (1 or 0).
1419 */
LL_DMA_IsActiveFlag_HT7(DMA_TypeDef * DMAx)1420 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
1421 {
1422 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)) ? 1UL : 0UL);
1423 }
1424
1425 /**
1426 * @brief Get Channel 8 half transfer flag.
1427 * @rmtoll ISR HTIF8 LL_DMA_IsActiveFlag_HT8
1428 * @param DMAx DMAx Instance
1429 * @retval State of bit (1 or 0).
1430 */
LL_DMA_IsActiveFlag_HT8(DMA_TypeDef * DMAx)1431 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT8(DMA_TypeDef *DMAx)
1432 {
1433 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF8) == (DMA_ISR_HTIF8)) ? 1UL : 0UL);
1434 }
1435
1436 /**
1437 * @brief Get Channel 1 transfer error flag.
1438 * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
1439 * @param DMAx DMAx Instance
1440 * @retval State of bit (1 or 0).
1441 */
LL_DMA_IsActiveFlag_TE1(DMA_TypeDef * DMAx)1442 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
1443 {
1444 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)) ? 1UL : 0UL);
1445 }
1446
1447 /**
1448 * @brief Get Channel 2 transfer error flag.
1449 * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
1450 * @param DMAx DMAx Instance
1451 * @retval State of bit (1 or 0).
1452 */
LL_DMA_IsActiveFlag_TE2(DMA_TypeDef * DMAx)1453 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
1454 {
1455 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)) ? 1UL : 0UL);
1456 }
1457
1458 /**
1459 * @brief Get Channel 3 transfer error flag.
1460 * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
1461 * @param DMAx DMAx Instance
1462 * @retval State of bit (1 or 0).
1463 */
LL_DMA_IsActiveFlag_TE3(DMA_TypeDef * DMAx)1464 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
1465 {
1466 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)) ? 1UL : 0UL);
1467 }
1468
1469 /**
1470 * @brief Get Channel 4 transfer error flag.
1471 * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
1472 * @param DMAx DMAx Instance
1473 * @retval State of bit (1 or 0).
1474 */
LL_DMA_IsActiveFlag_TE4(DMA_TypeDef * DMAx)1475 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
1476 {
1477 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)) ? 1UL : 0UL);
1478 }
1479
1480 /**
1481 * @brief Get Channel 5 transfer error flag.
1482 * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
1483 * @param DMAx DMAx Instance
1484 * @retval State of bit (1 or 0).
1485 */
LL_DMA_IsActiveFlag_TE5(DMA_TypeDef * DMAx)1486 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
1487 {
1488 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)) ? 1UL : 0UL);
1489 }
1490
1491 /**
1492 * @brief Get Channel 6 transfer error flag.
1493 * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
1494 * @param DMAx DMAx Instance
1495 * @retval State of bit (1 or 0).
1496 */
LL_DMA_IsActiveFlag_TE6(DMA_TypeDef * DMAx)1497 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
1498 {
1499 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)) ? 1UL : 0UL);
1500 }
1501
1502 /**
1503 * @brief Get Channel 7 transfer error flag.
1504 * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
1505 * @param DMAx DMAx Instance
1506 * @retval State of bit (1 or 0).
1507 */
LL_DMA_IsActiveFlag_TE7(DMA_TypeDef * DMAx)1508 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
1509 {
1510 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)) ? 1UL : 0UL);
1511 }
1512
1513 /**
1514 * @brief Get Channel 8 transfer error flag.
1515 * @rmtoll ISR TEIF8 LL_DMA_IsActiveFlag_TE8
1516 * @param DMAx DMAx Instance
1517 * @retval State of bit (1 or 0).
1518 */
LL_DMA_IsActiveFlag_TE8(DMA_TypeDef * DMAx)1519 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE8(DMA_TypeDef *DMAx)
1520 {
1521 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF8) == (DMA_ISR_TEIF8)) ? 1UL : 0UL);
1522 }
1523
1524 /**
1525 * @brief Clear Channel 1 global interrupt flag.
1526 * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
1527 * @param DMAx DMAx Instance
1528 * @retval None
1529 */
LL_DMA_ClearFlag_GI1(DMA_TypeDef * DMAx)1530 __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
1531 {
1532 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
1533 }
1534
1535 /**
1536 * @brief Clear Channel 2 global interrupt flag.
1537 * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
1538 * @param DMAx DMAx Instance
1539 * @retval None
1540 */
LL_DMA_ClearFlag_GI2(DMA_TypeDef * DMAx)1541 __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
1542 {
1543 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
1544 }
1545
1546 /**
1547 * @brief Clear Channel 3 global interrupt flag.
1548 * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
1549 * @param DMAx DMAx Instance
1550 * @retval None
1551 */
LL_DMA_ClearFlag_GI3(DMA_TypeDef * DMAx)1552 __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
1553 {
1554 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
1555 }
1556
1557 /**
1558 * @brief Clear Channel 4 global interrupt flag.
1559 * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
1560 * @param DMAx DMAx Instance
1561 * @retval None
1562 */
LL_DMA_ClearFlag_GI4(DMA_TypeDef * DMAx)1563 __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
1564 {
1565 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
1566 }
1567
1568 /**
1569 * @brief Clear Channel 5 global interrupt flag.
1570 * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
1571 * @param DMAx DMAx Instance
1572 * @retval None
1573 */
LL_DMA_ClearFlag_GI5(DMA_TypeDef * DMAx)1574 __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
1575 {
1576 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
1577 }
1578
1579 /**
1580 * @brief Clear Channel 6 global interrupt flag.
1581 * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
1582 * @param DMAx DMAx Instance
1583 * @retval None
1584 */
LL_DMA_ClearFlag_GI6(DMA_TypeDef * DMAx)1585 __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
1586 {
1587 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
1588 }
1589
1590 /**
1591 * @brief Clear Channel 7 global interrupt flag.
1592 * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
1593 * @param DMAx DMAx Instance
1594 * @retval None
1595 */
LL_DMA_ClearFlag_GI7(DMA_TypeDef * DMAx)1596 __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
1597 {
1598 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
1599 }
1600
1601 /**
1602 * @brief Clear Channel 8 global interrupt flag.
1603 * @rmtoll IFCR CGIF8 LL_DMA_ClearFlag_GI8
1604 * @param DMAx DMAx Instance
1605 * @retval None
1606 */
LL_DMA_ClearFlag_GI8(DMA_TypeDef * DMAx)1607 __STATIC_INLINE void LL_DMA_ClearFlag_GI8(DMA_TypeDef *DMAx)
1608 {
1609 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF8);
1610 }
1611
1612 /**
1613 * @brief Clear Channel 1 transfer complete flag.
1614 * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
1615 * @param DMAx DMAx Instance
1616 * @retval None
1617 */
LL_DMA_ClearFlag_TC1(DMA_TypeDef * DMAx)1618 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
1619 {
1620 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
1621 }
1622
1623 /**
1624 * @brief Clear Channel 2 transfer complete flag.
1625 * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
1626 * @param DMAx DMAx Instance
1627 * @retval None
1628 */
LL_DMA_ClearFlag_TC2(DMA_TypeDef * DMAx)1629 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
1630 {
1631 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
1632 }
1633
1634 /**
1635 * @brief Clear Channel 3 transfer complete flag.
1636 * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
1637 * @param DMAx DMAx Instance
1638 * @retval None
1639 */
LL_DMA_ClearFlag_TC3(DMA_TypeDef * DMAx)1640 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
1641 {
1642 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
1643 }
1644
1645 /**
1646 * @brief Clear Channel 4 transfer complete flag.
1647 * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
1648 * @param DMAx DMAx Instance
1649 * @retval None
1650 */
LL_DMA_ClearFlag_TC4(DMA_TypeDef * DMAx)1651 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
1652 {
1653 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
1654 }
1655
1656 /**
1657 * @brief Clear Channel 5 transfer complete flag.
1658 * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
1659 * @param DMAx DMAx Instance
1660 * @retval None
1661 */
LL_DMA_ClearFlag_TC5(DMA_TypeDef * DMAx)1662 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
1663 {
1664 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
1665 }
1666
1667 /**
1668 * @brief Clear Channel 6 transfer complete flag.
1669 * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
1670 * @param DMAx DMAx Instance
1671 * @retval None
1672 */
LL_DMA_ClearFlag_TC6(DMA_TypeDef * DMAx)1673 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
1674 {
1675 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
1676 }
1677
1678 /**
1679 * @brief Clear Channel 7 transfer complete flag.
1680 * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
1681 * @param DMAx DMAx Instance
1682 * @retval None
1683 */
LL_DMA_ClearFlag_TC7(DMA_TypeDef * DMAx)1684 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
1685 {
1686 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
1687 }
1688
1689 /**
1690 * @brief Clear Channel 8 transfer complete flag.
1691 * @rmtoll IFCR CTCIF8 LL_DMA_ClearFlag_TC8
1692 * @param DMAx DMAx Instance
1693 * @retval None
1694 */
LL_DMA_ClearFlag_TC8(DMA_TypeDef * DMAx)1695 __STATIC_INLINE void LL_DMA_ClearFlag_TC8(DMA_TypeDef *DMAx)
1696 {
1697 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF8);
1698 }
1699
1700 /**
1701 * @brief Clear Channel 1 half transfer flag.
1702 * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
1703 * @param DMAx DMAx Instance
1704 * @retval None
1705 */
LL_DMA_ClearFlag_HT1(DMA_TypeDef * DMAx)1706 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
1707 {
1708 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
1709 }
1710
1711 /**
1712 * @brief Clear Channel 2 half transfer flag.
1713 * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
1714 * @param DMAx DMAx Instance
1715 * @retval None
1716 */
LL_DMA_ClearFlag_HT2(DMA_TypeDef * DMAx)1717 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
1718 {
1719 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
1720 }
1721
1722 /**
1723 * @brief Clear Channel 3 half transfer flag.
1724 * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
1725 * @param DMAx DMAx Instance
1726 * @retval None
1727 */
LL_DMA_ClearFlag_HT3(DMA_TypeDef * DMAx)1728 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
1729 {
1730 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
1731 }
1732
1733 /**
1734 * @brief Clear Channel 4 half transfer flag.
1735 * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
1736 * @param DMAx DMAx Instance
1737 * @retval None
1738 */
LL_DMA_ClearFlag_HT4(DMA_TypeDef * DMAx)1739 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
1740 {
1741 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
1742 }
1743
1744 /**
1745 * @brief Clear Channel 5 half transfer flag.
1746 * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
1747 * @param DMAx DMAx Instance
1748 * @retval None
1749 */
LL_DMA_ClearFlag_HT5(DMA_TypeDef * DMAx)1750 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
1751 {
1752 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
1753 }
1754
1755 /**
1756 * @brief Clear Channel 6 half transfer flag.
1757 * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
1758 * @param DMAx DMAx Instance
1759 * @retval None
1760 */
LL_DMA_ClearFlag_HT6(DMA_TypeDef * DMAx)1761 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
1762 {
1763 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
1764 }
1765
1766 /**
1767 * @brief Clear Channel 7 half transfer flag.
1768 * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
1769 * @param DMAx DMAx Instance
1770 * @retval None
1771 */
LL_DMA_ClearFlag_HT7(DMA_TypeDef * DMAx)1772 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
1773 {
1774 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
1775 }
1776
1777 /**
1778 * @brief Clear Channel 8 half transfer flag.
1779 * @rmtoll IFCR CHTIF8 LL_DMA_ClearFlag_HT8
1780 * @param DMAx DMAx Instance
1781 * @retval None
1782 */
LL_DMA_ClearFlag_HT8(DMA_TypeDef * DMAx)1783 __STATIC_INLINE void LL_DMA_ClearFlag_HT8(DMA_TypeDef *DMAx)
1784 {
1785 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF8);
1786 }
1787
1788 /**
1789 * @brief Clear Channel 1 transfer error flag.
1790 * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
1791 * @param DMAx DMAx Instance
1792 * @retval None
1793 */
LL_DMA_ClearFlag_TE1(DMA_TypeDef * DMAx)1794 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
1795 {
1796 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
1797 }
1798
1799 /**
1800 * @brief Clear Channel 2 transfer error flag.
1801 * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
1802 * @param DMAx DMAx Instance
1803 * @retval None
1804 */
LL_DMA_ClearFlag_TE2(DMA_TypeDef * DMAx)1805 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
1806 {
1807 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
1808 }
1809
1810 /**
1811 * @brief Clear Channel 3 transfer error flag.
1812 * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
1813 * @param DMAx DMAx Instance
1814 * @retval None
1815 */
LL_DMA_ClearFlag_TE3(DMA_TypeDef * DMAx)1816 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
1817 {
1818 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
1819 }
1820
1821 /**
1822 * @brief Clear Channel 4 transfer error flag.
1823 * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
1824 * @param DMAx DMAx Instance
1825 * @retval None
1826 */
LL_DMA_ClearFlag_TE4(DMA_TypeDef * DMAx)1827 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
1828 {
1829 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
1830 }
1831
1832 /**
1833 * @brief Clear Channel 5 transfer error flag.
1834 * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
1835 * @param DMAx DMAx Instance
1836 * @retval None
1837 */
LL_DMA_ClearFlag_TE5(DMA_TypeDef * DMAx)1838 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
1839 {
1840 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
1841 }
1842
1843 /**
1844 * @brief Clear Channel 6 transfer error flag.
1845 * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
1846 * @param DMAx DMAx Instance
1847 * @retval None
1848 */
LL_DMA_ClearFlag_TE6(DMA_TypeDef * DMAx)1849 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
1850 {
1851 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
1852 }
1853
1854 /**
1855 * @brief Clear Channel 7 transfer error flag.
1856 * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
1857 * @param DMAx DMAx Instance
1858 * @retval None
1859 */
LL_DMA_ClearFlag_TE7(DMA_TypeDef * DMAx)1860 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
1861 {
1862 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
1863 }
1864
1865 /**
1866 * @brief Clear Channel 8 transfer error flag.
1867 * @rmtoll IFCR CTEIF8 LL_DMA_ClearFlag_TE8
1868 * @param DMAx DMAx Instance
1869 * @retval None
1870 */
LL_DMA_ClearFlag_TE8(DMA_TypeDef * DMAx)1871 __STATIC_INLINE void LL_DMA_ClearFlag_TE8(DMA_TypeDef *DMAx)
1872 {
1873 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF8);
1874 }
1875
1876 /**
1877 * @}
1878 */
1879
1880 /** @defgroup DMA_LL_EF_IT_Management IT_Management
1881 * @{
1882 */
1883 /**
1884 * @brief Enable Transfer complete interrupt.
1885 * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
1886 * @param DMAx DMAx Instance
1887 * @param Channel This parameter can be one of the following values:
1888 * @arg LL_DMA_CHANNEL_1
1889 * @arg LL_DMA_CHANNEL_2
1890 * @arg LL_DMA_CHANNEL_3
1891 * @arg LL_DMA_CHANNEL_4
1892 * @arg LL_DMA_CHANNEL_5
1893 * @arg LL_DMA_CHANNEL_6
1894 * @arg LL_DMA_CHANNEL_7
1895 * @arg LL_DMA_CHANNEL_8
1896 * @retval None
1897 */
LL_DMA_EnableIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)1898 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
1899 {
1900 SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TCIE);
1901 }
1902
1903 /**
1904 * @brief Enable Half transfer interrupt.
1905 * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
1906 * @param DMAx DMAx Instance
1907 * @param Channel This parameter can be one of the following values:
1908 * @arg LL_DMA_CHANNEL_1
1909 * @arg LL_DMA_CHANNEL_2
1910 * @arg LL_DMA_CHANNEL_3
1911 * @arg LL_DMA_CHANNEL_4
1912 * @arg LL_DMA_CHANNEL_5
1913 * @arg LL_DMA_CHANNEL_6
1914 * @arg LL_DMA_CHANNEL_7
1915 * @arg LL_DMA_CHANNEL_8
1916 * @retval None
1917 */
LL_DMA_EnableIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)1918 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
1919 {
1920 SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_HTIE);
1921 }
1922
1923 /**
1924 * @brief Enable Transfer error interrupt.
1925 * @rmtoll CCR TEIE LL_DMA_EnableIT_TE
1926 * @param DMAx DMAx Instance
1927 * @param Channel This parameter can be one of the following values:
1928 * @arg LL_DMA_CHANNEL_1
1929 * @arg LL_DMA_CHANNEL_2
1930 * @arg LL_DMA_CHANNEL_3
1931 * @arg LL_DMA_CHANNEL_4
1932 * @arg LL_DMA_CHANNEL_5
1933 * @arg LL_DMA_CHANNEL_6
1934 * @arg LL_DMA_CHANNEL_7
1935 * @arg LL_DMA_CHANNEL_8
1936 * @retval None
1937 */
LL_DMA_EnableIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)1938 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
1939 {
1940 SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE);
1941 }
1942
1943 /**
1944 * @brief Disable Transfer complete interrupt.
1945 * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
1946 * @param DMAx DMAx Instance
1947 * @param Channel This parameter can be one of the following values:
1948 * @arg LL_DMA_CHANNEL_1
1949 * @arg LL_DMA_CHANNEL_2
1950 * @arg LL_DMA_CHANNEL_3
1951 * @arg LL_DMA_CHANNEL_4
1952 * @arg LL_DMA_CHANNEL_5
1953 * @arg LL_DMA_CHANNEL_6
1954 * @arg LL_DMA_CHANNEL_7
1955 * @arg LL_DMA_CHANNEL_8
1956 * @retval None
1957 */
LL_DMA_DisableIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)1958 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
1959 {
1960 CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TCIE);
1961 }
1962
1963 /**
1964 * @brief Disable Half transfer interrupt.
1965 * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
1966 * @param DMAx DMAx Instance
1967 * @param Channel This parameter can be one of the following values:
1968 * @arg LL_DMA_CHANNEL_1
1969 * @arg LL_DMA_CHANNEL_2
1970 * @arg LL_DMA_CHANNEL_3
1971 * @arg LL_DMA_CHANNEL_4
1972 * @arg LL_DMA_CHANNEL_5
1973 * @arg LL_DMA_CHANNEL_6
1974 * @arg LL_DMA_CHANNEL_7
1975 * @arg LL_DMA_CHANNEL_8
1976 * @retval None
1977 */
LL_DMA_DisableIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)1978 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
1979 {
1980 CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_HTIE);
1981 }
1982
1983 /**
1984 * @brief Disable Transfer error interrupt.
1985 * @rmtoll CCR TEIE LL_DMA_DisableIT_TE
1986 * @param DMAx DMAx Instance
1987 * @param Channel This parameter can be one of the following values:
1988 * @arg LL_DMA_CHANNEL_1
1989 * @arg LL_DMA_CHANNEL_2
1990 * @arg LL_DMA_CHANNEL_3
1991 * @arg LL_DMA_CHANNEL_4
1992 * @arg LL_DMA_CHANNEL_5
1993 * @arg LL_DMA_CHANNEL_6
1994 * @arg LL_DMA_CHANNEL_7
1995 * @arg LL_DMA_CHANNEL_8
1996 * @retval None
1997 */
LL_DMA_DisableIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)1998 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
1999 {
2000 CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE);
2001 }
2002
2003 /**
2004 * @brief Check if Transfer complete Interrupt is enabled.
2005 * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
2006 * @param DMAx DMAx Instance
2007 * @param Channel This parameter can be one of the following values:
2008 * @arg LL_DMA_CHANNEL_1
2009 * @arg LL_DMA_CHANNEL_2
2010 * @arg LL_DMA_CHANNEL_3
2011 * @arg LL_DMA_CHANNEL_4
2012 * @arg LL_DMA_CHANNEL_5
2013 * @arg LL_DMA_CHANNEL_6
2014 * @arg LL_DMA_CHANNEL_7
2015 * @arg LL_DMA_CHANNEL_8
2016 * @retval State of bit (1 or 0).
2017 */
LL_DMA_IsEnabledIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)2018 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
2019 {
2020 return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
2021 DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL);
2022 }
2023
2024 /**
2025 * @brief Check if Half transfer Interrupt is enabled.
2026 * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
2027 * @param DMAx DMAx Instance
2028 * @param Channel This parameter can be one of the following values:
2029 * @arg LL_DMA_CHANNEL_1
2030 * @arg LL_DMA_CHANNEL_2
2031 * @arg LL_DMA_CHANNEL_3
2032 * @arg LL_DMA_CHANNEL_4
2033 * @arg LL_DMA_CHANNEL_5
2034 * @arg LL_DMA_CHANNEL_6
2035 * @arg LL_DMA_CHANNEL_7
2036 * @arg LL_DMA_CHANNEL_8
2037 * @retval State of bit (1 or 0).
2038 */
LL_DMA_IsEnabledIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)2039 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
2040 {
2041 return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
2042 DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL);
2043 }
2044
2045 /**
2046 * @brief Check if Transfer error Interrupt is enabled.
2047 * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
2048 * @param DMAx DMAx Instance
2049 * @param Channel This parameter can be one of the following values:
2050 * @arg LL_DMA_CHANNEL_1
2051 * @arg LL_DMA_CHANNEL_2
2052 * @arg LL_DMA_CHANNEL_3
2053 * @arg LL_DMA_CHANNEL_4
2054 * @arg LL_DMA_CHANNEL_5
2055 * @arg LL_DMA_CHANNEL_6
2056 * @arg LL_DMA_CHANNEL_7
2057 * @arg LL_DMA_CHANNEL_8
2058 * @retval State of bit (1 or 0).
2059 */
LL_DMA_IsEnabledIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)2060 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
2061 {
2062 return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
2063 DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL);
2064 }
2065
2066 /**
2067 * @}
2068 */
2069
2070 #if defined(USE_FULL_LL_DRIVER)
2071 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
2072 * @{
2073 */
2074
2075 ErrorStatus LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
2076 ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
2077 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
2078
2079 /**
2080 * @}
2081 */
2082 #endif /* USE_FULL_LL_DRIVER */
2083
2084 /**
2085 * @}
2086 */
2087
2088 /**
2089 * @}
2090 */
2091
2092 #endif /* DMA1 */
2093
2094 /**
2095 * @}
2096 */
2097
2098 #ifdef __cplusplus
2099 }
2100 #endif
2101
2102 #endif /* STM32WB0x_LL_DMA_H */
2103
