1 /**
2 ******************************************************************************
3 * @file stm32c0xx_ll_dma.h
4 * @author MCD Application Team
5 * @brief Header file of DMA LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32C0xx_LL_DMA_H
21 #define STM32C0xx_LL_DMA_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32c0xx.h"
29 #include "stm32c0xx_ll_dmamux.h"
30
31 /** @addtogroup STM32C0xx_LL_Driver
32 * @{
33 */
34
35 #if defined (DMA1)
36
37 /** @defgroup DMA_LL DMA
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
44 * @{
45 */
46 /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
47 static const uint8_t CHANNEL_OFFSET_TAB[] =
48 {
49 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
50 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
51 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
52 #if defined(DMA1_Channel4_BASE)
53 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
54 #endif /* DMA1_Channel4_BASE */
55 #if defined(DMA1_Channel5_BASE)
56 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
57 #endif /* DMA1_Channel5_BASE */
58 };
59 /**
60 * @}
61 */
62
63 /* Private constants ---------------------------------------------------------*/
64 /* Private macros ------------------------------------------------------------*/
65 /** @defgroup DMA_LL_Private_Macros DMA Private Macros
66 * @{
67 */
68 /**
69 * @}
70 */
71
72 /* Exported types ------------------------------------------------------------*/
73 #if defined(USE_FULL_LL_DRIVER)
74 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
75 * @{
76 */
77 typedef struct
78 {
79 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
80 or as Source base address in case of memory to memory transfer direction.
81
82 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF */
83
84 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
85 or as Destination base address in case of memory to memory transfer direction.
86
87 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF */
88
89 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
90 from memory to memory or from peripheral to memory.
91 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
92
93 This feature can be modified afterwards using unitary function
94 @ref LL_DMA_SetDataTransferDirection(). */
95
96 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
97 This parameter can be a value of @ref DMA_LL_EC_MODE
98 @note: The circular buffer mode cannot be used if the memory to memory
99 data transfer direction is configured on the selected Channel
100
101 This feature can be modified afterwards using unitary function
102 @ref LL_DMA_SetMode(). */
103
104 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to
105 memory transfer directionis incremented or not.
106 This parameter can be a value of @ref DMA_LL_EC_PERIPH
107
108 This feature can be modified afterwards using unitary function
109 @ref LL_DMA_SetPeriphIncMode(). */
110
111 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to
112 memory transfer direction is incremented or not.
113 This parameter can be a value of @ref DMA_LL_EC_MEMORY
114
115 This feature can be modified afterwards using unitary function
116 @ref LL_DMA_SetMemoryIncMode(). */
117
118 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment
119 (byte, half word, word)in case of memory to memory transfer direction.
120 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
121
122 This feature can be modified afterwards using unitary function
123 @ref LL_DMA_SetPeriphSize(). */
124
125 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment
126 (byte, half word, word) in case of memory to memory transfer direction.
127 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
128
129 This feature can be modified afterwards using unitary function
130 @ref LL_DMA_SetMemorySize(). */
131
132 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
133 The data unit is equal to the source buffer configuration set in PeripheralSize
134 or MemorySize parameters depending in the transfer direction.
135 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
136
137 This feature can be modified afterwards using unitary function
138 @ref LL_DMA_SetDataLength(). */
139
140 uint32_t PeriphRequest; /*!< Specifies the peripheral request.
141 This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST
142
143 This feature can be modified afterwards using unitary function
144 @ref LL_DMA_SetPeriphRequest(). */
145
146 uint32_t Priority; /*!< Specifies the channel priority level.
147 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
148
149 This feature can be modified afterwards using unitary function
150 @ref LL_DMA_SetChannelPriorityLevel(). */
151
152 } LL_DMA_InitTypeDef;
153 /**
154 * @}
155 */
156 #endif /*USE_FULL_LL_DRIVER*/
157
158 /* Exported constants --------------------------------------------------------*/
159 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
160 * @{
161 */
162 /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
163 * @brief Flags defines which can be used with LL_DMA_WriteReg function
164 * @{
165 */
166 #define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */
167 #define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
168 #define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
169 #define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
170 #define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */
171 #define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
172 #define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
173 #define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
174 #define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */
175 #define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
176 #define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
177 #define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
178 #if defined(DMA1_Channel4)
179 #define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */
180 #define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
181 #define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
182 #define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
183 #endif /* DMA1_Channel4 */
184 #if defined(DMA1_Channel5)
185 #define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */
186 #define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */
187 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */
188 #define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */
189 #endif /* DMA1_Channel5 */
190
191 /**
192 * @}
193 */
194
195 /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
196 * @brief Flags defines which can be used with LL_DMA_ReadReg function
197 * @{
198 */
199 #define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */
200 #define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
201 #define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
202 #define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
203 #define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */
204 #define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
205 #define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
206 #define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
207 #define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */
208 #define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
209 #define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
210 #define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
211 #if defined(DMA1_Channel4)
212 #define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */
213 #define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */
214 #define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
215 #define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
216 #endif /* DMA1_Channel4 */
217 #if defined(DMA1_Channel5)
218 #define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */
219 #define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */
220 #define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
221 #define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
222 #endif /* DMA1_Channel5 */
223 /**
224 * @}
225 */
226
227 /** @defgroup DMA_LL_EC_IT IT Defines
228 * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
229 * @{
230 */
231 #define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */
232 #define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */
233 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
234 /**
235 * @}
236 */
237
238 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
239 * @{
240 */
241 #define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */
242 #define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */
243 #define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */
244 #if defined(DMA1_Channel4)
245 #define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */
246 #endif /* DMA1_Channel4 */
247 #if defined(DMA1_Channel5)
248 #define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */
249 #endif /* DMA1_Channel5 */
250 #if defined(USE_FULL_LL_DRIVER)
251 #define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function
252 @ref LL_DMA_DeInit(). */
253 #endif /*USE_FULL_LL_DRIVER*/
254 /**
255 * @}
256 */
257
258 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
259 * @{
260 */
261 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
262 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
263 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
264 /**
265 * @}
266 */
267
268 /** @defgroup DMA_LL_EC_MODE Transfer mode
269 * @{
270 */
271 #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
272 #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */
273 /**
274 * @}
275 */
276
277 /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
278 * @{
279 */
280 #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */
281 #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
282 /**
283 * @}
284 */
285
286 /** @defgroup DMA_LL_EC_MEMORY Memory increment mode
287 * @{
288 */
289 #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */
290 #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
291 /**
292 * @}
293 */
294
295 /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
296 * @{
297 */
298 #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
299 #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
300 #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
301 /**
302 * @}
303 */
304
305 /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
306 * @{
307 */
308 #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
309 #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
310 #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
311 /**
312 * @}
313 */
314
315 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
316 * @{
317 */
318 #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
319 #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
320 #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
321 #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */
322 /**
323 * @}
324 */
325
326 /**
327 * @}
328 */
329
330 /* Exported macro ------------------------------------------------------------*/
331 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
332 * @{
333 */
334
335 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
336 * @{
337 */
338 /**
339 * @brief Write a value in DMA register
340 * @param __INSTANCE__ DMA Instance
341 * @param __REG__ Register to be written
342 * @param __VALUE__ Value to be written in the register
343 * @retval None
344 */
345 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
346
347 /**
348 * @brief Read a value in DMA register
349 * @param __INSTANCE__ DMA Instance
350 * @param __REG__ Register to be read
351 * @retval Register value
352 */
353 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
354 /**
355 * @}
356 */
357
358 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
359 * @{
360 */
361 /**
362 * @brief Convert DMAx_Channely into DMAx
363 * @param __CHANNEL_INSTANCE__ DMAx_Channely
364 * @retval DMAx
365 */
366 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
367
368 /**
369 * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
370 * @param __CHANNEL_INSTANCE__ DMAx_Channely
371 * @retval LL_DMA_CHANNEL_y
372 */
373 #if defined(LL_DMA_CHANNEL_5)
374 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
375 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
376 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
377 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
378 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
379 LL_DMA_CHANNEL_5)
380 #else
381 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
382 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
383 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
384 LL_DMA_CHANNEL_3)
385 #endif /* LL_DMA_CHANNEL_5 */
386
387 /**
388 * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
389 * @param __DMA_INSTANCE__ DMAx
390 * @param __CHANNEL__ LL_DMA_CHANNEL_y
391 * @retval DMAx_Channely
392 */
393 #if defined(LL_DMA_CHANNEL_5)
394 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
395 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
396 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
397 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
398 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
399 DMA1_Channel5)
400 #else
401 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
402 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
403 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
404 DMA1_Channel3)
405 #endif /* LL_DMA_CHANNEL_5 */
406
407 /**
408 * @}
409 */
410
411 /**
412 * @}
413 */
414
415 /* Exported functions --------------------------------------------------------*/
416 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
417 * @{
418 */
419
420 /** @defgroup DMA_LL_EF_Configuration Configuration
421 * @{
422 */
423 /**
424 * @brief Enable DMA channel.
425 * @rmtoll CCR EN LL_DMA_EnableChannel
426 * @param DMAx DMAx Instance
427 * @param Channel This parameter can be one of the following values:
428 * @arg @ref LL_DMA_CHANNEL_1
429 * @arg @ref LL_DMA_CHANNEL_2
430 * @arg @ref LL_DMA_CHANNEL_3
431 * @arg @ref LL_DMA_CHANNEL_4 (*)
432 * @arg @ref LL_DMA_CHANNEL_5 (*)
433 * @note (*) Availability depends on devices
434 * @retval None
435 */
LL_DMA_EnableChannel(DMA_TypeDef * DMAx,uint32_t Channel)436 __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
437 {
438 uint32_t dma_base_addr = (uint32_t)DMAx;
439 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_EN);
440 }
441
442 /**
443 * @brief Disable DMA channel.
444 * @rmtoll CCR EN LL_DMA_DisableChannel
445 * @param DMAx DMAx Instance
446 * @param Channel This parameter can be one of the following values:
447 * @arg @ref LL_DMA_CHANNEL_1
448 * @arg @ref LL_DMA_CHANNEL_2
449 * @arg @ref LL_DMA_CHANNEL_3
450 * @arg @ref LL_DMA_CHANNEL_4 (*)
451 * @arg @ref LL_DMA_CHANNEL_5 (*)
452 * @note (*) Availability depends on devices
453 * @retval None
454 */
LL_DMA_DisableChannel(DMA_TypeDef * DMAx,uint32_t Channel)455 __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
456 {
457 uint32_t dma_base_addr = (uint32_t)DMAx;
458 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_EN);
459 }
460
461 /**
462 * @brief Check if DMA channel is enabled or disabled.
463 * @rmtoll CCR EN LL_DMA_IsEnabledChannel
464 * @param DMAx DMAx Instance
465 * @param Channel This parameter can be one of the following values:
466 * @arg @ref LL_DMA_CHANNEL_1
467 * @arg @ref LL_DMA_CHANNEL_2
468 * @arg @ref LL_DMA_CHANNEL_3
469 * @arg @ref LL_DMA_CHANNEL_4 (*)
470 * @arg @ref LL_DMA_CHANNEL_5 (*)
471 * @note (*) Availability depends on devices
472 * @retval State of bit (1 or 0).
473 */
LL_DMA_IsEnabledChannel(DMA_TypeDef * DMAx,uint32_t Channel)474 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
475 {
476 uint32_t dma_base_addr = (uint32_t)DMAx;
477 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR,
478 DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL);
479 }
480
481 /**
482 * @brief Configure all parameters link to DMA transfer.
483 * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
484 * CCR MEM2MEM LL_DMA_ConfigTransfer\n
485 * CCR CIRC LL_DMA_ConfigTransfer\n
486 * CCR PINC LL_DMA_ConfigTransfer\n
487 * CCR MINC LL_DMA_ConfigTransfer\n
488 * CCR PSIZE LL_DMA_ConfigTransfer\n
489 * CCR MSIZE LL_DMA_ConfigTransfer\n
490 * CCR PL LL_DMA_ConfigTransfer
491 * @param DMAx DMAx Instance
492 * @param Channel This parameter can be one of the following values:
493 * @arg @ref LL_DMA_CHANNEL_1
494 * @arg @ref LL_DMA_CHANNEL_2
495 * @arg @ref LL_DMA_CHANNEL_3
496 * @arg @ref LL_DMA_CHANNEL_4 (*)
497 * @arg @ref LL_DMA_CHANNEL_5 (*)
498 * @note (*) Availability depends on devices
499 * @param Configuration This parameter must be a combination of all the following values:
500 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or
501 * @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
502 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
503 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
504 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
505 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
506 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
507 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or
508 * @ref LL_DMA_PRIORITY_VERYHIGH
509 * @retval None
510 */
LL_DMA_ConfigTransfer(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)511 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
512 {
513 uint32_t dma_base_addr = (uint32_t)DMAx;
514 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR,
515 DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | \
516 DMA_CCR_MSIZE | DMA_CCR_PL, Configuration);
517 }
518
519 /**
520 * @brief Set Data transfer direction (read from peripheral or from memory).
521 * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
522 * CCR MEM2MEM LL_DMA_SetDataTransferDirection
523 * @param DMAx DMAx Instance
524 * @param Channel This parameter can be one of the following values:
525 * @arg @ref LL_DMA_CHANNEL_1
526 * @arg @ref LL_DMA_CHANNEL_2
527 * @arg @ref LL_DMA_CHANNEL_3
528 * @arg @ref LL_DMA_CHANNEL_4 (*)
529 * @arg @ref LL_DMA_CHANNEL_5 (*)
530 * @note (*) Availability depends on devices
531 * @param Direction This parameter can be one of the following values:
532 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
533 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
534 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
535 * @retval None
536 */
LL_DMA_SetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Direction)537 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
538 {
539 uint32_t dma_base_addr = (uint32_t)DMAx;
540 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR,
541 DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
542 }
543
544 /**
545 * @brief Get Data transfer direction (read from peripheral or from memory).
546 * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
547 * CCR MEM2MEM LL_DMA_GetDataTransferDirection
548 * @param DMAx DMAx Instance
549 * @param Channel This parameter can be one of the following values:
550 * @arg @ref LL_DMA_CHANNEL_1
551 * @arg @ref LL_DMA_CHANNEL_2
552 * @arg @ref LL_DMA_CHANNEL_3
553 * @arg @ref LL_DMA_CHANNEL_4 (*)
554 * @arg @ref LL_DMA_CHANNEL_5 (*)
555 * @note (*) Availability depends on devices
556 * @retval Returned value can be one of the following values:
557 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
558 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
559 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
560 */
LL_DMA_GetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Channel)561 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
562 {
563 uint32_t dma_base_addr = (uint32_t)DMAx;
564 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR,
565 DMA_CCR_DIR | DMA_CCR_MEM2MEM));
566 }
567
568 /**
569 * @brief Set DMA mode circular or normal.
570 * @note The circular buffer mode cannot be used if the memory-to-memory
571 * data transfer is configured on the selected Channel.
572 * @rmtoll CCR CIRC LL_DMA_SetMode
573 * @param DMAx DMAx Instance
574 * @param Channel This parameter can be one of the following values:
575 * @arg @ref LL_DMA_CHANNEL_1
576 * @arg @ref LL_DMA_CHANNEL_2
577 * @arg @ref LL_DMA_CHANNEL_3
578 * @arg @ref LL_DMA_CHANNEL_4 (*)
579 * @arg @ref LL_DMA_CHANNEL_5 (*)
580 * @note (*) Availability depends on devices
581 * @param Mode This parameter can be one of the following values:
582 * @arg @ref LL_DMA_MODE_NORMAL
583 * @arg @ref LL_DMA_MODE_CIRCULAR
584 * @retval None
585 */
LL_DMA_SetMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Mode)586 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
587 {
588 uint32_t dma_base_addr = (uint32_t)DMAx;
589 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_CIRC,
590 Mode);
591 }
592
593 /**
594 * @brief Get DMA mode circular or normal.
595 * @rmtoll CCR CIRC LL_DMA_GetMode
596 * @param DMAx DMAx Instance
597 * @param Channel This parameter can be one of the following values:
598 * @arg @ref LL_DMA_CHANNEL_1
599 * @arg @ref LL_DMA_CHANNEL_2
600 * @arg @ref LL_DMA_CHANNEL_3
601 * @arg @ref LL_DMA_CHANNEL_4 (*)
602 * @arg @ref LL_DMA_CHANNEL_5 (*)
603 * @note (*) Availability depends on devices
604 * @retval Returned value can be one of the following values:
605 * @arg @ref LL_DMA_MODE_NORMAL
606 * @arg @ref LL_DMA_MODE_CIRCULAR
607 */
LL_DMA_GetMode(DMA_TypeDef * DMAx,uint32_t Channel)608 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
609 {
610 uint32_t dma_base_addr = (uint32_t)DMAx;
611 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR,
612 DMA_CCR_CIRC));
613 }
614
615 /**
616 * @brief Set Peripheral increment mode.
617 * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
618 * @param DMAx DMAx Instance
619 * @param Channel This parameter can be one of the following values:
620 * @arg @ref LL_DMA_CHANNEL_1
621 * @arg @ref LL_DMA_CHANNEL_2
622 * @arg @ref LL_DMA_CHANNEL_3
623 * @arg @ref LL_DMA_CHANNEL_4 (*)
624 * @arg @ref LL_DMA_CHANNEL_5 (*)
625 * @note (*) Availability depends on devices
626 * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
627 * @arg @ref LL_DMA_PERIPH_INCREMENT
628 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
629 * @retval None
630 */
LL_DMA_SetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphOrM2MSrcIncMode)631 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
632 {
633 uint32_t dma_base_addr = (uint32_t)DMAx;
634 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_PINC,
635 PeriphOrM2MSrcIncMode);
636 }
637
638 /**
639 * @brief Get Peripheral increment mode.
640 * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
641 * @param DMAx DMAx Instance
642 * @param Channel This parameter can be one of the following values:
643 * @arg @ref LL_DMA_CHANNEL_1
644 * @arg @ref LL_DMA_CHANNEL_2
645 * @arg @ref LL_DMA_CHANNEL_3
646 * @arg @ref LL_DMA_CHANNEL_4 (*)
647 * @arg @ref LL_DMA_CHANNEL_5 (*)
648 * @note (*) Availability depends on devices
649 * @retval Returned value can be one of the following values:
650 * @arg @ref LL_DMA_PERIPH_INCREMENT
651 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
652 */
LL_DMA_GetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Channel)653 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
654 {
655 uint32_t dma_base_addr = (uint32_t)DMAx;
656 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR,
657 DMA_CCR_PINC));
658 }
659
660 /**
661 * @brief Set Memory increment mode.
662 * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
663 * @param DMAx DMAx Instance
664 * @param Channel This parameter can be one of the following values:
665 * @arg @ref LL_DMA_CHANNEL_1
666 * @arg @ref LL_DMA_CHANNEL_2
667 * @arg @ref LL_DMA_CHANNEL_3
668 * @arg @ref LL_DMA_CHANNEL_4 (*)
669 * @arg @ref LL_DMA_CHANNEL_5 (*)
670 * @note (*) Availability depends on devices
671 * @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
672 * @arg @ref LL_DMA_MEMORY_INCREMENT
673 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
674 * @retval None
675 */
LL_DMA_SetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryOrM2MDstIncMode)676 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
677 {
678 uint32_t dma_base_addr = (uint32_t)DMAx;
679 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_MINC,
680 MemoryOrM2MDstIncMode);
681 }
682
683 /**
684 * @brief Get Memory increment mode.
685 * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
686 * @param DMAx DMAx Instance
687 * @param Channel This parameter can be one of the following values:
688 * @arg @ref LL_DMA_CHANNEL_1
689 * @arg @ref LL_DMA_CHANNEL_2
690 * @arg @ref LL_DMA_CHANNEL_3
691 * @arg @ref LL_DMA_CHANNEL_4 (*)
692 * @arg @ref LL_DMA_CHANNEL_5 (*)
693 * @note (*) Availability depends on devices
694 * @retval Returned value can be one of the following values:
695 * @arg @ref LL_DMA_MEMORY_INCREMENT
696 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
697 */
LL_DMA_GetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Channel)698 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
699 {
700 uint32_t dma_base_addr = (uint32_t)DMAx;
701 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR,
702 DMA_CCR_MINC));
703 }
704
705 /**
706 * @brief Set Peripheral size.
707 * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
708 * @param DMAx DMAx Instance
709 * @param Channel This parameter can be one of the following values:
710 * @arg @ref LL_DMA_CHANNEL_1
711 * @arg @ref LL_DMA_CHANNEL_2
712 * @arg @ref LL_DMA_CHANNEL_3
713 * @arg @ref LL_DMA_CHANNEL_4 (*)
714 * @arg @ref LL_DMA_CHANNEL_5 (*)
715 * @note (*) Availability depends on devices
716 * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
717 * @arg @ref LL_DMA_PDATAALIGN_BYTE
718 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
719 * @arg @ref LL_DMA_PDATAALIGN_WORD
720 * @retval None
721 */
LL_DMA_SetPeriphSize(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphOrM2MSrcDataSize)722 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
723 {
724 uint32_t dma_base_addr = (uint32_t)DMAx;
725 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_PSIZE,
726 PeriphOrM2MSrcDataSize);
727 }
728
729 /**
730 * @brief Get Peripheral size.
731 * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
732 * @param DMAx DMAx Instance
733 * @param Channel This parameter can be one of the following values:
734 * @arg @ref LL_DMA_CHANNEL_1
735 * @arg @ref LL_DMA_CHANNEL_2
736 * @arg @ref LL_DMA_CHANNEL_3
737 * @arg @ref LL_DMA_CHANNEL_4 (*)
738 * @arg @ref LL_DMA_CHANNEL_5 (*)
739 * @note (*) Availability depends on devices
740 * @retval Returned value can be one of the following values:
741 * @arg @ref LL_DMA_PDATAALIGN_BYTE
742 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
743 * @arg @ref LL_DMA_PDATAALIGN_WORD
744 */
LL_DMA_GetPeriphSize(DMA_TypeDef * DMAx,uint32_t Channel)745 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
746 {
747 uint32_t dma_base_addr = (uint32_t)DMAx;
748 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR,
749 DMA_CCR_PSIZE));
750 }
751
752 /**
753 * @brief Set Memory size.
754 * @rmtoll CCR MSIZE LL_DMA_SetMemorySize
755 * @param DMAx DMAx Instance
756 * @param Channel This parameter can be one of the following values:
757 * @arg @ref LL_DMA_CHANNEL_1
758 * @arg @ref LL_DMA_CHANNEL_2
759 * @arg @ref LL_DMA_CHANNEL_3
760 * @arg @ref LL_DMA_CHANNEL_4 (*)
761 * @arg @ref LL_DMA_CHANNEL_5 (*)
762 * @note (*) Availability depends on devices
763 * @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
764 * @arg @ref LL_DMA_MDATAALIGN_BYTE
765 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
766 * @arg @ref LL_DMA_MDATAALIGN_WORD
767 * @retval None
768 */
LL_DMA_SetMemorySize(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryOrM2MDstDataSize)769 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
770 {
771 uint32_t dma_base_addr = (uint32_t)DMAx;
772 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_MSIZE,
773 MemoryOrM2MDstDataSize);
774 }
775
776 /**
777 * @brief Get Memory size.
778 * @rmtoll CCR MSIZE LL_DMA_GetMemorySize
779 * @param DMAx DMAx Instance
780 * @param Channel This parameter can be one of the following values:
781 * @arg @ref LL_DMA_CHANNEL_1
782 * @arg @ref LL_DMA_CHANNEL_2
783 * @arg @ref LL_DMA_CHANNEL_3
784 * @arg @ref LL_DMA_CHANNEL_4 (*)
785 * @arg @ref LL_DMA_CHANNEL_5 (*)
786 * @note (*) Availability depends on devices
787 * @retval Returned value can be one of the following values:
788 * @arg @ref LL_DMA_MDATAALIGN_BYTE
789 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
790 * @arg @ref LL_DMA_MDATAALIGN_WORD
791 */
LL_DMA_GetMemorySize(DMA_TypeDef * DMAx,uint32_t Channel)792 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
793 {
794 uint32_t dma_base_addr = (uint32_t)DMAx;
795 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR,
796 DMA_CCR_MSIZE));
797 }
798
799 /**
800 * @brief Set Channel priority level.
801 * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
802 * @param DMAx DMAx Instance
803 * @param Channel This parameter can be one of the following values:
804 * @arg @ref LL_DMA_CHANNEL_1
805 * @arg @ref LL_DMA_CHANNEL_2
806 * @arg @ref LL_DMA_CHANNEL_3
807 * @arg @ref LL_DMA_CHANNEL_4 (*)
808 * @arg @ref LL_DMA_CHANNEL_5 (*)
809 * @note (*) Availability depends on devices
810 * @param Priority This parameter can be one of the following values:
811 * @arg @ref LL_DMA_PRIORITY_LOW
812 * @arg @ref LL_DMA_PRIORITY_MEDIUM
813 * @arg @ref LL_DMA_PRIORITY_HIGH
814 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
815 * @retval None
816 */
LL_DMA_SetChannelPriorityLevel(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Priority)817 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
818 {
819 uint32_t dma_base_addr = (uint32_t)DMAx;
820 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_PL,
821 Priority);
822 }
823
824 /**
825 * @brief Get Channel priority level.
826 * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
827 * @param DMAx DMAx Instance
828 * @param Channel This parameter can be one of the following values:
829 * @arg @ref LL_DMA_CHANNEL_1
830 * @arg @ref LL_DMA_CHANNEL_2
831 * @arg @ref LL_DMA_CHANNEL_3
832 * @arg @ref LL_DMA_CHANNEL_4 (*)
833 * @arg @ref LL_DMA_CHANNEL_5 (*)
834 * @note (*) Availability depends on devices
835 * @retval Returned value can be one of the following values:
836 * @arg @ref LL_DMA_PRIORITY_LOW
837 * @arg @ref LL_DMA_PRIORITY_MEDIUM
838 * @arg @ref LL_DMA_PRIORITY_HIGH
839 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
840 */
LL_DMA_GetChannelPriorityLevel(DMA_TypeDef * DMAx,uint32_t Channel)841 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
842 {
843 uint32_t dma_base_addr = (uint32_t)DMAx;
844 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR,
845 DMA_CCR_PL));
846 }
847
848 /**
849 * @brief Set Number of data to transfer.
850 * @note This action has no effect if
851 * channel is enabled.
852 * @rmtoll CNDTR NDT LL_DMA_SetDataLength
853 * @param DMAx DMAx Instance
854 * @param Channel This parameter can be one of the following values:
855 * @arg @ref LL_DMA_CHANNEL_1
856 * @arg @ref LL_DMA_CHANNEL_2
857 * @arg @ref LL_DMA_CHANNEL_3
858 * @arg @ref LL_DMA_CHANNEL_4 (*)
859 * @arg @ref LL_DMA_CHANNEL_5 (*)
860 * @note (*) Availability depends on devices
861 * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
862 * @retval None
863 */
LL_DMA_SetDataLength(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t NbData)864 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
865 {
866 uint32_t dma_base_addr = (uint32_t)DMAx;
867 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CNDTR,
868 DMA_CNDTR_NDT, NbData);
869 }
870
871 /**
872 * @brief Get Number of data to transfer.
873 * @note Once the channel is enabled, the return value indicate the
874 * remaining bytes to be transmitted.
875 * @rmtoll CNDTR NDT LL_DMA_GetDataLength
876 * @param DMAx DMAx Instance
877 * @param Channel This parameter can be one of the following values:
878 * @arg @ref LL_DMA_CHANNEL_1
879 * @arg @ref LL_DMA_CHANNEL_2
880 * @arg @ref LL_DMA_CHANNEL_3
881 * @arg @ref LL_DMA_CHANNEL_4 (*)
882 * @arg @ref LL_DMA_CHANNEL_5 (*)
883 * @note (*) Availability depends on devices
884 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
885 */
LL_DMA_GetDataLength(DMA_TypeDef * DMAx,uint32_t Channel)886 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
887 {
888 uint32_t dma_base_addr = (uint32_t)DMAx;
889 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CNDTR,
890 DMA_CNDTR_NDT));
891 }
892
893 /**
894 * @brief Configure the Source and Destination addresses.
895 * @note This API must not be called when the DMA channel is enabled.
896 * @note Each peripheral using DMA provides an API to get directly the register address (LL_PPP_DMA_GetRegAddr).
897 * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
898 * CMAR MA LL_DMA_ConfigAddresses
899 * @param DMAx DMAx Instance
900 * @param Channel This parameter can be one of the following values:
901 * @arg @ref LL_DMA_CHANNEL_1
902 * @arg @ref LL_DMA_CHANNEL_2
903 * @arg @ref LL_DMA_CHANNEL_3
904 * @arg @ref LL_DMA_CHANNEL_4 (*)
905 * @arg @ref LL_DMA_CHANNEL_5 (*)
906 * @note (*) Availability depends on devices
907 * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
908 * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
909 * @param Direction This parameter can be one of the following values:
910 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
911 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
912 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
913 * @retval None
914 */
LL_DMA_ConfigAddresses(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddress,uint32_t DstAddress,uint32_t Direction)915 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
916 uint32_t DstAddress, uint32_t Direction)
917 {
918 uint32_t dma_base_addr = (uint32_t)DMAx;
919 /* Direction Memory to Periph */
920 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
921 {
922 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CMAR, SrcAddress);
923 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CPAR, DstAddress);
924 }
925 /* Direction Periph to Memory and Memory to Memory */
926 else
927 {
928 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CPAR, SrcAddress);
929 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CMAR, DstAddress);
930 }
931 }
932
933 /**
934 * @brief Set the Memory address.
935 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
936 * @note This API must not be called when the DMA channel is enabled.
937 * @rmtoll CMAR MA LL_DMA_SetMemoryAddress
938 * @param DMAx DMAx Instance
939 * @param Channel This parameter can be one of the following values:
940 * @arg @ref LL_DMA_CHANNEL_1
941 * @arg @ref LL_DMA_CHANNEL_2
942 * @arg @ref LL_DMA_CHANNEL_3
943 * @arg @ref LL_DMA_CHANNEL_4 (*)
944 * @arg @ref LL_DMA_CHANNEL_5 (*)
945 * @note (*) Availability depends on devices
946 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
947 * @retval None
948 */
LL_DMA_SetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)949 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
950 {
951 uint32_t dma_base_addr = (uint32_t)DMAx;
952 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CMAR, MemoryAddress);
953 }
954
955 /**
956 * @brief Set the Peripheral address.
957 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
958 * @note This API must not be called when the DMA channel is enabled.
959 * @rmtoll CPAR PA LL_DMA_SetPeriphAddress
960 * @param DMAx DMAx Instance
961 * @param Channel This parameter can be one of the following values:
962 * @arg @ref LL_DMA_CHANNEL_1
963 * @arg @ref LL_DMA_CHANNEL_2
964 * @arg @ref LL_DMA_CHANNEL_3
965 * @arg @ref LL_DMA_CHANNEL_4 (*)
966 * @arg @ref LL_DMA_CHANNEL_5 (*)
967 * @note (*) Availability depends on devices
968 * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
969 * @retval None
970 */
LL_DMA_SetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphAddress)971 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
972 {
973 uint32_t dma_base_addr = (uint32_t)DMAx;
974 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CPAR, PeriphAddress);
975 }
976
977 /**
978 * @brief Get Memory address.
979 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
980 * @rmtoll CMAR MA LL_DMA_GetMemoryAddress
981 * @param DMAx DMAx Instance
982 * @param Channel This parameter can be one of the following values:
983 * @arg @ref LL_DMA_CHANNEL_1
984 * @arg @ref LL_DMA_CHANNEL_2
985 * @arg @ref LL_DMA_CHANNEL_3
986 * @arg @ref LL_DMA_CHANNEL_4 (*)
987 * @arg @ref LL_DMA_CHANNEL_5 (*)
988 * @note (*) Availability depends on devices
989 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
990 */
LL_DMA_GetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Channel)991 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
992 {
993 uint32_t dma_base_addr = (uint32_t)DMAx;
994 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CMAR));
995 }
996
997 /**
998 * @brief Get Peripheral address.
999 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1000 * @rmtoll CPAR PA LL_DMA_GetPeriphAddress
1001 * @param DMAx DMAx Instance
1002 * @param Channel This parameter can be one of the following values:
1003 * @arg @ref LL_DMA_CHANNEL_1
1004 * @arg @ref LL_DMA_CHANNEL_2
1005 * @arg @ref LL_DMA_CHANNEL_3
1006 * @arg @ref LL_DMA_CHANNEL_4 (*)
1007 * @arg @ref LL_DMA_CHANNEL_5 (*)
1008 * @note (*) Availability depends on devices
1009 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1010 */
LL_DMA_GetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Channel)1011 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1012 {
1013 uint32_t dma_base_addr = (uint32_t)DMAx;
1014 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CPAR));
1015 }
1016
1017 /**
1018 * @brief Set the Memory to Memory Source address.
1019 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1020 * @note This API must not be called when the DMA channel is enabled.
1021 * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
1022 * @param DMAx DMAx Instance
1023 * @param Channel This parameter can be one of the following values:
1024 * @arg @ref LL_DMA_CHANNEL_1
1025 * @arg @ref LL_DMA_CHANNEL_2
1026 * @arg @ref LL_DMA_CHANNEL_3
1027 * @arg @ref LL_DMA_CHANNEL_4 (*)
1028 * @arg @ref LL_DMA_CHANNEL_5 (*)
1029 * @note (*) Availability depends on devices
1030 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1031 * @retval None
1032 */
LL_DMA_SetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1033 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1034 {
1035 uint32_t dma_base_addr = (uint32_t)DMAx;
1036 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CPAR, MemoryAddress);
1037 }
1038
1039 /**
1040 * @brief Set the Memory to Memory Destination address.
1041 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1042 * @note This API must not be called when the DMA channel is enabled.
1043 * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
1044 * @param DMAx DMAx Instance
1045 * @param Channel This parameter can be one of the following values:
1046 * @arg @ref LL_DMA_CHANNEL_1
1047 * @arg @ref LL_DMA_CHANNEL_2
1048 * @arg @ref LL_DMA_CHANNEL_3
1049 * @arg @ref LL_DMA_CHANNEL_4 (*)
1050 * @arg @ref LL_DMA_CHANNEL_5 (*)
1051 * @note (*) Availability depends on devices
1052 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1053 * @retval None
1054 */
LL_DMA_SetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1055 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1056 {
1057 uint32_t dma_base_addr = (uint32_t)DMAx;
1058 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CMAR, MemoryAddress);
1059 }
1060
1061 /**
1062 * @brief Get the Memory to Memory Source address.
1063 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1064 * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
1065 * @param DMAx DMAx Instance
1066 * @param Channel This parameter can be one of the following values:
1067 * @arg @ref LL_DMA_CHANNEL_1
1068 * @arg @ref LL_DMA_CHANNEL_2
1069 * @arg @ref LL_DMA_CHANNEL_3
1070 * @arg @ref LL_DMA_CHANNEL_4 (*)
1071 * @arg @ref LL_DMA_CHANNEL_5 (*)
1072 * @note (*) Availability depends on devices
1073 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1074 */
LL_DMA_GetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Channel)1075 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1076 {
1077 uint32_t dma_base_addr = (uint32_t)DMAx;
1078 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CPAR));
1079 }
1080
1081 /**
1082 * @brief Get the Memory to Memory Destination address.
1083 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1084 * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
1085 * @param DMAx DMAx Instance
1086 * @param Channel This parameter can be one of the following values:
1087 * @arg @ref LL_DMA_CHANNEL_1
1088 * @arg @ref LL_DMA_CHANNEL_2
1089 * @arg @ref LL_DMA_CHANNEL_3
1090 * @arg @ref LL_DMA_CHANNEL_4 (*)
1091 * @arg @ref LL_DMA_CHANNEL_5 (*)
1092 * @note (*) Availability depends on devices
1093 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1094 */
LL_DMA_GetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Channel)1095 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1096 {
1097 uint32_t dma_base_addr = (uint32_t)DMAx;
1098 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CMAR));
1099 }
1100
1101 /**
1102 * @brief Set DMA request for DMA Channels on DMAMUX Channel x.
1103 * @note DMAMUX channel 0 to 4 are mapped to DMA1 channel 1 to 5.
1104 * @rmtoll CxCR DMAREQ_ID LL_DMA_SetPeriphRequest
1105 * @param DMAx DMAx Instance
1106 * @param Channel This parameter can be one of the following values:
1107 * @arg @ref LL_DMA_CHANNEL_1
1108 * @arg @ref LL_DMA_CHANNEL_2
1109 * @arg @ref LL_DMA_CHANNEL_3
1110 * @arg @ref LL_DMA_CHANNEL_4 (*)
1111 * @arg @ref LL_DMA_CHANNEL_5 (*)
1112 * @param Request This parameter can be one of the following values:
1113 * @arg @ref LL_DMAMUX_REQ_MEM2MEM
1114 * @arg @ref LL_DMAMUX_REQ_GENERATOR0
1115 * @arg @ref LL_DMAMUX_REQ_GENERATOR1
1116 * @arg @ref LL_DMAMUX_REQ_GENERATOR2
1117 * @arg @ref LL_DMAMUX_REQ_GENERATOR3
1118 * @arg @ref LL_DMAMUX_REQ_ADC1
1119 * @arg @ref LL_DMAMUX_REQ_I2C1_RX
1120 * @arg @ref LL_DMAMUX_REQ_I2C1_TX
1121 * @arg @ref LL_DMAMUX_REQ_I2C2_RX (*)
1122 * @arg @ref LL_DMAMUX_REQ_I2C2_TX (*)
1123 * @arg @ref LL_DMAMUX_REQ_SPI1_RX
1124 * @arg @ref LL_DMAMUX_REQ_SPI1_TX
1125 * @arg @ref LL_DMAMUX_REQ_SPI2_RX (*)
1126 * @arg @ref LL_DMAMUX_REQ_SPI2_TX (*)
1127 * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
1128 * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
1129 * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
1130 * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
1131 * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG_COM
1132 * @arg @ref LL_DMAMUX_REQ_TIM1_UP
1133 * @arg @ref LL_DMAMUX_REQ_TIM2_CH1 (*)
1134 * @arg @ref LL_DMAMUX_REQ_TIM2_CH2 (*)
1135 * @arg @ref LL_DMAMUX_REQ_TIM2_CH3 (*)
1136 * @arg @ref LL_DMAMUX_REQ_TIM2_CH4 (*)
1137 * @arg @ref LL_DMAMUX_REQ_TIM2_TRIG_COM (*)
1138 * @arg @ref LL_DMAMUX_REQ_TIM2_UP (*)
1139 * @arg @ref LL_DMAMUX_REQ_TIM3_CH1
1140 * @arg @ref LL_DMAMUX_REQ_TIM3_CH2
1141 * @arg @ref LL_DMAMUX_REQ_TIM3_CH3
1142 * @arg @ref LL_DMAMUX_REQ_TIM3_CH4
1143 * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
1144 * @arg @ref LL_DMAMUX_REQ_TIM3_UP
1145 * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
1146 * @arg @ref LL_DMAMUX_REQ_TIM16_TRIG_COM
1147 * @arg @ref LL_DMAMUX_REQ_TIM16_UP
1148 * @arg @ref LL_DMAMUX_REQ_TIM17_CH1
1149 * @arg @ref LL_DMAMUX_REQ_TIM17_TRIG_COM
1150 * @arg @ref LL_DMAMUX_REQ_TIM17_UP
1151 * @arg @ref LL_DMAMUX_REQ_USART1_RX
1152 * @arg @ref LL_DMAMUX_REQ_USART1_TX
1153 * @arg @ref LL_DMAMUX_REQ_USART2_RX
1154 * @arg @ref LL_DMAMUX_REQ_USART2_TX
1155 * @note (*) Availability depends on devices
1156 * @retval None
1157 */
LL_DMA_SetPeriphRequest(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Request)1158 __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request)
1159 {
1160 (void)(DMAx);
1161 MODIFY_REG(((DMAMUX_Channel_TypeDef *)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Channel - 1UL))))->CCR,
1162 DMAMUX_CxCR_DMAREQ_ID, Request);
1163 }
1164
1165 /**
1166 * @brief Get DMA request for DMA Channels on DMAMUX Channel x.
1167 * @note DMAMUX channel 0 to 4 are mapped to DMA1 channel 1 to 5.
1168 * @rmtoll CxCR DMAREQ_ID LL_DMA_GetPeriphRequest
1169 * @param DMAx DMAx Instance
1170 * @param Channel This parameter can be one of the following values:
1171 * @arg @ref LL_DMA_CHANNEL_1
1172 * @arg @ref LL_DMA_CHANNEL_2
1173 * @arg @ref LL_DMA_CHANNEL_3
1174 * @arg @ref LL_DMA_CHANNEL_4 (*)
1175 * @arg @ref LL_DMA_CHANNEL_5 (*)
1176 * @retval Returned value can be one of the following values:
1177 * @arg @ref LL_DMAMUX_REQ_MEM2MEM
1178 * @arg @ref LL_DMAMUX_REQ_GENERATOR0
1179 * @arg @ref LL_DMAMUX_REQ_GENERATOR1
1180 * @arg @ref LL_DMAMUX_REQ_GENERATOR2
1181 * @arg @ref LL_DMAMUX_REQ_GENERATOR3
1182 * @arg @ref LL_DMAMUX_REQ_ADC1
1183 * @arg @ref LL_DMAMUX_REQ_I2C1_RX
1184 * @arg @ref LL_DMAMUX_REQ_I2C1_TX
1185 * @arg @ref LL_DMAMUX_REQ_I2C2_RX (*)
1186 * @arg @ref LL_DMAMUX_REQ_I2C2_TX (*)
1187 * @arg @ref LL_DMAMUX_REQ_SPI1_RX
1188 * @arg @ref LL_DMAMUX_REQ_SPI1_TX
1189 * @arg @ref LL_DMAMUX_REQ_SPI2_RX (*)
1190 * @arg @ref LL_DMAMUX_REQ_SPI2_TX (*)
1191 * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
1192 * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
1193 * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
1194 * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
1195 * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG_COM
1196 * @arg @ref LL_DMAMUX_REQ_TIM1_UP
1197 * @arg @ref LL_DMAMUX_REQ_TIM2_CH1 (*)
1198 * @arg @ref LL_DMAMUX_REQ_TIM2_CH2 (*)
1199 * @arg @ref LL_DMAMUX_REQ_TIM2_CH3 (*)
1200 * @arg @ref LL_DMAMUX_REQ_TIM2_CH4 (*)
1201 * @arg @ref LL_DMAMUX_REQ_TIM2_TRIG_COM (*)
1202 * @arg @ref LL_DMAMUX_REQ_TIM2_UP (*)
1203 * @arg @ref LL_DMAMUX_REQ_TIM3_CH1
1204 * @arg @ref LL_DMAMUX_REQ_TIM3_CH2
1205 * @arg @ref LL_DMAMUX_REQ_TIM3_CH3
1206 * @arg @ref LL_DMAMUX_REQ_TIM3_CH4
1207 * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
1208 * @arg @ref LL_DMAMUX_REQ_TIM3_UP
1209 * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
1210 * @arg @ref LL_DMAMUX_REQ_TIM16_TRIG_COM
1211 * @arg @ref LL_DMAMUX_REQ_TIM16_UP
1212 * @arg @ref LL_DMAMUX_REQ_TIM17_CH1
1213 * @arg @ref LL_DMAMUX_REQ_TIM17_TRIG_COM
1214 * @arg @ref LL_DMAMUX_REQ_TIM17_UP
1215 * @arg @ref LL_DMAMUX_REQ_USART1_RX
1216 * @arg @ref LL_DMAMUX_REQ_USART1_TX
1217 * @arg @ref LL_DMAMUX_REQ_USART2_RX
1218 * @arg @ref LL_DMAMUX_REQ_USART2_TX
1219 * @note (*) Availability depends on devices
1220 */
LL_DMA_GetPeriphRequest(DMA_TypeDef * DMAx,uint32_t Channel)1221 __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
1222 {
1223 (void)(DMAx);
1224 return (READ_BIT(((DMAMUX_Channel_TypeDef *)(((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * \
1225 (Channel - 1UL)))))->CCR,
1226 DMAMUX_CxCR_DMAREQ_ID));
1227 }
1228
1229 /**
1230 * @}
1231 */
1232
1233 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
1234 * @{
1235 */
1236
1237 /**
1238 * @brief Get Channel 1 global interrupt flag.
1239 * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
1240 * @param DMAx DMAx Instance
1241 * @retval State of bit (1 or 0).
1242 */
LL_DMA_IsActiveFlag_GI1(DMA_TypeDef * DMAx)1243 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
1244 {
1245 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)) ? 1UL : 0UL);
1246 }
1247
1248 /**
1249 * @brief Get Channel 2 global interrupt flag.
1250 * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
1251 * @param DMAx DMAx Instance
1252 * @retval State of bit (1 or 0).
1253 */
LL_DMA_IsActiveFlag_GI2(DMA_TypeDef * DMAx)1254 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
1255 {
1256 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)) ? 1UL : 0UL);
1257 }
1258
1259 /**
1260 * @brief Get Channel 3 global interrupt flag.
1261 * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
1262 * @param DMAx DMAx Instance
1263 * @retval State of bit (1 or 0).
1264 */
LL_DMA_IsActiveFlag_GI3(DMA_TypeDef * DMAx)1265 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
1266 {
1267 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)) ? 1UL : 0UL);
1268 }
1269
1270 #if defined(DMA_ISR_GIF4)
1271 /**
1272 * @brief Get Channel 4 global interrupt flag.
1273 * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
1274 * @param DMAx DMAx Instance
1275 * @retval State of bit (1 or 0).
1276 */
LL_DMA_IsActiveFlag_GI4(DMA_TypeDef * DMAx)1277 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
1278 {
1279 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)) ? 1UL : 0UL);
1280 }
1281 #endif /* DMA_ISR_GIF4 */
1282
1283 #if defined(DMA_ISR_GIF5)
1284 /**
1285 * @brief Get Channel 5 global interrupt flag.
1286 * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
1287 * @param DMAx DMAx Instance
1288 * @retval State of bit (1 or 0).
1289 */
LL_DMA_IsActiveFlag_GI5(DMA_TypeDef * DMAx)1290 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
1291 {
1292 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)) ? 1UL : 0UL);
1293 }
1294 #endif /* DMA_ISR_GIF5 */
1295
1296 /**
1297 * @brief Get Channel 1 transfer complete flag.
1298 * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
1299 * @param DMAx DMAx Instance
1300 * @retval State of bit (1 or 0).
1301 */
LL_DMA_IsActiveFlag_TC1(DMA_TypeDef * DMAx)1302 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
1303 {
1304 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)) ? 1UL : 0UL);
1305 }
1306
1307 /**
1308 * @brief Get Channel 2 transfer complete flag.
1309 * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
1310 * @param DMAx DMAx Instance
1311 * @retval State of bit (1 or 0).
1312 */
LL_DMA_IsActiveFlag_TC2(DMA_TypeDef * DMAx)1313 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
1314 {
1315 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)) ? 1UL : 0UL);
1316 }
1317
1318 /**
1319 * @brief Get Channel 3 transfer complete flag.
1320 * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
1321 * @param DMAx DMAx Instance
1322 * @retval State of bit (1 or 0).
1323 */
LL_DMA_IsActiveFlag_TC3(DMA_TypeDef * DMAx)1324 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
1325 {
1326 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)) ? 1UL : 0UL);
1327 }
1328
1329 #if defined(DMA_ISR_TCIF4)
1330 /**
1331 * @brief Get Channel 4 transfer complete flag.
1332 * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
1333 * @param DMAx DMAx Instance
1334 * @retval State of bit (1 or 0).
1335 */
LL_DMA_IsActiveFlag_TC4(DMA_TypeDef * DMAx)1336 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
1337 {
1338 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)) ? 1UL : 0UL);
1339 }
1340 #endif /* DMA_ISR_TCIF4 */
1341
1342 #if defined(DMA_ISR_TCIF5)
1343 /**
1344 * @brief Get Channel 5 transfer complete flag.
1345 * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
1346 * @param DMAx DMAx Instance
1347 * @retval State of bit (1 or 0).
1348 */
LL_DMA_IsActiveFlag_TC5(DMA_TypeDef * DMAx)1349 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
1350 {
1351 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)) ? 1UL : 0UL);
1352 }
1353 #endif /* DMA_ISR_TCIF5 */
1354
1355 /**
1356 * @brief Get Channel 1 half transfer flag.
1357 * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
1358 * @param DMAx DMAx Instance
1359 * @retval State of bit (1 or 0).
1360 */
LL_DMA_IsActiveFlag_HT1(DMA_TypeDef * DMAx)1361 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
1362 {
1363 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)) ? 1UL : 0UL);
1364 }
1365
1366 /**
1367 * @brief Get Channel 2 half transfer flag.
1368 * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
1369 * @param DMAx DMAx Instance
1370 * @retval State of bit (1 or 0).
1371 */
LL_DMA_IsActiveFlag_HT2(DMA_TypeDef * DMAx)1372 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
1373 {
1374 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)) ? 1UL : 0UL);
1375 }
1376
1377 /**
1378 * @brief Get Channel 3 half transfer flag.
1379 * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
1380 * @param DMAx DMAx Instance
1381 * @retval State of bit (1 or 0).
1382 */
LL_DMA_IsActiveFlag_HT3(DMA_TypeDef * DMAx)1383 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
1384 {
1385 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)) ? 1UL : 0UL);
1386 }
1387
1388 #if defined(DMA_ISR_HTIF4)
1389 /**
1390 * @brief Get Channel 4 half transfer flag.
1391 * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
1392 * @param DMAx DMAx Instance
1393 * @retval State of bit (1 or 0).
1394 */
LL_DMA_IsActiveFlag_HT4(DMA_TypeDef * DMAx)1395 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
1396 {
1397 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)) ? 1UL : 0UL);
1398 }
1399 #endif /* DMA_ISR_HTIF4 */
1400
1401 #if defined(DMA_ISR_HTIF5)
1402 /**
1403 * @brief Get Channel 5 half transfer flag.
1404 * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
1405 * @param DMAx DMAx Instance
1406 * @retval State of bit (1 or 0).
1407 */
LL_DMA_IsActiveFlag_HT5(DMA_TypeDef * DMAx)1408 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
1409 {
1410 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)) ? 1UL : 0UL);
1411 }
1412 #endif /* DMA_ISR_HTIF5 */
1413
1414 /**
1415 * @brief Get Channel 1 transfer error flag.
1416 * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
1417 * @param DMAx DMAx Instance
1418 * @retval State of bit (1 or 0).
1419 */
LL_DMA_IsActiveFlag_TE1(DMA_TypeDef * DMAx)1420 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
1421 {
1422 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)) ? 1UL : 0UL);
1423 }
1424
1425 /**
1426 * @brief Get Channel 2 transfer error flag.
1427 * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
1428 * @param DMAx DMAx Instance
1429 * @retval State of bit (1 or 0).
1430 */
LL_DMA_IsActiveFlag_TE2(DMA_TypeDef * DMAx)1431 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
1432 {
1433 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)) ? 1UL : 0UL);
1434 }
1435
1436 /**
1437 * @brief Get Channel 3 transfer error flag.
1438 * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
1439 * @param DMAx DMAx Instance
1440 * @retval State of bit (1 or 0).
1441 */
LL_DMA_IsActiveFlag_TE3(DMA_TypeDef * DMAx)1442 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
1443 {
1444 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)) ? 1UL : 0UL);
1445 }
1446
1447 #if defined(DMA_ISR_TEIF4)
1448 /**
1449 * @brief Get Channel 4 transfer error flag.
1450 * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
1451 * @param DMAx DMAx Instance
1452 * @retval State of bit (1 or 0).
1453 */
LL_DMA_IsActiveFlag_TE4(DMA_TypeDef * DMAx)1454 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
1455 {
1456 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)) ? 1UL : 0UL);
1457 }
1458 #endif /* DMA_ISR_TEIF4 */
1459
1460 #if defined(DMA_ISR_TEIF5)
1461 /**
1462 * @brief Get Channel 5 transfer error flag.
1463 * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
1464 * @param DMAx DMAx Instance
1465 * @retval State of bit (1 or 0).
1466 */
LL_DMA_IsActiveFlag_TE5(DMA_TypeDef * DMAx)1467 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
1468 {
1469 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)) ? 1UL : 0UL);
1470 }
1471 #endif /* DMA_ISR_TEIF5 */
1472
1473 /**
1474 * @brief Clear Channel 1 global interrupt flag.
1475 * @note Do not Clear Channel 1 global interrupt flag when the channel in ON.
1476 Instead clear specific flags transfer complete, half transfer & transfer
1477 error flag with LL_DMA_ClearFlag_TC1, LL_DMA_ClearFlag_HT1,
1478 LL_DMA_ClearFlag_TE1. bug id 2.4.1 in Product Errata Sheet.
1479 * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
1480 * @param DMAx DMAx Instance
1481 * @retval None
1482 */
LL_DMA_ClearFlag_GI1(DMA_TypeDef * DMAx)1483 __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
1484 {
1485 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
1486 }
1487
1488 /**
1489 * @brief Clear Channel 2 global interrupt flag.
1490 * @note Do not Clear Channel 2 global interrupt flag when the channel in ON.
1491 Instead clear specific flags transfer complete, half transfer & transfer
1492 error flag with LL_DMA_ClearFlag_TC2, LL_DMA_ClearFlag_HT2,
1493 LL_DMA_ClearFlag_TE2. bug id 2.4.1 in Product Errata Sheet.
1494 * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
1495 * @param DMAx DMAx Instance
1496 * @retval None
1497 */
LL_DMA_ClearFlag_GI2(DMA_TypeDef * DMAx)1498 __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
1499 {
1500 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
1501 }
1502
1503 /**
1504 * @brief Clear Channel 3 global interrupt flag.
1505 * @note Do not Clear Channel 3 global interrupt flag when the channel in ON.
1506 Instead clear specific flags transfer complete, half transfer & transfer
1507 error flag with LL_DMA_ClearFlag_TC3, LL_DMA_ClearFlag_HT3,
1508 LL_DMA_ClearFlag_TE3. bug id 2.4.1 in Product Errata Sheet.
1509 * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
1510 * @param DMAx DMAx Instance
1511 * @retval None
1512 */
LL_DMA_ClearFlag_GI3(DMA_TypeDef * DMAx)1513 __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
1514 {
1515 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
1516 }
1517
1518 #if defined(DMA_IFCR_CGIF4)
1519 /**
1520 * @brief Clear Channel 4 global interrupt flag.
1521 * @note Do not Clear Channel 4 global interrupt flag when the channel in ON.
1522 Instead clear specific flags transfer complete, half transfer & transfer
1523 error flag with LL_DMA_ClearFlag_TC4, LL_DMA_ClearFlag_HT4,
1524 LL_DMA_ClearFlag_TE4. bug id 2.4.1 in Product Errata Sheet.
1525 * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
1526 * @param DMAx DMAx Instance
1527 * @retval None
1528 */
LL_DMA_ClearFlag_GI4(DMA_TypeDef * DMAx)1529 __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
1530 {
1531 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
1532 }
1533 #endif /* DMA_IFCR_CGIF4 */
1534
1535 #if defined(DMA_IFCR_CGIF5)
1536 /**
1537 * @brief Clear Channel 5 global interrupt flag.
1538 * @note Do not Clear Channel 5 global interrupt flag when the channel in ON.
1539 Instead clear specific flags transfer complete, half transfer & transfer
1540 error flag with LL_DMA_ClearFlag_TC5, LL_DMA_ClearFlag_HT5,
1541 LL_DMA_ClearFlag_TE5. bug id 2.4.1 in Product Errata Sheet.
1542 * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
1543 * @param DMAx DMAx Instance
1544 * @retval None
1545 */
LL_DMA_ClearFlag_GI5(DMA_TypeDef * DMAx)1546 __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
1547 {
1548 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
1549 }
1550 #endif /* DMA_IFCR_CGIF5 */
1551
1552 /**
1553 * @brief Clear Channel 1 transfer complete flag.
1554 * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
1555 * @param DMAx DMAx Instance
1556 * @retval None
1557 */
LL_DMA_ClearFlag_TC1(DMA_TypeDef * DMAx)1558 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
1559 {
1560 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
1561 }
1562
1563 /**
1564 * @brief Clear Channel 2 transfer complete flag.
1565 * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
1566 * @param DMAx DMAx Instance
1567 * @retval None
1568 */
LL_DMA_ClearFlag_TC2(DMA_TypeDef * DMAx)1569 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
1570 {
1571 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
1572 }
1573
1574 /**
1575 * @brief Clear Channel 3 transfer complete flag.
1576 * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
1577 * @param DMAx DMAx Instance
1578 * @retval None
1579 */
LL_DMA_ClearFlag_TC3(DMA_TypeDef * DMAx)1580 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
1581 {
1582 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
1583 }
1584
1585 #if defined(DMA_IFCR_CTCIF4)
1586 /**
1587 * @brief Clear Channel 4 transfer complete flag.
1588 * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
1589 * @param DMAx DMAx Instance
1590 * @retval None
1591 */
LL_DMA_ClearFlag_TC4(DMA_TypeDef * DMAx)1592 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
1593 {
1594 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
1595 }
1596 #endif /* DMA_IFCR_CTCIF4 */
1597
1598 #if defined(DMA_IFCR_CTCIF5)
1599 /**
1600 * @brief Clear Channel 5 transfer complete flag.
1601 * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
1602 * @param DMAx DMAx Instance
1603 * @retval None
1604 */
LL_DMA_ClearFlag_TC5(DMA_TypeDef * DMAx)1605 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
1606 {
1607 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
1608 }
1609 #endif /* DMA_IFCR_CTCIF5 */
1610
1611 /**
1612 * @brief Clear Channel 1 half transfer flag.
1613 * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
1614 * @param DMAx DMAx Instance
1615 * @retval None
1616 */
LL_DMA_ClearFlag_HT1(DMA_TypeDef * DMAx)1617 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
1618 {
1619 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
1620 }
1621
1622 /**
1623 * @brief Clear Channel 2 half transfer flag.
1624 * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
1625 * @param DMAx DMAx Instance
1626 * @retval None
1627 */
LL_DMA_ClearFlag_HT2(DMA_TypeDef * DMAx)1628 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
1629 {
1630 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
1631 }
1632
1633 /**
1634 * @brief Clear Channel 3 half transfer flag.
1635 * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
1636 * @param DMAx DMAx Instance
1637 * @retval None
1638 */
LL_DMA_ClearFlag_HT3(DMA_TypeDef * DMAx)1639 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
1640 {
1641 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
1642 }
1643
1644 #if defined(DMA_IFCR_CHTIF4)
1645 /**
1646 * @brief Clear Channel 4 half transfer flag.
1647 * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
1648 * @param DMAx DMAx Instance
1649 * @retval None
1650 */
LL_DMA_ClearFlag_HT4(DMA_TypeDef * DMAx)1651 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
1652 {
1653 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
1654 }
1655 #endif /* DMA_IFCR_CHTIF4 */
1656
1657 #if defined(DMA_IFCR_CHTIF5)
1658 /**
1659 * @brief Clear Channel 5 half transfer flag.
1660 * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
1661 * @param DMAx DMAx Instance
1662 * @retval None
1663 */
LL_DMA_ClearFlag_HT5(DMA_TypeDef * DMAx)1664 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
1665 {
1666 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
1667 }
1668 #endif /* DMA_IFCR_CHTIF5 */
1669
1670 /**
1671 * @brief Clear Channel 1 transfer error flag.
1672 * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
1673 * @param DMAx DMAx Instance
1674 * @retval None
1675 */
LL_DMA_ClearFlag_TE1(DMA_TypeDef * DMAx)1676 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
1677 {
1678 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
1679 }
1680
1681 /**
1682 * @brief Clear Channel 2 transfer error flag.
1683 * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
1684 * @param DMAx DMAx Instance
1685 * @retval None
1686 */
LL_DMA_ClearFlag_TE2(DMA_TypeDef * DMAx)1687 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
1688 {
1689 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
1690 }
1691
1692 /**
1693 * @brief Clear Channel 3 transfer error flag.
1694 * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
1695 * @param DMAx DMAx Instance
1696 * @retval None
1697 */
LL_DMA_ClearFlag_TE3(DMA_TypeDef * DMAx)1698 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
1699 {
1700 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
1701 }
1702
1703 #if defined(DMA_IFCR_CTEIF4)
1704 /**
1705 * @brief Clear Channel 4 transfer error flag.
1706 * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
1707 * @param DMAx DMAx Instance
1708 * @retval None
1709 */
LL_DMA_ClearFlag_TE4(DMA_TypeDef * DMAx)1710 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
1711 {
1712 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
1713 }
1714 #endif /* DMA_IFCR_CTEIF4 */
1715
1716 #if defined(DMA_IFCR_CTEIF5)
1717 /**
1718 * @brief Clear Channel 5 transfer error flag.
1719 * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
1720 * @param DMAx DMAx Instance
1721 * @retval None
1722 */
LL_DMA_ClearFlag_TE5(DMA_TypeDef * DMAx)1723 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
1724 {
1725 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
1726 }
1727 #endif /* DMA_IFCR_CTEIF5 */
1728
1729 /**
1730 * @}
1731 */
1732
1733 /** @defgroup DMA_LL_EF_IT_Management IT_Management
1734 * @{
1735 */
1736 /**
1737 * @brief Enable Transfer complete interrupt.
1738 * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
1739 * @param DMAx DMAx Instance
1740 * @param Channel This parameter can be one of the following values:
1741 * @arg @ref LL_DMA_CHANNEL_1
1742 * @arg @ref LL_DMA_CHANNEL_2
1743 * @arg @ref LL_DMA_CHANNEL_3
1744 * @arg @ref LL_DMA_CHANNEL_4 (*)
1745 * @arg @ref LL_DMA_CHANNEL_5 (*)
1746 * @note (*) Availability depends on devices
1747 * @retval None
1748 */
LL_DMA_EnableIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)1749 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
1750 {
1751 uint32_t dma_base_addr = (uint32_t)DMAx;
1752 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_TCIE);
1753 }
1754
1755 /**
1756 * @brief Enable Half transfer interrupt.
1757 * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
1758 * @param DMAx DMAx Instance
1759 * @param Channel This parameter can be one of the following values:
1760 * @arg @ref LL_DMA_CHANNEL_1
1761 * @arg @ref LL_DMA_CHANNEL_2
1762 * @arg @ref LL_DMA_CHANNEL_3
1763 * @arg @ref LL_DMA_CHANNEL_4 (*)
1764 * @arg @ref LL_DMA_CHANNEL_5 (*)
1765 * @note (*) Availability depends on devices
1766 * @retval None
1767 */
LL_DMA_EnableIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)1768 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
1769 {
1770 uint32_t dma_base_addr = (uint32_t)DMAx;
1771 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_HTIE);
1772 }
1773
1774 /**
1775 * @brief Enable Transfer error interrupt.
1776 * @rmtoll CCR TEIE LL_DMA_EnableIT_TE
1777 * @param DMAx DMAx Instance
1778 * @param Channel This parameter can be one of the following values:
1779 * @arg @ref LL_DMA_CHANNEL_1
1780 * @arg @ref LL_DMA_CHANNEL_2
1781 * @arg @ref LL_DMA_CHANNEL_3
1782 * @arg @ref LL_DMA_CHANNEL_4 (*)
1783 * @arg @ref LL_DMA_CHANNEL_5 (*)
1784 * @note (*) Availability depends on devices
1785 * @retval None
1786 */
LL_DMA_EnableIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)1787 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
1788 {
1789 uint32_t dma_base_addr = (uint32_t)DMAx;
1790 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_TEIE);
1791 }
1792
1793 /**
1794 * @brief Disable Transfer complete interrupt.
1795 * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
1796 * @param DMAx DMAx Instance
1797 * @param Channel This parameter can be one of the following values:
1798 * @arg @ref LL_DMA_CHANNEL_1
1799 * @arg @ref LL_DMA_CHANNEL_2
1800 * @arg @ref LL_DMA_CHANNEL_3
1801 * @arg @ref LL_DMA_CHANNEL_4 (*)
1802 * @arg @ref LL_DMA_CHANNEL_5 (*)
1803 * @note (*) Availability depends on devices
1804 * @retval None
1805 */
LL_DMA_DisableIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)1806 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
1807 {
1808 uint32_t dma_base_addr = (uint32_t)DMAx;
1809 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_TCIE);
1810 }
1811
1812 /**
1813 * @brief Disable Half transfer interrupt.
1814 * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
1815 * @param DMAx DMAx Instance
1816 * @param Channel This parameter can be one of the following values:
1817 * @arg @ref LL_DMA_CHANNEL_1
1818 * @arg @ref LL_DMA_CHANNEL_2
1819 * @arg @ref LL_DMA_CHANNEL_3
1820 * @arg @ref LL_DMA_CHANNEL_4 (*)
1821 * @arg @ref LL_DMA_CHANNEL_5 (*)
1822 * @note (*) Availability depends on devices
1823 * @retval None
1824 */
LL_DMA_DisableIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)1825 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
1826 {
1827 uint32_t dma_base_addr = (uint32_t)DMAx;
1828 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_HTIE);
1829 }
1830
1831 /**
1832 * @brief Disable Transfer error interrupt.
1833 * @rmtoll CCR TEIE LL_DMA_DisableIT_TE
1834 * @param DMAx DMAx Instance
1835 * @param Channel This parameter can be one of the following values:
1836 * @arg @ref LL_DMA_CHANNEL_1
1837 * @arg @ref LL_DMA_CHANNEL_2
1838 * @arg @ref LL_DMA_CHANNEL_3
1839 * @arg @ref LL_DMA_CHANNEL_4 (*)
1840 * @arg @ref LL_DMA_CHANNEL_5 (*)
1841 * @note (*) Availability depends on devices
1842 * @retval None
1843 */
LL_DMA_DisableIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)1844 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
1845 {
1846 uint32_t dma_base_addr = (uint32_t)DMAx;
1847 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_TEIE);
1848 }
1849
1850 /**
1851 * @brief Check if Transfer complete Interrupt is enabled.
1852 * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
1853 * @param DMAx DMAx Instance
1854 * @param Channel This parameter can be one of the following values:
1855 * @arg @ref LL_DMA_CHANNEL_1
1856 * @arg @ref LL_DMA_CHANNEL_2
1857 * @arg @ref LL_DMA_CHANNEL_3
1858 * @arg @ref LL_DMA_CHANNEL_4 (*)
1859 * @arg @ref LL_DMA_CHANNEL_5 (*)
1860 * @note (*) Availability depends on devices
1861 * @retval State of bit (1 or 0).
1862 */
LL_DMA_IsEnabledIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)1863 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
1864 {
1865 uint32_t dma_base_addr = (uint32_t)DMAx;
1866 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR,
1867 DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL);
1868 }
1869
1870 /**
1871 * @brief Check if Half transfer Interrupt is enabled.
1872 * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
1873 * @param DMAx DMAx Instance
1874 * @param Channel This parameter can be one of the following values:
1875 * @arg @ref LL_DMA_CHANNEL_1
1876 * @arg @ref LL_DMA_CHANNEL_2
1877 * @arg @ref LL_DMA_CHANNEL_3
1878 * @arg @ref LL_DMA_CHANNEL_4 (*)
1879 * @arg @ref LL_DMA_CHANNEL_5 (*)
1880 * @note (*) Availability depends on devices
1881 * @retval State of bit (1 or 0).
1882 */
LL_DMA_IsEnabledIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)1883 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
1884 {
1885 uint32_t dma_base_addr = (uint32_t)DMAx;
1886 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR,
1887 DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL);
1888 }
1889
1890 /**
1891 * @brief Check if Transfer error Interrupt is enabled.
1892 * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
1893 * @param DMAx DMAx Instance
1894 * @param Channel This parameter can be one of the following values:
1895 * @arg @ref LL_DMA_CHANNEL_1
1896 * @arg @ref LL_DMA_CHANNEL_2
1897 * @arg @ref LL_DMA_CHANNEL_3
1898 * @arg @ref LL_DMA_CHANNEL_4 (*)
1899 * @arg @ref LL_DMA_CHANNEL_5 (*)
1900 * @note (*) Availability depends on devices
1901 * @retval State of bit (1 or 0).
1902 */
LL_DMA_IsEnabledIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)1903 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
1904 {
1905 uint32_t dma_base_addr = (uint32_t)DMAx;
1906 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR,
1907 DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL);
1908 }
1909
1910 /**
1911 * @}
1912 */
1913
1914 #if defined(USE_FULL_LL_DRIVER)
1915 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
1916 * @{
1917 */
1918 ErrorStatus LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
1919 ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
1920 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
1921 /**
1922 * @}
1923 */
1924 #endif /* USE_FULL_LL_DRIVER */
1925
1926 /**
1927 * @}
1928 */
1929
1930 /**
1931 * @}
1932 */
1933
1934 #endif /* DMA1 */
1935
1936 /**
1937 * @}
1938 */
1939
1940 #ifdef __cplusplus
1941 }
1942 #endif
1943
1944 #endif /* STM32C0xx_LL_DMA_H */
1945
