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Searched refs:GTZC_TZIC (Results 1 – 11 of 11) sorted by relevance

/hal_stm32-3.5.0/stm32cube/stm32l5xx/drivers/src/
Dstm32l5xx_hal_gtzc.c1230 WRITE_REG(GTZC_TZIC->IER1, 0U); in HAL_GTZC_TZIC_DisableIT()
1231 WRITE_REG(GTZC_TZIC->IER2, 0U); in HAL_GTZC_TZIC_DisableIT()
1232 WRITE_REG(GTZC_TZIC->IER3, 0U); in HAL_GTZC_TZIC_DisableIT()
1237 register_address = (uint32_t) &(GTZC_TZIC->IER1) + (4U * GTZC_GET_REG_INDEX(PeriphId)); in HAL_GTZC_TZIC_DisableIT()
1265 WRITE_REG(GTZC_TZIC->IER1, TZIC_IER1_ALL); in HAL_GTZC_TZIC_EnableIT()
1266 WRITE_REG(GTZC_TZIC->IER2, TZIC_IER2_ALL); in HAL_GTZC_TZIC_EnableIT()
1267 WRITE_REG(GTZC_TZIC->IER3, TZIC_IER3_ALL); in HAL_GTZC_TZIC_EnableIT()
1272 register_address = (uint32_t) &(GTZC_TZIC->IER1) + (4U * GTZC_GET_REG_INDEX(PeriphId)); in HAL_GTZC_TZIC_EnableIT()
1308 reg_value = READ_REG(GTZC_TZIC->SR1); in HAL_GTZC_TZIC_GetFlag()
1314 reg_value = READ_REG(GTZC_TZIC->SR2); in HAL_GTZC_TZIC_GetFlag()
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/hal_stm32-3.5.0/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_hal_gtzc.c1203 WRITE_REG(GTZC_TZIC->IER1, 0U); in HAL_GTZC_TZIC_DisableIT()
1204 WRITE_REG(GTZC_TZIC->IER2, 0U); in HAL_GTZC_TZIC_DisableIT()
1205 WRITE_REG(GTZC_TZIC->IER3, 0U); in HAL_GTZC_TZIC_DisableIT()
1206 WRITE_REG(GTZC_TZIC->IER4, 0U); in HAL_GTZC_TZIC_DisableIT()
1211 register_address = (uint32_t) &(GTZC_TZIC->IER1) in HAL_GTZC_TZIC_DisableIT()
1241 WRITE_REG(GTZC_TZIC->IER1, TZIC1_IER1_ALL); in HAL_GTZC_TZIC_EnableIT()
1242 WRITE_REG(GTZC_TZIC->IER2, TZIC1_IER2_ALL); in HAL_GTZC_TZIC_EnableIT()
1243 WRITE_REG(GTZC_TZIC->IER3, TZIC1_IER3_ALL); in HAL_GTZC_TZIC_EnableIT()
1244 WRITE_REG(GTZC_TZIC->IER4, TZIC1_IER4_ALL); in HAL_GTZC_TZIC_EnableIT()
1249 register_address = (uint32_t) &(GTZC_TZIC->IER1) in HAL_GTZC_TZIC_EnableIT()
[all …]
/hal_stm32-3.5.0/stm32cube/stm32wlxx/drivers/src/
Dstm32wlxx_hal_gtzc.c565 WRITE_REG(GTZC_TZIC->IER1, 0U); in HAL_GTZC_TZIC_DisableIT()
572 register_address = (uint32_t)&(GTZC_TZIC->IER1) + (4U * GTZC_GET_REG_INDEX(PeriphId)); in HAL_GTZC_TZIC_DisableIT()
593 WRITE_REG(GTZC_TZIC->IER1, TZIC_IER1_ALL_Msk); in HAL_GTZC_TZIC_EnableIT()
600 register_address = (uint32_t)&(GTZC_TZIC->IER1) + (4U * GTZC_GET_REG_INDEX(PeriphId)); in HAL_GTZC_TZIC_EnableIT()
629 reg_value = READ_REG(GTZC_TZIC->MISR1); in HAL_GTZC_TZIC_GetFlag()
640 register_address = (uint32_t)&(GTZC_TZIC->MISR1) + (4U * GTZC_GET_REG_INDEX(PeriphId)); in HAL_GTZC_TZIC_GetFlag()
662 WRITE_REG(GTZC_TZIC->ICR1, TZIC_IER1_ALL_Msk); in HAL_GTZC_TZIC_ClearFlag()
669 register_address = (uint32_t)&(GTZC_TZIC->ICR1) + (4U * GTZC_GET_REG_INDEX(PeriphId)); in HAL_GTZC_TZIC_ClearFlag()
705 flag = GTZC_TZIC->MISR1; in HAL_GTZC_IRQHandler()
706 GTZC_TZIC->ICR1 = flag; in HAL_GTZC_IRQHandler()
/hal_stm32-3.5.0/stm32cube/stm32l5xx/soc/
Dstm32l552xx.h2251 #define GTZC_TZIC GTZC_TZIC_S macro
2665 #define GTZC_TZIC GTZC_TZIC_NS macro
Dstm32l562xx.h2353 #define GTZC_TZIC GTZC_TZIC_S macro
2788 #define GTZC_TZIC GTZC_TZIC_NS macro
/hal_stm32-3.5.0/stm32cube/stm32wlxx/soc/
Dstm32wl54xx.h1176 #define GTZC_TZIC ((GTZC_TZIC_TypeDef *) GTZC_TZIC_BASE) macro
Dstm32wl55xx.h1176 #define GTZC_TZIC ((GTZC_TZIC_TypeDef *) GTZC_TZIC_BASE) macro
Dstm32wl5mxx.h1176 #define GTZC_TZIC ((GTZC_TZIC_TypeDef *) GTZC_TZIC_BASE) macro
/hal_stm32-3.5.0/stm32cube/stm32wbaxx/soc/
Dstm32wba52xx.h1426 #define GTZC_TZIC GTZC_TZIC_S macro
Dstm32wba54xx.h1520 #define GTZC_TZIC GTZC_TZIC_S macro
Dstm32wba55xx.h1520 #define GTZC_TZIC GTZC_TZIC_S macro