1 /**
2 ******************************************************************************
3 * @file stm32wlxx_hal_gtzc.c
4 * @author MCD Application Team
5 * @brief GTZC HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of GTZC peripheral:
8 * + TZSC Initialization and Configuration functions
9 * + MPCWM Initialization and Configuration functions
10 * + TZSC and TZSC-MPCWM Lock functions
11 * + TZIC Initialization and Configuration functions
12 *
13 ******************************************************************************
14 * @attention
15 *
16 * Copyright (c) 2020 STMicroelectronics.
17 * All rights reserved.
18 *
19 * This software is licensed under terms that can be found in the LICENSE file
20 * in the root directory of this software component.
21 * If no LICENSE file comes with this software, it is provided AS-IS.
22 *
23 ******************************************************************************
24 @verbatim
25 ==============================================================================
26 ##### GTZC main features #####
27 ==============================================================================
28 [..]
29 (+) Global Security Controller (GTZC) composed of two sub-blocks:
30 (++) TZSC: Security controller
31 This sub-block defines the secure/privileged state of slave
32 peripherals. It also controls the unprivileged area size for the
33 watermark memory peripheral controller (MPCWM).
34 (++) TZIC: Security Illegal access controller
35 This sub-block gathers all illegal access events in the system and
36 generates a secure interrupt towards the secure CPU2 NVIC.
37
38 (+) These sub-blocks are used to configure system security and
39 privilege such as:
40 (++) on-chip Flash memory and RAM with programmable secure or privilege or
41 both area
42 (++) AHB and APB peripherals with programmable security and/or privileged
43 access
44
45 [..]
46 (+) TZIC accessible only with secure privileged transactions.
47 When the system is non-secure (ESE = 0), TZIC is not accessible.
48 (+) Secure and non-secure access supported for privileged and unprivileged
49 part of TZSC
50 (+) Set of registers to define product security settings:
51 (++) Privileged watermark for internal memories
52 (++) Secure and privileged access mode for securable peripherals
53
54 ##### How to use this driver #####
55 ==============================================================================
56 [..]
57 The GTZC HAL driver can be used as follows:
58
59 (#) Configure or get back securable peripherals attributes using
60 HAL_GTZC_TZSC_ConfigPeriphAttributes() / HAL_GTZC_TZSC_GetConfigPeriphAttributes()
61
62 (#) Configure or get back ecurable peripherals attributes using
63 HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes() / HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes()
64 (#) Lock TZSC sub-block or get lock status using HAL_GTZC_TZSC_Lock() /
65 HAL_GTZC_TZSC_GetLock()
66
67 (#) Illegal access detection can be configured through TZIC sub-block using
68 following functions: HAL_GTZC_TZIC_DisableIT() / HAL_GTZC_TZIC_EnableIT()
69
70 (#) Illegal access flags can be retrieved through HAL_GTZC_TZIC_GetFlag() and
71 HAL_GTZC_TZIC_ClearFlag() functions
72
73 (#) Illegal access interrupt service routing is served by HAL_GTZC_IRQHandler()
74 and user can add his own code using HAL_GTZC_TZIC_ILA_Callback()
75
76 @endverbatim
77 ******************************************************************************
78 */
79
80 /* Includes ------------------------------------------------------------------*/
81 #include "stm32wlxx_hal.h"
82
83 #if defined(GTZC_TZSC)
84 /** @addtogroup STM32WLxx_HAL_Driver
85 * @{
86 */
87
88 /** @defgroup GTZC GTZC
89 * @brief GTZC HAL module driver
90 * @{
91 */
92
93 #ifdef HAL_GTZC_MODULE_ENABLED
94
95 /* Private typedef -----------------------------------------------------------*/
96 /* Private Constants ---------------------------------------------------------*/
97 /* Private macros ------------------------------------------------------------*/
98 /* Private variables ---------------------------------------------------------*/
99 /* Private function prototypes -----------------------------------------------*/
100 /* Exported functions --------------------------------------------------------*/
101 /** @defgroup GTZC_Exported_Functions GTZC Exported Functions
102 * @{
103 */
104
105 /** @defgroup GTZC_Exported_Functions_Group1 TZSC Initialization and Configuration functions
106 * @brief TZSC Initialization and Configuration functions
107 *
108 @verbatim
109 ==============================================================================
110 ##### TZSC Initialization and Configuration functions #####
111 ==============================================================================
112 [..]
113 This section provides functions allowing to initialize/configure TZSC
114 TZSC: Security Controller
115 @endverbatim
116 * @{
117 */
118
119 /**
120 * @brief Configure TZSC on a single peripheral or on all peripherals
121 * @param PeriphId Peripheral identifier.
122 * This parameter can be a value of @ref GTZC_Peripheral_Identification
123 * @param PeriphAttributes Periph attribute (see structure in stm32wlxx_hal_gtzc.h).
124 * @retval HAL status
125 */
HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId,uint32_t PeriphAttributes)126 HAL_StatusTypeDef HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId, uint32_t PeriphAttributes)
127 {
128 uint32_t periphpos;
129
130 /* check entry parameters */
131 assert_param(IS_GTZC_TZSC_PERIPHERAL(PeriphId));
132 assert_param(IS_GTZC_ATTRIBUTE(PeriphAttributes));
133
134 if ((PeriphId & GTZC_PERIPH_ALL) != 0x00U)
135 {
136 /* special case where the same configuration is applied to all peripherals */
137
138 #if defined(CORE_CM0PLUS)
139 /* secure configuration */
140 if ((PeriphAttributes & GTZC_TZSC_ATTRIBUTE_SEC) != 0x00U)
141 {
142 GTZC_TZSC->SECCFGR1 = TZSC_SECCFGR1_ALL_Msk;
143 }
144 else
145 {
146 GTZC_TZSC->SECCFGR1 = 0x00U;
147 }
148 #endif
149
150 /* privilege configuration */
151 if ((PeriphAttributes & GTZC_TZSC_ATTRIBUTE_PRIV) != 0x00U)
152 {
153 GTZC_TZSC->PRIVCFGR1 = TZSC_PRIVCFGR1_ALL_Msk;
154 }
155 else
156 {
157 GTZC_TZSC->PRIVCFGR1 = 0x00U;
158 }
159 }
160 else
161 {
162 /* common case where only one peripheral is configured */
163 periphpos = (1UL << GTZC_GET_PERIPH_POS(PeriphId));
164
165 #if defined(CORE_CM0PLUS)
166 /* secure configuration. Make sure not to configure SUBGHZ SPI which is securable by option byte. */
167 if ((PeriphId != GTZC_PERIPH_SUBGHZSPI) && ((PeriphAttributes & GTZC_TZSC_ATTRIBUTE_SEC) != 0x00U))
168 {
169 GTZC_TZSC->SECCFGR1 |= periphpos;
170 }
171 else
172 {
173 GTZC_TZSC->SECCFGR1 &= ~periphpos;
174 }
175 #endif
176
177 /* privilege configuration */
178 if ((PeriphAttributes & GTZC_TZSC_ATTRIBUTE_PRIV) != 0x00U)
179 {
180 GTZC_TZSC->PRIVCFGR1 |= periphpos;
181 }
182 else
183 {
184 GTZC_TZSC->PRIVCFGR1 &= ~periphpos;
185 }
186 }
187
188 return HAL_OK;
189 }
190
191
192 /**
193 * @brief Get TZSC configuration on a single peripheral or on all peripherals
194 * @param PeriphId Peripheral identifier.
195 * This parameter can be a value of @ref GTZC_Peripheral_Identification
196 * @param PeriphAttributes Pointer to the periph attributes (see structure in stm32wlxx_hal_gtzc.h).
197 * If PeriphId target a single peripheral, pointer on a single element.
198 * If all peripherals selected, pointer to an array of GTZC_PERIPH_TZSC_MAX elements
199 * @retval HAL status
200 */
HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId,uint32_t * PeriphAttributes)201 HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId, uint32_t *PeriphAttributes)
202 {
203 uint32_t reg_value;
204 uint32_t periphpos;
205 uint32_t index;
206
207 /* check entry parameters */
208 assert_param(IS_GTZC_TZSC_PERIPHERAL(PeriphId));
209
210 /* check null pointer */
211 if (PeriphAttributes == NULL)
212 {
213 return HAL_ERROR;
214 }
215
216 if ((PeriphId & GTZC_PERIPH_ALL) != 0x00U)
217 {
218
219 /* special case where the configuration getting is requested for all peripherals */
220 /* get secure configuration: read each register and deploy each bit value */
221 /* in bit0 of corresponding index in the destination array */
222 reg_value = (GTZC_TZSC->SECCFGR1 & TZSC_SECCFGR1_ALL_Msk);
223 periphpos = 0;
224 for (index = 0U; index < GTZC_TZSC_PERIPH_NUMBER; index++)
225 {
226 /* Check what are TZSC peripheral position. Here use privilege mask as
227 reference because SPISUBGHZ is securable by option byte */
228 while((TZSC_PRIVCFGR1_ALL_Msk & (1UL << periphpos)) == 0x00U)
229 {
230 /* increment peripheral position */
231 periphpos++;
232 }
233
234 if ((reg_value & (1UL << periphpos)) != 0x00U)
235 {
236 PeriphAttributes[index] = GTZC_TZSC_ATTRIBUTE_SEC;
237 }
238 else
239 {
240 PeriphAttributes[index] = GTZC_TZSC_ATTRIBUTE_NSEC;
241 }
242
243 /* increment peripheral position */
244 periphpos++;
245 }
246
247 /* do the same for get privilege configuration but on bit1 */
248 reg_value = (GTZC_TZSC->PRIVCFGR1 & TZSC_PRIVCFGR1_ALL_Msk);
249 periphpos = 0;
250 for (index = 0U; index < GTZC_TZSC_PERIPH_NUMBER; index++)
251 {
252 /* Check what are TZSC peripheral position */
253 while((TZSC_PRIVCFGR1_ALL_Msk & (1UL << periphpos)) == 0x00U)
254 {
255 /* increment peripheral position */
256 periphpos++;
257 }
258
259 if ((reg_value & (1UL << periphpos)) != 0x00U)
260 {
261 PeriphAttributes[index] |= GTZC_TZSC_ATTRIBUTE_PRIV;
262 }
263 else
264 {
265 /* do nothing */
266 }
267
268 /* increment peripheral position */
269 periphpos++;
270 }
271 }
272 else
273 {
274 /* common case where only one peripheral is configured */
275 /* secure configuration */
276 reg_value = GTZC_TZSC->SECCFGR1;
277
278 if ((reg_value & (1UL << GTZC_GET_PERIPH_POS(PeriphId))) != 0x00U)
279 {
280 *PeriphAttributes = GTZC_TZSC_ATTRIBUTE_SEC;
281 }
282 else
283 {
284 *(PeriphAttributes) = GTZC_TZSC_ATTRIBUTE_NSEC;
285 }
286
287 /* privilege configuration */
288 reg_value = GTZC_TZSC->PRIVCFGR1;
289
290 if ((reg_value & (1UL << GTZC_GET_PERIPH_POS(PeriphId))) != 0x00U)
291 {
292 *PeriphAttributes |= GTZC_TZSC_ATTRIBUTE_PRIV;
293 }
294 else
295 {
296 /* do nothing */
297 }
298 }
299 return HAL_OK;
300 }
301
302 /**
303 * @}
304 */
305
306 /** @defgroup GTZC_Exported_Functions_Group2 MPCWM Initialization and Configuration functions
307 * @brief MPCWM Initialization and Configuration functions
308 *
309 @verbatim
310 ==============================================================================
311 ##### MPCWM Initialization and Configuration functions #####
312 ==============================================================================
313 [..]
314 This section provides functions allowing to initialize/configure MPCWM
315 MPCWM: Memory Protection Controller WaterMark
316 @endverbatim
317 * @{
318 */
319
320 /**
321 * @brief Configure a TZSC-MPCWM area.
322 * @param MemBaseAddress WM identifier.
323 * @param pMPCWM_Desc TZSC-MPCWM descriptor pointer.
324 * The structure description is available in @ref GTZC_Exported_Types.
325 * @retval HAL status.
326 */
HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress,MPCWM_ConfigTypeDef * pMPCWM_Desc)327 HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress, MPCWM_ConfigTypeDef *pMPCWM_Desc)
328 {
329 __IO uint32_t *pregister;
330 HAL_StatusTypeDef status = HAL_OK;
331 uint32_t reg_value;
332 uint32_t length_pos;
333 uint32_t length_msk;
334 uint32_t gran_offset;
335
336 /* check entry parameters */
337 assert_param(IS_GTZC_MPCWM_MEMORY_BASEADDRESS(MemBaseAddress));
338
339 switch (MemBaseAddress)
340 {
341 case FLASH_BASE:
342 /* check descriptor content vs. memory capacity */
343 assert_param(IS_GTZC_MPCWM_FLASH_AREAID(pMPCWM_Desc->AreaId));
344 assert_param(IS_GTZC_MPCWM_FLASH_LENGTH(pMPCWM_Desc->Length));
345
346 /* Set local variable with Flash MPCWM characteristics */
347 gran_offset = GTZC_TZSC_MPCWM_GRANULARITY_FLASH_OFFSET;
348 if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_AREAID_UNPRIV)
349 {
350 pregister = &(GTZC_TZSC->MPCWM1_UPWMR);
351 length_pos = TZSC_MPCWM1_UPWMR_LGTH_Pos;
352 length_msk = TZSC_MPCWM1_UPWMR_LGTH_Msk;
353 }
354 else
355 {
356 pregister = &(GTZC_TZSC->MPCWM1_UPWWMR);
357 length_pos = TZSC_MPCWM1_UPWWMR_LGTH_Pos;
358 length_msk = TZSC_MPCWM1_UPWWMR_LGTH_Msk;
359 }
360 break;
361
362 case SRAM1_BASE:
363 /* check descriptor content vs. memory capacity */
364 assert_param(IS_GTZC_MPCWM_SRAM1_AREAID(pMPCWM_Desc->AreaId));
365 assert_param(IS_GTZC_MPCWM_SRAM1_LENGTH(pMPCWM_Desc->Length));
366
367 /* Set local variable with Sram1 MPCWM characteristics */
368 gran_offset = GTZC_TZSC_MPCWM_GRANULARITY_SRAM1_OFFSET;
369 pregister = &(GTZC_TZSC->MPCWM2_UPWMR);
370 length_pos = TZSC_MPCWM2_UPWMR_LGTH_Pos;
371 length_msk = TZSC_MPCWM2_UPWMR_LGTH_Msk;
372 break;
373
374 case SRAM2_BASE:
375 /* check descriptor content vs. memory capacity */
376 assert_param(IS_GTZC_MPCWM_SRAM2_AREAID(pMPCWM_Desc->AreaId));
377 assert_param(IS_GTZC_MPCWM_SRAM2_LENGTH(pMPCWM_Desc->Length));
378
379 /* Set local variable with Sram2 MPCWM characteristics */
380 gran_offset = GTZC_TZSC_MPCWM_GRANULARITY_SRAM2_OFFSET;
381 pregister = &(GTZC_TZSC->MPCWM3_UPWMR);
382 length_pos = TZSC_MPCWM3_UPWMR_LGTH_Pos;
383 length_msk = TZSC_MPCWM3_UPWMR_LGTH_Msk;
384 break;
385
386 default:
387 status = HAL_ERROR;
388 break;
389 }
390
391 if(status != HAL_ERROR)
392 {
393 /* Store length */
394 reg_value = *pregister & ~length_msk;
395 *pregister = (reg_value | ((pMPCWM_Desc->Length >> gran_offset) << length_pos));
396 }
397 else
398 {
399 /* Do nothing */
400 }
401
402 return status;
403 }
404
405
406 /**
407 * @brief Get a TZSC-MPCWM area configuration.
408 * @param MemBaseAddress WM identifier.
409 * @param pMPCWM_Desc pointer to a TZSC-MPCWM descriptor.
410 * The structure description is available in @ref GTZC_Exported_Types.
411 * @retval HAL status.
412 */
HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress,MPCWM_ConfigTypeDef * pMPCWM_Desc)413 HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress, MPCWM_ConfigTypeDef *pMPCWM_Desc)
414 {
415 __IO uint32_t *pregister;
416 HAL_StatusTypeDef status = HAL_OK;
417 uint32_t reg_value;
418 uint32_t length_pos;
419 uint32_t length_msk;
420 uint32_t gran_offset;
421
422 /* check entry parameters */
423 assert_param(IS_GTZC_MPCWM_MEMORY_BASEADDRESS(MemBaseAddress));
424
425 /* depending on targted memory */
426 switch (MemBaseAddress)
427 {
428 case FLASH_BASE:
429 /* check descriptor content vs. memory capacity */
430 assert_param(IS_GTZC_MPCWM_FLASH_AREAID(pMPCWM_Desc->AreaId));
431
432 /* Set local variable with Flash MPCWM characteristics */
433 gran_offset = GTZC_TZSC_MPCWM_GRANULARITY_FLASH_OFFSET;
434 if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_AREAID_UNPRIV)
435 {
436 pregister = &(GTZC_TZSC->MPCWM1_UPWMR);
437 length_pos = TZSC_MPCWM1_UPWMR_LGTH_Pos;
438 length_msk = TZSC_MPCWM1_UPWMR_LGTH_Msk;
439 }
440 else
441 {
442 pregister = &(GTZC_TZSC->MPCWM1_UPWWMR);
443 length_pos = TZSC_MPCWM1_UPWWMR_LGTH_Pos;
444 length_msk = TZSC_MPCWM1_UPWWMR_LGTH_Msk;
445 }
446 break;
447
448 case SRAM1_BASE:
449 /* check descriptor content vs. memory capacity */
450 assert_param(IS_GTZC_MPCWM_SRAM1_AREAID(pMPCWM_Desc->AreaId));
451
452 /* Set local variable with Sram1 MPCWM characteristics */
453 gran_offset = GTZC_TZSC_MPCWM_GRANULARITY_SRAM1_OFFSET;
454 pregister = &(GTZC_TZSC->MPCWM2_UPWMR);
455 length_pos = TZSC_MPCWM2_UPWMR_LGTH_Pos;
456 length_msk = TZSC_MPCWM2_UPWMR_LGTH_Msk;
457
458 break;
459
460 case SRAM2_BASE:
461 /* check descriptor content vs. memory capacity */
462 assert_param(IS_GTZC_MPCWM_SRAM2_AREAID(pMPCWM_Desc->AreaId));
463
464 /* Set local variable with Sram2 MPCWM characteristics */
465 gran_offset = GTZC_TZSC_MPCWM_GRANULARITY_SRAM2_OFFSET;
466 pregister = &(GTZC_TZSC->MPCWM3_UPWMR);
467 length_pos = TZSC_MPCWM3_UPWMR_LGTH_Pos;
468 length_msk = TZSC_MPCWM3_UPWMR_LGTH_Msk;
469 break;
470
471 default:
472 status = HAL_ERROR;
473 break;
474 }
475
476 if(status != HAL_ERROR)
477 {
478 /* Store length */
479 reg_value = (*pregister & length_msk) >> length_pos;
480 pMPCWM_Desc->Length = (reg_value << gran_offset);
481 }
482 else
483 {
484 /* Do nothing */
485 }
486
487 return status;
488 }
489
490
491 /**
492 * @}
493 */
494
495 /** @defgroup GTZC_Exported_Functions_Group3 TZSC and TZSC-MPCWM Lock functions
496 * @brief TZSC-MPCWM Lock functions
497 *
498 @verbatim
499 ==============================================================================
500 ##### TZSC and TZSC-MPCWM Lock functions #####
501 ==============================================================================
502 [..]
503 This section provides functions allowing to manage the common TZSC and TZSC-MPCWM lock.
504 It includes lock enable, and current value read.
505 TZSC: Security Controller
506 MPCWM: Memory Protection Controller WaterMark
507 @endverbatim
508 * @{
509 */
510
511 /**
512 * @brief Get TZSC and TZSC-MPCWM configuration lock state.
513 * @param TZSCx TZSC sub-block instance.
514 * @retval Lock State (GTZC_TZSC_LOCK_OFF or GTZC_TZSC_LOCK_ON)
515 */
HAL_GTZC_TZSC_GetLock(GTZC_TZSC_TypeDef * TZSCx)516 uint32_t HAL_GTZC_TZSC_GetLock(GTZC_TZSC_TypeDef *TZSCx)
517 {
518 return (READ_BIT(TZSCx->CR, TZSC_CR_LCK_Msk) >> TZSC_CR_LCK_Pos);
519 }
520
521
522 #if defined(CORE_CM0PLUS)
523 /**
524 * @brief Lock TZSC and TZSC-MPCWM configuration.
525 * @param TZSCx TZSC sub-block instance.
526 * @retval None
527 */
HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef * TZSCx)528 void HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef *TZSCx)
529 {
530 SET_BIT(TZSCx->CR, TZSC_CR_LCK_Msk);
531 }
532
533 /**
534 * @}
535 */
536
537 /** @defgroup GTZC_Exported_Functions_Group4 TZIC Initialization and Configuration functions
538 * @brief TZIC Initialization and Configuration functions
539 *
540 @verbatim
541 ==============================================================================
542 ##### TZIC Initialization and Configuration functions #####
543 ==============================================================================
544 [..]
545 This section provides functions allowing to initialize/configure TZIC
546 TZIC: Security Interrupt Controller
547 @endverbatim
548 * @{
549 */
550
551 /**
552 * @brief Disable an IT on a single TZIC peripheral or on all peripherals.
553 * @param PeriphId Peripheral identifier.
554 * This parameter can be a value of @ref GTZC_Peripheral_Identification
555 * @retval HAL status
556 */
HAL_GTZC_TZIC_DisableIT(uint32_t PeriphId)557 HAL_StatusTypeDef HAL_GTZC_TZIC_DisableIT(uint32_t PeriphId)
558 {
559 /* check entry parameter */
560 assert_param(IS_GTZC_TZIC_PERIPHERAL(PeriphId));
561
562 if ((PeriphId & GTZC_PERIPH_ALL) != 0x00U)
563 {
564 /* special case where the same configuration is applied to all peripherals */
565 WRITE_REG(GTZC_TZIC->IER1, 0U);
566 }
567 else
568 {
569 uint32_t register_address;
570
571 /* common case where only one peripheral is configured */
572 register_address = (uint32_t)&(GTZC_TZIC->IER1) + (4U * GTZC_GET_REG_INDEX(PeriphId));
573 CLEAR_BIT(*(uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
574 }
575
576 return HAL_OK;
577 }
578
579 /**
580 * @brief Enable an interrupt on a single TZIC peripheral or on all peripherals.
581 * @param PeriphId Peripheral identifier.
582 * This parameter can be a value of @ref GTZC_Peripheral_Identification
583 * @retval HAL status
584 */
HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId)585 HAL_StatusTypeDef HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId)
586 {
587 /* check entry parameter */
588 assert_param(IS_GTZC_TZIC_PERIPHERAL(PeriphId));
589
590 if ((PeriphId & GTZC_PERIPH_ALL) != 0x00U)
591 {
592 /* special case where the same configuration is applied to all peripherals */
593 WRITE_REG(GTZC_TZIC->IER1, TZIC_IER1_ALL_Msk);
594 }
595 else
596 {
597 uint32_t register_address;
598
599 /* common case where only one peripheral is configured */
600 register_address = (uint32_t)&(GTZC_TZIC->IER1) + (4U * GTZC_GET_REG_INDEX(PeriphId));
601 SET_BIT(*(uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
602 }
603
604 return HAL_OK;
605 }
606
607
608 /**
609 * @brief Get interrupt flag on a single TZIC peripheral or on all peripherals.
610 * @param PeriphId Peripheral identifier.
611 * This parameter can be a value of @ref GTZC_Peripheral_Identification
612 * @param pFlag Pointer to the flags.
613 * If PeriphId target a single peripheral, pointer on a single element.
614 * If all peripherals selected, pointer to an array of GTZC_PERIPH_TZIC_MAX elements
615 * Element content is either GTZC_TZIC_NO_ILA_EVENT or GTZC_TZIC_ILA_EVENT_PENDING
616 * @retval HAL status
617 */
HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId,uint32_t * pFlag)618 HAL_StatusTypeDef HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId, uint32_t *pFlag)
619 {
620 /* check entry parameter */
621 assert_param(IS_GTZC_TZIC_PERIPHERAL(PeriphId));
622
623 if ((PeriphId & GTZC_PERIPH_ALL) != 0x00U)
624 {
625 uint32_t i;
626 uint32_t reg_value;
627
628 /* special case where it is applied to all peripherals */
629 reg_value = READ_REG(GTZC_TZIC->MISR1);
630 for (i = 0U; i < GTZC_TZIC_PERIPH_NUMBER; i++)
631 {
632 pFlag[i] = (reg_value & (1UL << i)) >> i;
633 }
634 }
635 else
636 {
637 uint32_t register_address;
638
639 /* common case where only one peripheral is concerned */
640 register_address = (uint32_t)&(GTZC_TZIC->MISR1) + (4U * GTZC_GET_REG_INDEX(PeriphId));
641 *pFlag = READ_BIT(*(uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId)) >> GTZC_GET_PERIPH_POS(PeriphId);
642 }
643
644 return HAL_OK;
645 }
646
647
648 /**
649 * @brief Clear interrupt flag on a single TZIC peripheral or on all peripherals.
650 * @param PeriphId Peripheral identifier.
651 * This parameter can be a value of @ref GTZC_Peripheral_Identification
652 * @retval HAL status
653 */
HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId)654 HAL_StatusTypeDef HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId)
655 {
656 /* check entry parameter */
657 assert_param(IS_GTZC_TZIC_PERIPHERAL(PeriphId));
658
659 if ((PeriphId & GTZC_PERIPH_ALL) != 0x00U)
660 {
661 /* special case where the same configuration is applied to all peripherals */
662 WRITE_REG(GTZC_TZIC->ICR1, TZIC_IER1_ALL_Msk);
663 }
664 else
665 {
666 uint32_t register_address;
667
668 /* common case where only one peripheral is configured */
669 register_address = (uint32_t)&(GTZC_TZIC->ICR1) + (4U * GTZC_GET_REG_INDEX(PeriphId));
670 SET_BIT(*(uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
671 }
672
673 return HAL_OK;
674 }
675
676 /**
677 * @}
678 */
679
680
681 /** @defgroup GTZC_Exported_Functions_Group5 TZIC IRQ Handler and Callback
682 * @brief TZIC IRQ Handler and Callback
683 *
684 @verbatim
685 ==============================================================================
686 ##### TZIC IRQ Handler and Callback functions #####
687 ==============================================================================
688 [..]
689 This section provides functions allowing to treat ISR and provide user callback
690 @endverbatim
691 * @{
692 */
693
694 /**
695 * @brief Handle GTZC TZIC interrupt request.
696 * @param none
697 * @retval None
698 */
HAL_GTZC_IRQHandler(void)699 void HAL_GTZC_IRQHandler(void)
700 {
701 uint32_t position = 0x00u;
702 uint32_t flag;
703
704 /* Get Mask interrupt and then clear them */
705 flag = GTZC_TZIC->MISR1;
706 GTZC_TZIC->ICR1 = flag;
707
708 /* Loop on flag to check, which ones have been raised */
709 while ((flag >> position) != 0x00u)
710 {
711 if ((flag & (1UL << position)) != 0x00u)
712 {
713 HAL_GTZC_TZIC_Callback(GTZC_PERIPH_REG1 | position);
714 }
715
716 /* Position bit to be updated */
717 position++;
718 }
719 }
720
721
722 /**
723 * @brief GTZC TZIC Illegal Access callback.
724 * @param PeriphId Peripheral identifier.
725 * This parameter can be a value of @ref GTZC_Peripheral_Identification
726 * @retval None
727 */
HAL_GTZC_TZIC_Callback(uint32_t PeriphId)728 __weak void HAL_GTZC_TZIC_Callback(uint32_t PeriphId)
729 {
730 /* Prevent unused argument(s) compilation warning */
731 UNUSED(PeriphId);
732
733 /* NOTE: This function should not be modified, when the callback is needed,
734 the HAL_GTZC_TZIC_Callback could be implemented in the user file
735 */
736 }
737
738 #endif
739 /**
740 * @}
741 */
742
743 /**
744 * @}
745 */
746
747 #endif /* HAL_GTZC_MODULE_ENABLED */
748
749 /**
750 * @}
751 */
752
753 /**
754 * @}
755 */
756 #endif /* GTZC_TZSC */
757
