Searched refs:PCR (Results 1 – 10 of 10) sorted by relevance
93 PORTB->PCR[19] = (PORTB->PCR[19] & ~PORT_PCR_MUX_MASK) | in set_modem_clock()96 PORTC->PCR[0] = (PORTC->PCR[0] & ~PORT_PCR_MUX_MASK) | in set_modem_clock()
7 bool "MCHP XEC PCR clock control driver"11 Enable support for Microchip XEC PCR clock driver.
86 if (pin >= ARRAY_SIZE(port_base->PCR)) { in gpio_rv32m1_configure()158 port_base->PCR[pin] = (port_base->PCR[pin] & ~mask) | pcr; in gpio_rv32m1_configure()227 if (pin >= ARRAY_SIZE(port_base->PCR)) { in gpio_rv32m1_pin_interrupt_configure()239 port_base->PCR[pin] = (port_base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | pcr; in gpio_rv32m1_pin_interrupt_configure()
45 if (pin >= ARRAY_SIZE(port_base->PCR)) { in gpio_mcux_configure()122 port_base->PCR[pin] = (port_base->PCR[pin] & ~mask) | pcr; in gpio_mcux_configure()275 if (pin >= ARRAY_SIZE(port_base->PCR)) { in gpio_mcux_pin_interrupt_configure()294 port_base->PCR[pin] = (port_base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | pcr; in gpio_mcux_pin_interrupt_configure()
26 # SYSTICK. SYSTICK frequency is 96 MHz divided down by the MEC172x PCR27 # processor clock divider register. We assume PCR processor clock divider
40 base->PCR[pin] = (base->PCR[pin] & (~Z_PINCTRL_RV32M1_PCR_MASK)) | mux; in pinctrl_configure_pins()
50 base->PCR[pin] = (base->PCR[pin] & (~Z_PINCTRL_NXP_PORT_PCR_MASK)) | mux; in pinctrl_configure_pins()
66 Prints MEC172x VBAT and PCR register pertaining to power on status and
1582 * :github:`29059` - HAL: mchp: Missing PCR ids to control PM for certain HW blocks
