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Searched refs:bus_id (Results 1 – 9 of 9) sorted by relevance

/hal_espressif-latest/components/esp_mm/port/esp32s2/
Dext_mem_layout.c22 .bus_id = CACHE_BUS_IBUS0,
30 .bus_id = CACHE_BUS_IBUS2,
38 .bus_id = CACHE_BUS_DBUS2,
46 .bus_id = CACHE_BUS_DBUS1,
54 .bus_id = CACHE_BUS_DBUS0,
/hal_espressif-latest/components/esp_mm/port/esp32/
Dext_mem_layout.c22 .bus_id = CACHE_BUS_IBUS0,
30 .bus_id = CACHE_BUS_DBUS0,
38 .bus_id = CACHE_BUS_DBUS1,
/hal_espressif-latest/components/esp_mm/
Desp_mmu_map.c87 cache_bus_mask_t bus_id; //cache bus mask of this region member
139 if (bus_mask & hw_mem_regions[i].bus_id) { in s_reserve_irom_region()
167 if (bus_mask & hw_mem_regions[i].bus_id) { in s_reserve_drom_region()
191 hw_mem_regions[i].bus_id = g_mmu_mem_regions[i].bus_id; in esp_mmu_map_init()
195 assert(__builtin_popcount(hw_mem_regions[i].bus_id) == 1); in esp_mmu_map_init()
213 b->bus_id |= a->bus_id; in esp_mmu_map_init()
638 s_mmu_ctx.mem_regions[i].bus_id, in esp_mmu_map_dump_mapped_blocks()
689 ESP_DRAM_LOGI(TAG, "region bus_id: 0x%x", s_mmu_ctx.mem_regions[i].bus_id); in esp_mmu_map_dump_mapped_blocks_private()
Dext_mem_layout.h24 cache_bus_mask_t bus_id; //bus_id mask, for accessible cache buses member
/hal_espressif-latest/components/esp_mm/port/esp32c2/
Dext_mem_layout.c21 .bus_id = CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0,
/hal_espressif-latest/components/esp_mm/port/esp32c3/
Dext_mem_layout.c21 .bus_id = CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0,
/hal_espressif-latest/components/esp_mm/port/esp32c6/
Dext_mem_layout.c22 .bus_id = CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0,
/hal_espressif-latest/components/esp_mm/port/esp32h2/
Dext_mem_layout.c22 .bus_id = CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0,
/hal_espressif-latest/components/esp_mm/port/esp32s3/
Dext_mem_layout.c21 .bus_id = CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0,