1 /*
2  * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 #include <stdlib.h>
7 #include <stdint.h>
8 #include "sdkconfig.h"
9 #include "soc/ext_mem_defs.h"
10 #include "../ext_mem_layout.h"
11 
12 /**
13  * These regions is referring to linear address
14  * The start addresses in this list should always be sorted from low to high, as MMU driver will need to
15  * coalesce adjacent regions
16  */
17 const mmu_mem_region_t g_mmu_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = {
18     [0] = {
19         .start = SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW,
20         .end = SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH,
21         .size = BUS_SIZE(SOC_MMU_IRAM0_LINEAR),
22         .bus_id = CACHE_BUS_IBUS0,
23         .targets = MMU_TARGET_FLASH0 | MMU_TARGET_PSRAM0,
24         .caps = MMU_MEM_CAP_EXEC | MMU_MEM_CAP_32BIT,
25     },
26     [1] = {
27         .start = SOC_MMU_DROM0_LINEAR_ADDRESS_LOW,
28         .end = SOC_MMU_DROM0_LINEAR_ADDRESS_HIGH,
29         .size = BUS_SIZE(SOC_MMU_DROM0_LINEAR),
30         .bus_id = CACHE_BUS_IBUS2,
31         .targets = MMU_TARGET_FLASH0 | MMU_TARGET_PSRAM0,
32         .caps = MMU_MEM_CAP_READ | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT,
33     },
34     [2] = {
35         .start = SOC_MMU_DPORT_LINEAR_ADDRESS_LOW,
36         .end = SOC_MMU_DPORT_LINEAR_ADDRESS_HIGH,
37         .size = BUS_SIZE(SOC_MMU_DPORT_LINEAR),
38         .bus_id = CACHE_BUS_DBUS2,
39         .targets = MMU_TARGET_FLASH0 | MMU_TARGET_PSRAM0,
40         .caps = MMU_MEM_CAP_READ | MMU_MEM_CAP_WRITE | MMU_MEM_CAP_32BIT,
41     },
42     [3] = {
43         .start = SOC_MMU_DRAM1_LINEAR_ADDRESS_LOW,
44         .end = SOC_MMU_DRAM1_LINEAR_ADDRESS_HIGH,
45         .size = BUS_SIZE(SOC_MMU_DRAM1_LINEAR),
46         .bus_id = CACHE_BUS_DBUS1,
47         .targets = MMU_TARGET_FLASH0 | MMU_TARGET_PSRAM0,
48         .caps = MMU_MEM_CAP_READ | MMU_MEM_CAP_WRITE | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT,
49     },
50     [4] = {
51         .start = SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW,
52         .end = SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH,
53         .size = BUS_SIZE(SOC_MMU_DRAM0_LINEAR),
54         .bus_id = CACHE_BUS_DBUS0,
55         .targets = MMU_TARGET_FLASH0 | MMU_TARGET_PSRAM0,
56         .caps = MMU_MEM_CAP_READ | MMU_MEM_CAP_WRITE | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT,
57     },
58 };
59