Searched refs:RTC_CNTL_SLOW_CLK_CONF_REG (Results 1 – 12 of 12) sorted by relevance
| /hal_espressif-latest/components/esp_hw_support/port/esp32c2/ |
| D | rtc_time.c | 178 SET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_SLOW_CLK_NEXT_EDGE); in rtc_clk_wait_for_slow_cycle()
179 while (GET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_SLOW_CLK_NEXT_EDGE)) { in rtc_clk_wait_for_slow_cycle()
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| /hal_espressif-latest/components/esp_hw_support/port/esp32c3/ |
| D | rtc_time.c | 181 SET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_SLOW_CLK_NEXT_EDGE); in rtc_clk_wait_for_slow_cycle()
182 while (GET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_SLOW_CLK_NEXT_EDGE)) { in rtc_clk_wait_for_slow_cycle()
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| /hal_espressif-latest/components/esp_hw_support/port/esp32s3/ |
| D | rtc_time.c | 180 SET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_SLOW_CLK_NEXT_EDGE); in rtc_clk_wait_for_slow_cycle()
181 while (GET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_SLOW_CLK_NEXT_EDGE)) { in rtc_clk_wait_for_slow_cycle()
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| /hal_espressif-latest/components/hal/esp32c2/include/hal/ |
| D | clk_tree_ll.h | 500 CLEAR_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV_VLD); in clk_ll_rc_slow_set_divider()
501 REG_SET_FIELD(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV, divider - 1); in clk_ll_rc_slow_set_divider()
502 SET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV_VLD); in clk_ll_rc_slow_set_divider()
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| /hal_espressif-latest/components/esp_hw_support/port/esp32s2/ |
| D | rtc_time.c | 246 SET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_SLOW_CLK_NEXT_EDGE); in rtc_clk_wait_for_slow_cycle()
247 while (GET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_SLOW_CLK_NEXT_EDGE)) { in rtc_clk_wait_for_slow_cycle()
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| /hal_espressif-latest/components/hal/esp32s3/include/hal/ |
| D | clk_tree_ll.h | 610 CLEAR_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV_VLD); in clk_ll_rc_slow_set_divider()
611 REG_SET_FIELD(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV, divider - 1); in clk_ll_rc_slow_set_divider()
612 SET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV_VLD); in clk_ll_rc_slow_set_divider()
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| /hal_espressif-latest/components/hal/esp32c3/include/hal/ |
| D | clk_tree_ll.h | 608 CLEAR_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV_VLD); in clk_ll_rc_slow_set_divider()
609 REG_SET_FIELD(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV, divider - 1); in clk_ll_rc_slow_set_divider()
610 SET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV_VLD); in clk_ll_rc_slow_set_divider()
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| /hal_espressif-latest/components/hal/esp32s2/include/hal/ |
| D | clk_tree_ll.h | 723 CLEAR_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV_VLD); in clk_ll_rc_slow_set_divider()
724 REG_SET_FIELD(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV, divider - 1); in clk_ll_rc_slow_set_divider()
725 SET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV_VLD); in clk_ll_rc_slow_set_divider()
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| /hal_espressif-latest/components/soc/esp32c2/include/soc/ |
| D | rtc_cntl_reg.h | 771 #define RTC_CNTL_SLOW_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x6C) macro
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| /hal_espressif-latest/components/soc/esp32c3/include/soc/ |
| D | rtc_cntl_reg.h | 1102 #define RTC_CNTL_SLOW_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0074) macro
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| /hal_espressif-latest/components/soc/esp32s2/include/soc/ |
| D | rtc_cntl_reg.h | 1306 #define RTC_CNTL_SLOW_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0078) macro
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| /hal_espressif-latest/components/soc/esp32s3/include/soc/ |
| D | rtc_cntl_reg.h | 1411 #define RTC_CNTL_SLOW_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x78) macro
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