1 /*
2  * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #include <stdint.h>
8 #include "esp_rom_sys.h"
9 #include "soc/rtc.h"
10 #include "soc/rtc_cntl_reg.h"
11 #include "hal/clk_tree_ll.h"
12 #include "hal/rtc_cntl_ll.h"
13 #include "soc/timer_group_reg.h"
14 
15 /* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0.
16  * This feature counts the number of XTAL clock cycles within a given number of
17  * RTC_SLOW_CLK cycles.
18  *
19  * Slow clock calibration feature has two modes of operation: one-off and cycling.
20  * In cycling mode (which is enabled by default on SoC reset), counting of XTAL
21  * cycles within RTC_SLOW_CLK cycle is done continuously. Cycling mode is enabled
22  * using TIMG_RTC_CALI_START_CYCLING bit. In one-off mode counting is performed
23  * once, and TIMG_RTC_CALI_RDY bit is set when counting is done. One-off mode is
24  * enabled using TIMG_RTC_CALI_START bit.
25  */
26 
27 /**
28  * @brief Clock calibration function used by rtc_clk_cal and rtc_clk_cal_ratio
29  * @param cal_clk which clock to calibrate
30  * @param slowclk_cycles number of slow clock cycles to count
31  * @return number of XTAL clock cycles within the given number of slow clock cycles
32  */
rtc_clk_cal_internal(rtc_cal_sel_t cal_clk,uint32_t slowclk_cycles)33 uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
34 {
35     /* On ESP32S3, choosing RTC_CAL_RTC_MUX results in calibration of
36      * the 150k RTC clock regardless of the currenlty selected SLOW_CLK.
37      * On the ESP32, it used the currently selected SLOW_CLK.
38      * The following code emulates ESP32 behavior:
39      */
40     if (cal_clk == RTC_CAL_RTC_MUX) {
41         soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get();
42         if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
43             cal_clk = RTC_CAL_32K_XTAL;
44         } else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) {
45             cal_clk = RTC_CAL_8MD256;
46         }
47     } else if (cal_clk == RTC_CAL_INTERNAL_OSC) {
48         cal_clk = RTC_CAL_RTC_MUX;
49     }
50 
51     /* Enable requested clock (150k clock is always on) */
52     bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled();
53     if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
54         clk_ll_xtal32k_digi_enable();
55     }
56 
57     bool rc_fast_enabled = clk_ll_rc_fast_is_enabled();
58     bool rc_fast_d256_enabled = clk_ll_rc_fast_d256_is_enabled();
59     if (cal_clk == RTC_CAL_8MD256) {
60         rtc_clk_8m_enable(true, true);
61         clk_ll_rc_fast_d256_digi_enable();
62     }
63     /* There may be another calibration process already running during we call this function,
64      * so we should wait the last process is done.
65      */
66     if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING)) {
67         /**
68          * Set a small timeout threshold to accelerate the generation of timeout.
69          * The internal circuit will be reset when the timeout occurs and will not affect the next calibration.
70          */
71         REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, 1);
72         while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)
73                && !GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT));
74     }
75 
76     /* Prepare calibration */
77     REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cal_clk);
78     CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
79     REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles);
80     /* Figure out how long to wait for calibration to finish */
81 
82     /* Set timeout reg and expect time delay*/
83     uint32_t expected_freq;
84     if (cal_clk == RTC_CAL_32K_XTAL) {
85         REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(slowclk_cycles));
86         expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX;
87     } else if (cal_clk == RTC_CAL_8MD256) {
88         REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(slowclk_cycles));
89         expected_freq = SOC_CLK_RC_FAST_D256_FREQ_APPROX;
90     } else {
91         REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(slowclk_cycles));
92         expected_freq = SOC_CLK_RC_SLOW_FREQ_APPROX;
93     }
94     uint32_t us_time_estimate = (uint32_t) (((uint64_t) slowclk_cycles) * MHZ / expected_freq);
95     /* Start calibration */
96     CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
97     SET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
98 
99     /* Wait for calibration to finish up to another us_time_estimate */
100     esp_rom_delay_us(us_time_estimate);
101     uint32_t cal_val;
102     while (true) {
103         if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)) {
104             cal_val = REG_GET_FIELD(TIMG_RTCCALICFG1_REG(0), TIMG_RTC_CALI_VALUE);
105             break;
106         }
107         if (GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)) {
108             cal_val = 0;
109             break;
110         }
111     }
112     CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
113 
114     /* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */
115     if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
116         clk_ll_xtal32k_digi_disable();
117     }
118 
119     if (cal_clk == RTC_CAL_8MD256) {
120         clk_ll_rc_fast_d256_digi_disable();
121         rtc_clk_8m_enable(rc_fast_enabled, rc_fast_d256_enabled);
122     }
123 
124     return cal_val;
125 }
126 
rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk,uint32_t slowclk_cycles)127 uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
128 {
129     assert(slowclk_cycles);
130     uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles);
131     uint64_t ratio_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT)) / slowclk_cycles;
132     uint32_t ratio = (uint32_t)(ratio_64 & UINT32_MAX);
133     return ratio;
134 }
135 
rtc_clk_cal_32k_valid(rtc_xtal_freq_t xtal_freq,uint32_t slowclk_cycles,uint64_t actual_xtal_cycles)136 static inline bool rtc_clk_cal_32k_valid(rtc_xtal_freq_t xtal_freq, uint32_t slowclk_cycles, uint64_t actual_xtal_cycles)
137 {
138     uint64_t expected_xtal_cycles = (xtal_freq * 1000000ULL * slowclk_cycles) >> 15; // xtal_freq(hz) * slowclk_cycles / 32768
139     uint64_t delta = expected_xtal_cycles / 2000;                                    // 5/10000
140     return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta));
141 }
142 
rtc_clk_cal(rtc_cal_sel_t cal_clk,uint32_t slowclk_cycles)143 uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
144 {
145     assert(slowclk_cycles);
146     rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
147     uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles);
148 
149     if ((cal_clk == RTC_CAL_32K_XTAL) && !rtc_clk_cal_32k_valid(xtal_freq, slowclk_cycles, xtal_cycles)) {
150         return 0;
151     }
152 
153     uint64_t divider = ((uint64_t)xtal_freq) * slowclk_cycles;
154     uint64_t period_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT) + divider / 2 - 1) / divider;
155     uint32_t period = (uint32_t)(period_64 & UINT32_MAX);
156     return period;
157 }
158 
rtc_time_us_to_slowclk(uint64_t time_in_us,uint32_t period)159 uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period)
160 {
161     assert(period);
162     /* Overflow will happen in this function if time_in_us >= 2^45, which is about 400 days.
163      * TODO: fix overflow.
164      */
165     return (time_in_us << RTC_CLK_CAL_FRACT) / period;
166 }
167 
rtc_time_slowclk_to_us(uint64_t rtc_cycles,uint32_t period)168 uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
169 {
170     return (rtc_cycles * period) >> RTC_CLK_CAL_FRACT;
171 }
172 
rtc_time_get(void)173 uint64_t rtc_time_get(void)
174 {
175     return rtc_cntl_ll_get_rtc_time();
176 }
177 
rtc_clk_wait_for_slow_cycle(void)178 void rtc_clk_wait_for_slow_cycle(void) //This function may not by useful any more
179 {
180     SET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_SLOW_CLK_NEXT_EDGE);
181     while (GET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_SLOW_CLK_NEXT_EDGE)) {
182         esp_rom_delay_us(1);
183     }
184 }
185 
rtc_clk_freq_cal(uint32_t cal_val)186 uint32_t rtc_clk_freq_cal(uint32_t cal_val)
187 {
188     if (cal_val == 0) {
189         return 0;   // cal_val will be denominator, return 0 as the symbol of failure.
190     }
191     return 1000000ULL * (1 << RTC_CLK_CAL_FRACT) / cal_val;
192 }
193