1 /*
2 * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <stdint.h>
8 #include "esp32c3/rom/ets_sys.h"
9 #include "soc/rtc.h"
10 #include "soc/rtc_cntl_reg.h"
11 #include "hal/clk_tree_ll.h"
12 #include "hal/rtc_cntl_ll.h"
13 #include "soc/timer_group_reg.h"
14 #include "esp_rom_sys.h"
15
16 /* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0.
17 * This feature counts the number of XTAL clock cycles within a given number of
18 * RTC_SLOW_CLK cycles.
19 *
20 * Slow clock calibration feature has two modes of operation: one-off and cycling.
21 * In cycling mode (which is enabled by default on SoC reset), counting of XTAL
22 * cycles within RTC_SLOW_CLK cycle is done continuously. Cycling mode is enabled
23 * using TIMG_RTC_CALI_START_CYCLING bit. In one-off mode counting is performed
24 * once, and TIMG_RTC_CALI_RDY bit is set when counting is done. One-off mode is
25 * enabled using TIMG_RTC_CALI_START bit.
26 */
27
28 /**
29 * @brief Clock calibration function used by rtc_clk_cal and rtc_clk_cal_ratio
30 * @param cal_clk which clock to calibrate
31 * @param slowclk_cycles number of slow clock cycles to count
32 * @return number of XTAL clock cycles within the given number of slow clock cycles
33 */
rtc_clk_cal_internal(rtc_cal_sel_t cal_clk,uint32_t slowclk_cycles)34 uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
35 {
36 /* On ESP32C3, choosing RTC_CAL_RTC_MUX results in calibration of
37 * the 150k RTC clock regardless of the currenlty selected SLOW_CLK.
38 * On the ESP32, it used the currently selected SLOW_CLK.
39 * The following code emulates ESP32 behavior:
40 */
41 if (cal_clk == RTC_CAL_RTC_MUX) {
42 soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get();
43 if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
44 cal_clk = RTC_CAL_32K_XTAL;
45 } else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) {
46 cal_clk = RTC_CAL_8MD256;
47 }
48 } else if (cal_clk == RTC_CAL_INTERNAL_OSC) {
49 cal_clk = RTC_CAL_RTC_MUX;
50 }
51
52
53 /* Enable requested clock (150k clock is always on) */
54 bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled();
55 if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
56 clk_ll_xtal32k_digi_enable();
57 }
58
59 bool rc_fast_enabled = clk_ll_rc_fast_is_enabled();
60 bool rc_fast_d256_enabled = clk_ll_rc_fast_d256_is_enabled();
61 if (cal_clk == RTC_CAL_8MD256) {
62 rtc_clk_8m_enable(true, true);
63 clk_ll_rc_fast_d256_digi_enable();
64 }
65 /* There may be another calibration process already running during we call this function,
66 * so we should wait the last process is done.
67 */
68 if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING)) {
69 /**
70 * Set a small timeout threshold to accelerate the generation of timeout.
71 * The internal circuit will be reset when the timeout occurs and will not affect the next calibration.
72 */
73 REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, 1);
74 while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)
75 && !GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT));
76 }
77
78 /* Prepare calibration */
79 REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cal_clk);
80 CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
81 REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles);
82 /* Figure out how long to wait for calibration to finish */
83
84 /* Set timeout reg and expect time delay*/
85 uint32_t expected_freq;
86 if (cal_clk == RTC_CAL_32K_XTAL) {
87 REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(slowclk_cycles));
88 expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX;
89 } else if (cal_clk == RTC_CAL_8MD256) {
90 REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(slowclk_cycles));
91 expected_freq = SOC_CLK_RC_FAST_D256_FREQ_APPROX;
92 } else {
93 REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(slowclk_cycles));
94 expected_freq = SOC_CLK_RC_SLOW_FREQ_APPROX;
95 }
96 uint32_t us_time_estimate = (uint32_t) (((uint64_t) slowclk_cycles) * MHZ / expected_freq);
97 /* Start calibration */
98 CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
99 SET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
100
101 /* Wait for calibration to finish up to another us_time_estimate */
102 esp_rom_delay_us(us_time_estimate);
103 uint32_t cal_val;
104 while (true) {
105 if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)) {
106 cal_val = REG_GET_FIELD(TIMG_RTCCALICFG1_REG(0), TIMG_RTC_CALI_VALUE);
107 break;
108 }
109 if (GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)) {
110 cal_val = 0;
111 break;
112 }
113 }
114 CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
115
116 /* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */
117 if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
118 clk_ll_xtal32k_digi_disable();
119 }
120
121 if (cal_clk == RTC_CAL_8MD256) {
122 clk_ll_rc_fast_d256_digi_disable();
123 rtc_clk_8m_enable(rc_fast_enabled, rc_fast_d256_enabled);
124 }
125
126 return cal_val;
127 }
128
rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk,uint32_t slowclk_cycles)129 uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
130 {
131 assert(slowclk_cycles);
132 uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles);
133 uint64_t ratio_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT)) / slowclk_cycles;
134 uint32_t ratio = (uint32_t)(ratio_64 & UINT32_MAX);
135 return ratio;
136 }
137
rtc_clk_cal_32k_valid(rtc_xtal_freq_t xtal_freq,uint32_t slowclk_cycles,uint64_t actual_xtal_cycles)138 static bool rtc_clk_cal_32k_valid(rtc_xtal_freq_t xtal_freq, uint32_t slowclk_cycles, uint64_t actual_xtal_cycles)
139 {
140 uint64_t expected_xtal_cycles = (xtal_freq * 1000000ULL * slowclk_cycles) >> 15; // xtal_freq(hz) * slowclk_cycles / 32768
141 uint64_t delta = expected_xtal_cycles / 2000; // 5/10000
142 return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta));
143 }
144
rtc_clk_cal(rtc_cal_sel_t cal_clk,uint32_t slowclk_cycles)145 uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
146 {
147 assert(slowclk_cycles);
148 rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
149 uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles);
150
151 if ((cal_clk == RTC_CAL_32K_XTAL) && !rtc_clk_cal_32k_valid(xtal_freq, slowclk_cycles, xtal_cycles))
152 return 0;
153
154 uint64_t divider = ((uint64_t)xtal_freq) * slowclk_cycles;
155 uint64_t period_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT) + divider / 2 - 1) / divider;
156 uint32_t period = (uint32_t)(period_64 & UINT32_MAX);
157 return period;
158 }
159
rtc_time_us_to_slowclk(uint64_t time_in_us,uint32_t period)160 uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period)
161 {
162 assert(period);
163 /* Overflow will happen in this function if time_in_us >= 2^45, which is about 400 days.
164 * TODO: fix overflow.
165 */
166 return (time_in_us << RTC_CLK_CAL_FRACT) / period;
167 }
168
rtc_time_slowclk_to_us(uint64_t rtc_cycles,uint32_t period)169 uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
170 {
171 return (rtc_cycles * period) >> RTC_CLK_CAL_FRACT;
172 }
173
rtc_time_get(void)174 uint64_t rtc_time_get(void)
175 {
176 return rtc_cntl_ll_get_rtc_time();
177 }
178
rtc_clk_wait_for_slow_cycle(void)179 void rtc_clk_wait_for_slow_cycle(void) //This function may not by useful any more
180 {
181 SET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_SLOW_CLK_NEXT_EDGE);
182 while (GET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_SLOW_CLK_NEXT_EDGE)) {
183 esp_rom_delay_us(1);
184 }
185 }
186
rtc_clk_freq_cal(uint32_t cal_val)187 uint32_t rtc_clk_freq_cal(uint32_t cal_val)
188 {
189 if (cal_val == 0) {
190 return 0; // cal_val will be denominator, return 0 as the symbol of failure.
191 }
192 return 1000000ULL * (1 << RTC_CLK_CAL_FRACT) / cal_val;
193 }
194