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Searched refs:DR_REG_AES_BASE (Results 1 – 12 of 12) sorted by relevance

/hal_espressif-latest/components/soc/esp32s2/include/soc/
Dhwcrypto_reg.h66 #define AES_MODE_REG ((DR_REG_AES_BASE) + 0x40)
67 #define AES_ENDIAN_REG ((DR_REG_AES_BASE) + 0x44)
68 #define AES_TRIGGER_REG ((DR_REG_AES_BASE) + 0x48)
69 #define AES_STATE_REG ((DR_REG_AES_BASE) + 0x4c)
70 #define AES_DMA_ENABLE_REG ((DR_REG_AES_BASE) + 0x90)
71 #define AES_BLOCK_MODE_REG ((DR_REG_AES_BASE) + 0x94)
72 #define AES_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0x98)
73 #define AES_INC_SEL_REG ((DR_REG_AES_BASE) + 0x9C)
74 #define AES_AAD_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0xA0)
75 #define AES_BIT_VALID_NUM_REG ((DR_REG_AES_BASE) + 0xA4)
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Dreg_base.h14 #define DR_REG_AES_BASE 0x6003a000 macro
/hal_espressif-latest/components/soc/esp32h2/include/soc/
Daes_reg.h17 #define AES_KEY_0_REG (DR_REG_AES_BASE + 0x0)
29 #define AES_KEY_1_REG (DR_REG_AES_BASE + 0x4)
41 #define AES_KEY_2_REG (DR_REG_AES_BASE + 0x8)
53 #define AES_KEY_3_REG (DR_REG_AES_BASE + 0xc)
65 #define AES_KEY_4_REG (DR_REG_AES_BASE + 0x10)
77 #define AES_KEY_5_REG (DR_REG_AES_BASE + 0x14)
89 #define AES_KEY_6_REG (DR_REG_AES_BASE + 0x18)
101 #define AES_KEY_7_REG (DR_REG_AES_BASE + 0x1c)
113 #define AES_TEXT_IN_0_REG (DR_REG_AES_BASE + 0x20)
125 #define AES_TEXT_IN_1_REG (DR_REG_AES_BASE + 0x24)
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Dreg_base.h31 #define DR_REG_AES_BASE 0x60088000 macro
/hal_espressif-latest/components/soc/esp32c6/include/soc/
Daes_reg.h17 #define AES_KEY_0_REG (DR_REG_AES_BASE + 0x0)
29 #define AES_KEY_1_REG (DR_REG_AES_BASE + 0x4)
41 #define AES_KEY_2_REG (DR_REG_AES_BASE + 0x8)
53 #define AES_KEY_3_REG (DR_REG_AES_BASE + 0xc)
65 #define AES_KEY_4_REG (DR_REG_AES_BASE + 0x10)
77 #define AES_KEY_5_REG (DR_REG_AES_BASE + 0x14)
89 #define AES_KEY_6_REG (DR_REG_AES_BASE + 0x18)
101 #define AES_KEY_7_REG (DR_REG_AES_BASE + 0x1c)
113 #define AES_TEXT_IN_0_REG (DR_REG_AES_BASE + 0x20)
125 #define AES_TEXT_IN_1_REG (DR_REG_AES_BASE + 0x24)
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Dreg_base.h40 #define DR_REG_AES_BASE 0x60088000 macro
/hal_espressif-latest/components/soc/esp32c3/include/soc/
Dhwcrypto_reg.h77 #define AES_MODE_REG ((DR_REG_AES_BASE) + 0x40)
78 #define AES_ENDIAN_REG ((DR_REG_AES_BASE) + 0x44)
79 #define AES_TRIGGER_REG ((DR_REG_AES_BASE) + 0x48)
80 #define AES_STATE_REG ((DR_REG_AES_BASE) + 0x4c)
81 #define AES_DMA_ENABLE_REG ((DR_REG_AES_BASE) + 0x90)
82 #define AES_BLOCK_MODE_REG ((DR_REG_AES_BASE) + 0x94)
83 #define AES_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0x98)
84 #define AES_INC_SEL_REG ((DR_REG_AES_BASE) + 0x9C)
85 #define AES_AAD_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0xA0)
86 #define AES_BIT_VALID_NUM_REG ((DR_REG_AES_BASE) + 0xA4)
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Dreg_base.h11 #define DR_REG_AES_BASE 0x6003a000 macro
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Dhwcrypto_reg.h64 #define AES_MODE_REG ((DR_REG_AES_BASE) + 0x40)
65 #define AES_ENDIAN_REG ((DR_REG_AES_BASE) + 0x44)
66 #define AES_TRIGGER_REG ((DR_REG_AES_BASE) + 0x48)
67 #define AES_STATE_REG ((DR_REG_AES_BASE) + 0x4c)
68 #define AES_DMA_ENABLE_REG ((DR_REG_AES_BASE) + 0x90)
69 #define AES_BLOCK_MODE_REG ((DR_REG_AES_BASE) + 0x94)
70 #define AES_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0x98)
71 #define AES_INC_SEL_REG ((DR_REG_AES_BASE) + 0x9C)
72 #define AES_CONTINUE_REG ((DR_REG_AES_BASE) + 0xA8)
73 #define AES_INT_CLEAR_REG ((DR_REG_AES_BASE) + 0xAC)
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Dreg_base.h51 #define DR_REG_AES_BASE 0x6003A000 macro
/hal_espressif-latest/components/soc/esp32/include/soc/
Dhwcrypto_reg.h67 #define AES_START_REG ((DR_REG_AES_BASE) + 0x00)
68 #define AES_IDLE_REG ((DR_REG_AES_BASE) + 0x04)
69 #define AES_MODE_REG ((DR_REG_AES_BASE) + 0x08)
70 #define AES_KEY_BASE ((DR_REG_AES_BASE) + 0x10)
71 #define AES_TEXT_BASE ((DR_REG_AES_BASE) + 0x30)
72 #define AES_ENDIAN ((DR_REG_AES_BASE) + 0x40)
Dreg_base.h7 #define DR_REG_AES_BASE 0x3ff01000 macro