1 /** 2 * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #include "soc/soc.h" 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 /** AES_KEY_0_REG register 15 * Key material key_0 configure register 16 */ 17 #define AES_KEY_0_REG (DR_REG_AES_BASE + 0x0) 18 /** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0; 19 * This bits stores key_0 that is a part of key material. 20 */ 21 #define AES_KEY_0 0xFFFFFFFFU 22 #define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S) 23 #define AES_KEY_0_V 0xFFFFFFFFU 24 #define AES_KEY_0_S 0 25 26 /** AES_KEY_1_REG register 27 * Key material key_1 configure register 28 */ 29 #define AES_KEY_1_REG (DR_REG_AES_BASE + 0x4) 30 /** AES_KEY_1 : R/W; bitpos: [31:0]; default: 0; 31 * This bits stores key_1 that is a part of key material. 32 */ 33 #define AES_KEY_1 0xFFFFFFFFU 34 #define AES_KEY_1_M (AES_KEY_1_V << AES_KEY_1_S) 35 #define AES_KEY_1_V 0xFFFFFFFFU 36 #define AES_KEY_1_S 0 37 38 /** AES_KEY_2_REG register 39 * Key material key_2 configure register 40 */ 41 #define AES_KEY_2_REG (DR_REG_AES_BASE + 0x8) 42 /** AES_KEY_2 : R/W; bitpos: [31:0]; default: 0; 43 * This bits stores key_2 that is a part of key material. 44 */ 45 #define AES_KEY_2 0xFFFFFFFFU 46 #define AES_KEY_2_M (AES_KEY_2_V << AES_KEY_2_S) 47 #define AES_KEY_2_V 0xFFFFFFFFU 48 #define AES_KEY_2_S 0 49 50 /** AES_KEY_3_REG register 51 * Key material key_3 configure register 52 */ 53 #define AES_KEY_3_REG (DR_REG_AES_BASE + 0xc) 54 /** AES_KEY_3 : R/W; bitpos: [31:0]; default: 0; 55 * This bits stores key_3 that is a part of key material. 56 */ 57 #define AES_KEY_3 0xFFFFFFFFU 58 #define AES_KEY_3_M (AES_KEY_3_V << AES_KEY_3_S) 59 #define AES_KEY_3_V 0xFFFFFFFFU 60 #define AES_KEY_3_S 0 61 62 /** AES_KEY_4_REG register 63 * Key material key_4 configure register 64 */ 65 #define AES_KEY_4_REG (DR_REG_AES_BASE + 0x10) 66 /** AES_KEY_4 : R/W; bitpos: [31:0]; default: 0; 67 * This bits stores key_4 that is a part of key material. 68 */ 69 #define AES_KEY_4 0xFFFFFFFFU 70 #define AES_KEY_4_M (AES_KEY_4_V << AES_KEY_4_S) 71 #define AES_KEY_4_V 0xFFFFFFFFU 72 #define AES_KEY_4_S 0 73 74 /** AES_KEY_5_REG register 75 * Key material key_5 configure register 76 */ 77 #define AES_KEY_5_REG (DR_REG_AES_BASE + 0x14) 78 /** AES_KEY_5 : R/W; bitpos: [31:0]; default: 0; 79 * This bits stores key_5 that is a part of key material. 80 */ 81 #define AES_KEY_5 0xFFFFFFFFU 82 #define AES_KEY_5_M (AES_KEY_5_V << AES_KEY_5_S) 83 #define AES_KEY_5_V 0xFFFFFFFFU 84 #define AES_KEY_5_S 0 85 86 /** AES_KEY_6_REG register 87 * Key material key_6 configure register 88 */ 89 #define AES_KEY_6_REG (DR_REG_AES_BASE + 0x18) 90 /** AES_KEY_6 : R/W; bitpos: [31:0]; default: 0; 91 * This bits stores key_6 that is a part of key material. 92 */ 93 #define AES_KEY_6 0xFFFFFFFFU 94 #define AES_KEY_6_M (AES_KEY_6_V << AES_KEY_6_S) 95 #define AES_KEY_6_V 0xFFFFFFFFU 96 #define AES_KEY_6_S 0 97 98 /** AES_KEY_7_REG register 99 * Key material key_7 configure register 100 */ 101 #define AES_KEY_7_REG (DR_REG_AES_BASE + 0x1c) 102 /** AES_KEY_7 : R/W; bitpos: [31:0]; default: 0; 103 * This bits stores key_7 that is a part of key material. 104 */ 105 #define AES_KEY_7 0xFFFFFFFFU 106 #define AES_KEY_7_M (AES_KEY_7_V << AES_KEY_7_S) 107 #define AES_KEY_7_V 0xFFFFFFFFU 108 #define AES_KEY_7_S 0 109 110 /** AES_TEXT_IN_0_REG register 111 * source text material text_in_0 configure register 112 */ 113 #define AES_TEXT_IN_0_REG (DR_REG_AES_BASE + 0x20) 114 /** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0; 115 * This bits stores text_in_0 that is a part of source text material. 116 */ 117 #define AES_TEXT_IN_0 0xFFFFFFFFU 118 #define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S) 119 #define AES_TEXT_IN_0_V 0xFFFFFFFFU 120 #define AES_TEXT_IN_0_S 0 121 122 /** AES_TEXT_IN_1_REG register 123 * source text material text_in_1 configure register 124 */ 125 #define AES_TEXT_IN_1_REG (DR_REG_AES_BASE + 0x24) 126 /** AES_TEXT_IN_1 : R/W; bitpos: [31:0]; default: 0; 127 * This bits stores text_in_1 that is a part of source text material. 128 */ 129 #define AES_TEXT_IN_1 0xFFFFFFFFU 130 #define AES_TEXT_IN_1_M (AES_TEXT_IN_1_V << AES_TEXT_IN_1_S) 131 #define AES_TEXT_IN_1_V 0xFFFFFFFFU 132 #define AES_TEXT_IN_1_S 0 133 134 /** AES_TEXT_IN_2_REG register 135 * source text material text_in_2 configure register 136 */ 137 #define AES_TEXT_IN_2_REG (DR_REG_AES_BASE + 0x28) 138 /** AES_TEXT_IN_2 : R/W; bitpos: [31:0]; default: 0; 139 * This bits stores text_in_2 that is a part of source text material. 140 */ 141 #define AES_TEXT_IN_2 0xFFFFFFFFU 142 #define AES_TEXT_IN_2_M (AES_TEXT_IN_2_V << AES_TEXT_IN_2_S) 143 #define AES_TEXT_IN_2_V 0xFFFFFFFFU 144 #define AES_TEXT_IN_2_S 0 145 146 /** AES_TEXT_IN_3_REG register 147 * source text material text_in_3 configure register 148 */ 149 #define AES_TEXT_IN_3_REG (DR_REG_AES_BASE + 0x2c) 150 /** AES_TEXT_IN_3 : R/W; bitpos: [31:0]; default: 0; 151 * This bits stores text_in_3 that is a part of source text material. 152 */ 153 #define AES_TEXT_IN_3 0xFFFFFFFFU 154 #define AES_TEXT_IN_3_M (AES_TEXT_IN_3_V << AES_TEXT_IN_3_S) 155 #define AES_TEXT_IN_3_V 0xFFFFFFFFU 156 #define AES_TEXT_IN_3_S 0 157 158 /** AES_TEXT_OUT_0_REG register 159 * result text material text_out_0 configure register 160 */ 161 #define AES_TEXT_OUT_0_REG (DR_REG_AES_BASE + 0x30) 162 /** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0; 163 * This bits stores text_out_0 that is a part of result text material. 164 */ 165 #define AES_TEXT_OUT_0 0xFFFFFFFFU 166 #define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S) 167 #define AES_TEXT_OUT_0_V 0xFFFFFFFFU 168 #define AES_TEXT_OUT_0_S 0 169 170 /** AES_TEXT_OUT_1_REG register 171 * result text material text_out_1 configure register 172 */ 173 #define AES_TEXT_OUT_1_REG (DR_REG_AES_BASE + 0x34) 174 /** AES_TEXT_OUT_1 : R/W; bitpos: [31:0]; default: 0; 175 * This bits stores text_out_1 that is a part of result text material. 176 */ 177 #define AES_TEXT_OUT_1 0xFFFFFFFFU 178 #define AES_TEXT_OUT_1_M (AES_TEXT_OUT_1_V << AES_TEXT_OUT_1_S) 179 #define AES_TEXT_OUT_1_V 0xFFFFFFFFU 180 #define AES_TEXT_OUT_1_S 0 181 182 /** AES_TEXT_OUT_2_REG register 183 * result text material text_out_2 configure register 184 */ 185 #define AES_TEXT_OUT_2_REG (DR_REG_AES_BASE + 0x38) 186 /** AES_TEXT_OUT_2 : R/W; bitpos: [31:0]; default: 0; 187 * This bits stores text_out_2 that is a part of result text material. 188 */ 189 #define AES_TEXT_OUT_2 0xFFFFFFFFU 190 #define AES_TEXT_OUT_2_M (AES_TEXT_OUT_2_V << AES_TEXT_OUT_2_S) 191 #define AES_TEXT_OUT_2_V 0xFFFFFFFFU 192 #define AES_TEXT_OUT_2_S 0 193 194 /** AES_TEXT_OUT_3_REG register 195 * result text material text_out_3 configure register 196 */ 197 #define AES_TEXT_OUT_3_REG (DR_REG_AES_BASE + 0x3c) 198 /** AES_TEXT_OUT_3 : R/W; bitpos: [31:0]; default: 0; 199 * This bits stores text_out_3 that is a part of result text material. 200 */ 201 #define AES_TEXT_OUT_3 0xFFFFFFFFU 202 #define AES_TEXT_OUT_3_M (AES_TEXT_OUT_3_V << AES_TEXT_OUT_3_S) 203 #define AES_TEXT_OUT_3_V 0xFFFFFFFFU 204 #define AES_TEXT_OUT_3_S 0 205 206 /** AES_MODE_REG register 207 * AES Mode register 208 */ 209 #define AES_MODE_REG (DR_REG_AES_BASE + 0x40) 210 /** AES_MODE : R/W; bitpos: [2:0]; default: 0; 211 * This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1: 212 * AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256. 213 */ 214 #define AES_MODE 0x00000007U 215 #define AES_MODE_M (AES_MODE_V << AES_MODE_S) 216 #define AES_MODE_V 0x00000007U 217 #define AES_MODE_S 0 218 219 /** AES_ENDIAN_REG register 220 * AES Endian configure register 221 */ 222 #define AES_ENDIAN_REG (DR_REG_AES_BASE + 0x44) 223 /** AES_ENDIAN : R/W; bitpos: [5:0]; default: 0; 224 * endian. [1:0] key endian, [3:2] text_in endian or in_stream endian, [5:4] text_out 225 * endian or out_stream endian 226 */ 227 #define AES_ENDIAN 0x0000003FU 228 #define AES_ENDIAN_M (AES_ENDIAN_V << AES_ENDIAN_S) 229 #define AES_ENDIAN_V 0x0000003FU 230 #define AES_ENDIAN_S 0 231 232 /** AES_TRIGGER_REG register 233 * AES trigger register 234 */ 235 #define AES_TRIGGER_REG (DR_REG_AES_BASE + 0x48) 236 /** AES_TRIGGER : WT; bitpos: [0]; default: 0; 237 * Set this bit to start AES calculation. 238 */ 239 #define AES_TRIGGER (BIT(0)) 240 #define AES_TRIGGER_M (AES_TRIGGER_V << AES_TRIGGER_S) 241 #define AES_TRIGGER_V 0x00000001U 242 #define AES_TRIGGER_S 0 243 244 /** AES_STATE_REG register 245 * AES state register 246 */ 247 #define AES_STATE_REG (DR_REG_AES_BASE + 0x4c) 248 /** AES_STATE : RO; bitpos: [1:0]; default: 0; 249 * Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: 250 * idle, 1: busy, 2: calculation_done. 251 */ 252 #define AES_STATE 0x00000003U 253 #define AES_STATE_M (AES_STATE_V << AES_STATE_S) 254 #define AES_STATE_V 0x00000003U 255 #define AES_STATE_S 0 256 257 /** AES_IV_MEM register 258 * The memory that stores initialization vector 259 */ 260 #define AES_IV_MEM (DR_REG_AES_BASE + 0x50) 261 #define AES_IV_MEM_SIZE_BYTES 16 262 263 /** AES_H_MEM register 264 * The memory that stores GCM hash subkey 265 */ 266 #define AES_H_MEM (DR_REG_AES_BASE + 0x60) 267 #define AES_H_MEM_SIZE_BYTES 16 268 269 /** AES_J0_MEM register 270 * The memory that stores J0 271 */ 272 #define AES_J0_MEM (DR_REG_AES_BASE + 0x70) 273 #define AES_J0_MEM_SIZE_BYTES 16 274 275 /** AES_T0_MEM register 276 * The memory that stores T0 277 */ 278 #define AES_T0_MEM (DR_REG_AES_BASE + 0x80) 279 #define AES_T0_MEM_SIZE_BYTES 16 280 281 /** AES_DMA_ENABLE_REG register 282 * DMA-AES working mode register 283 */ 284 #define AES_DMA_ENABLE_REG (DR_REG_AES_BASE + 0x90) 285 /** AES_DMA_ENABLE : R/W; bitpos: [0]; default: 0; 286 * 1'b0: typical AES working mode, 1'b1: DMA-AES working mode. 287 */ 288 #define AES_DMA_ENABLE (BIT(0)) 289 #define AES_DMA_ENABLE_M (AES_DMA_ENABLE_V << AES_DMA_ENABLE_S) 290 #define AES_DMA_ENABLE_V 0x00000001U 291 #define AES_DMA_ENABLE_S 0 292 293 /** AES_BLOCK_MODE_REG register 294 * AES cipher block mode register 295 */ 296 #define AES_BLOCK_MODE_REG (DR_REG_AES_BASE + 0x94) 297 /** AES_BLOCK_MODE : R/W; bitpos: [2:0]; default: 0; 298 * Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, 299 * 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved. 300 */ 301 #define AES_BLOCK_MODE 0x00000007U 302 #define AES_BLOCK_MODE_M (AES_BLOCK_MODE_V << AES_BLOCK_MODE_S) 303 #define AES_BLOCK_MODE_V 0x00000007U 304 #define AES_BLOCK_MODE_S 0 305 306 /** AES_BLOCK_NUM_REG register 307 * AES block number register 308 */ 309 #define AES_BLOCK_NUM_REG (DR_REG_AES_BASE + 0x98) 310 /** AES_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0; 311 * Those bits stores the number of Plaintext/ciphertext block. 312 */ 313 #define AES_BLOCK_NUM 0xFFFFFFFFU 314 #define AES_BLOCK_NUM_M (AES_BLOCK_NUM_V << AES_BLOCK_NUM_S) 315 #define AES_BLOCK_NUM_V 0xFFFFFFFFU 316 #define AES_BLOCK_NUM_S 0 317 318 /** AES_INC_SEL_REG register 319 * Standard incrementing function configure register 320 */ 321 #define AES_INC_SEL_REG (DR_REG_AES_BASE + 0x9c) 322 /** AES_INC_SEL : R/W; bitpos: [0]; default: 0; 323 * This bit decides the standard incrementing function. 0: INC32. 1: INC128. 324 */ 325 #define AES_INC_SEL (BIT(0)) 326 #define AES_INC_SEL_M (AES_INC_SEL_V << AES_INC_SEL_S) 327 #define AES_INC_SEL_V 0x00000001U 328 #define AES_INC_SEL_S 0 329 330 /** AES_AAD_BLOCK_NUM_REG register 331 * Additional Authential Data block number register 332 */ 333 #define AES_AAD_BLOCK_NUM_REG (DR_REG_AES_BASE + 0xa0) 334 /** AES_AAD_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0; 335 * Those bits stores the number of AAD block. 336 */ 337 #define AES_AAD_BLOCK_NUM 0xFFFFFFFFU 338 #define AES_AAD_BLOCK_NUM_M (AES_AAD_BLOCK_NUM_V << AES_AAD_BLOCK_NUM_S) 339 #define AES_AAD_BLOCK_NUM_V 0xFFFFFFFFU 340 #define AES_AAD_BLOCK_NUM_S 0 341 342 /** AES_REMAINDER_BIT_NUM_REG register 343 * AES remainder bit number register 344 */ 345 #define AES_REMAINDER_BIT_NUM_REG (DR_REG_AES_BASE + 0xa4) 346 /** AES_REMAINDER_BIT_NUM : R/W; bitpos: [6:0]; default: 0; 347 * Those bits stores the number of remainder bit. 348 */ 349 #define AES_REMAINDER_BIT_NUM 0x0000007FU 350 #define AES_REMAINDER_BIT_NUM_M (AES_REMAINDER_BIT_NUM_V << AES_REMAINDER_BIT_NUM_S) 351 #define AES_REMAINDER_BIT_NUM_V 0x0000007FU 352 #define AES_REMAINDER_BIT_NUM_S 0 353 354 /** AES_CONTINUE_REG register 355 * AES continue register 356 */ 357 #define AES_CONTINUE_REG (DR_REG_AES_BASE + 0xa8) 358 /** AES_CONTINUE : WT; bitpos: [0]; default: 0; 359 * Set this bit to continue GCM operation. 360 */ 361 #define AES_CONTINUE (BIT(0)) 362 #define AES_CONTINUE_M (AES_CONTINUE_V << AES_CONTINUE_S) 363 #define AES_CONTINUE_V 0x00000001U 364 #define AES_CONTINUE_S 0 365 366 /** AES_INT_CLEAR_REG register 367 * AES Interrupt clear register 368 */ 369 #define AES_INT_CLEAR_REG (DR_REG_AES_BASE + 0xac) 370 /** AES_INT_CLEAR : WT; bitpos: [0]; default: 0; 371 * Set this bit to clear the AES interrupt. 372 */ 373 #define AES_INT_CLEAR (BIT(0)) 374 #define AES_INT_CLEAR_M (AES_INT_CLEAR_V << AES_INT_CLEAR_S) 375 #define AES_INT_CLEAR_V 0x00000001U 376 #define AES_INT_CLEAR_S 0 377 378 /** AES_INT_ENA_REG register 379 * AES Interrupt enable register 380 */ 381 #define AES_INT_ENA_REG (DR_REG_AES_BASE + 0xb0) 382 /** AES_INT_ENA : R/W; bitpos: [0]; default: 0; 383 * Set this bit to enable interrupt that occurs when DMA-AES calculation is done. 384 */ 385 #define AES_INT_ENA (BIT(0)) 386 #define AES_INT_ENA_M (AES_INT_ENA_V << AES_INT_ENA_S) 387 #define AES_INT_ENA_V 0x00000001U 388 #define AES_INT_ENA_S 0 389 390 /** AES_DATE_REG register 391 * AES version control register 392 */ 393 #define AES_DATE_REG (DR_REG_AES_BASE + 0xb4) 394 /** AES_DATE : R/W; bitpos: [29:0]; default: 538513936; 395 * This bits stores the version information of AES. 396 */ 397 #define AES_DATE 0x3FFFFFFFU 398 #define AES_DATE_M (AES_DATE_V << AES_DATE_S) 399 #define AES_DATE_V 0x3FFFFFFFU 400 #define AES_DATE_S 0 401 402 /** AES_DMA_EXIT_REG register 403 * AES-DMA exit config 404 */ 405 #define AES_DMA_EXIT_REG (DR_REG_AES_BASE + 0xb8) 406 /** AES_DMA_EXIT : WT; bitpos: [0]; default: 0; 407 * Set this register to leave calculation done stage. Recommend to use it after 408 * software finishes reading DMA's output buffer. 409 */ 410 #define AES_DMA_EXIT (BIT(0)) 411 #define AES_DMA_EXIT_M (AES_DMA_EXIT_V << AES_DMA_EXIT_S) 412 #define AES_DMA_EXIT_V 0x00000001U 413 #define AES_DMA_EXIT_S 0 414 415 #ifdef __cplusplus 416 } 417 #endif 418
