1 /*
2  * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #ifndef __HWCRYPTO_REG_H__
8 #define __HWCRYPTO_REG_H__
9 
10 #include "soc.h"
11 
12 /* registers for RSA acceleration via Multiple Precision Integer ops */
13 #define RSA_MEM_M_BLOCK_BASE          ((DR_REG_RSA_BASE)+0x000)
14 /* RB & Z use the same memory block, depending on phase of operation */
15 #define RSA_MEM_RB_BLOCK_BASE         ((DR_REG_RSA_BASE)+0x200)
16 #define RSA_MEM_Z_BLOCK_BASE          ((DR_REG_RSA_BASE)+0x200)
17 #define RSA_MEM_Y_BLOCK_BASE          ((DR_REG_RSA_BASE)+0x400)
18 #define RSA_MEM_X_BLOCK_BASE          ((DR_REG_RSA_BASE)+0x600)
19 
20 /* Configuration registers */
21 #define RSA_M_DASH_REG                (DR_REG_RSA_BASE + 0x800)
22 #define RSA_LENGTH_REG                (DR_REG_RSA_BASE + 0x804)
23 #define RSA_CONSTANT_TIME_REG         (DR_REG_RSA_BASE + 0x820)
24 #define RSA_SEARCH_ENABLE_REG         (DR_REG_RSA_BASE + 0x824)
25 #define RSA_SEARCH_POS_REG            (DR_REG_RSA_BASE + 0x828)
26 
27 /* Initialization registers */
28 #define RSA_QUERY_CLEAN_REG           (DR_REG_RSA_BASE + 0x808)
29 
30 /* Calculation start registers */
31 #define RSA_MODEXP_START_REG          (DR_REG_RSA_BASE + 0x80c)
32 #define RSA_MOD_MULT_START_REG        (DR_REG_RSA_BASE + 0x810)
33 #define RSA_MULT_START_REG            (DR_REG_RSA_BASE + 0x814)
34 
35 /* Interrupt registers */
36 #define RSA_QUERY_INTERRUPT_REG       (DR_REG_RSA_BASE + 0x818)
37 #define RSA_CLEAR_INTERRUPT_REG       (DR_REG_RSA_BASE + 0x81C)
38 #define RSA_INTERRUPT_REG             (DR_REG_RSA_BASE + 0x82C)
39 #define RSA_DATE_REG                  (DR_REG_RSA_BASE + 0x82C)
40 
41 #define SHA_MODE_SHA1       0
42 #define SHA_MODE_SHA224     1
43 #define SHA_MODE_SHA256     2
44 
45 /* SHA acceleration registers */
46 #define SHA_MODE_REG                  ((DR_REG_SHA_BASE) + 0x00)
47 #define SHA_BLOCK_NUM_REG             ((DR_REG_SHA_BASE) + 0x0C)
48 #define SHA_START_REG                 ((DR_REG_SHA_BASE) + 0x10)
49 #define SHA_CONTINUE_REG              ((DR_REG_SHA_BASE) + 0x14)
50 #define SHA_BUSY_REG                  ((DR_REG_SHA_BASE) + 0x18)
51 #define SHA_DMA_START_REG             ((DR_REG_SHA_BASE) + 0x1C)
52 #define SHA_DMA_CONTINUE_REG          ((DR_REG_SHA_BASE) + 0x20)
53 #define SHA_CLEAR_IRQ_REG             ((DR_REG_SHA_BASE) + 0x24)
54 #define SHA_INT_ENA_REG               ((DR_REG_SHA_BASE) + 0x28)
55 #define SHA_DATE_REG                  ((DR_REG_SHA_BASE) + 0x2C)
56 
57 #define SHA_H_BASE                    ((DR_REG_SHA_BASE) + 0x40)
58 #define SHA_TEXT_BASE                 ((DR_REG_SHA_BASE) + 0x80)
59 
60 /* AES Block operation modes */
61 #define AES_BLOCK_MODE_ECB     0
62 #define AES_BLOCK_MODE_CBC     1
63 #define AES_BLOCK_MODE_OFB     2
64 #define AES_BLOCK_MODE_CTR     3
65 #define AES_BLOCK_MODE_CFB8    4
66 #define AES_BLOCK_MODE_CFB128  5
67 
68 /* AES Block operation modes (used with DMA) */
69 #define AES_BLOCK_MODE_ECB     0
70 #define AES_BLOCK_MODE_CBC     1
71 #define AES_BLOCK_MODE_OFB     2
72 #define AES_BLOCK_MODE_CTR     3
73 #define AES_BLOCK_MODE_CFB8    4
74 #define AES_BLOCK_MODE_CFB128  5
75 
76 /* AES acceleration registers */
77 #define AES_MODE_REG            ((DR_REG_AES_BASE) + 0x40)
78 #define AES_ENDIAN_REG          ((DR_REG_AES_BASE) + 0x44)
79 #define AES_TRIGGER_REG         ((DR_REG_AES_BASE) + 0x48)
80 #define AES_STATE_REG           ((DR_REG_AES_BASE) + 0x4c)
81 #define AES_DMA_ENABLE_REG      ((DR_REG_AES_BASE) + 0x90)
82 #define AES_BLOCK_MODE_REG      ((DR_REG_AES_BASE) + 0x94)
83 #define AES_BLOCK_NUM_REG       ((DR_REG_AES_BASE) + 0x98)
84 #define AES_INC_SEL_REG         ((DR_REG_AES_BASE) + 0x9C)
85 #define AES_AAD_BLOCK_NUM_REG   ((DR_REG_AES_BASE) + 0xA0)
86 #define AES_BIT_VALID_NUM_REG   ((DR_REG_AES_BASE) + 0xA4)
87 #define AES_CONTINUE_REG        ((DR_REG_AES_BASE) + 0xA8)
88 #define AES_INT_CLEAR_REG       ((DR_REG_AES_BASE) + 0xAC)
89 #define AES_INT_ENA_REG         ((DR_REG_AES_BASE) + 0xB0)
90 #define AES_DATE_REG            ((DR_REG_AES_BASE) + 0xB4)
91 #define AES_DMA_EXIT_REG        ((DR_REG_AES_BASE) + 0xB8)
92 
93 #define AES_DMA_ENABLE_REG      ((DR_REG_AES_BASE) + 0x90)
94 #define AES_BLOCK_MODE_REG      ((DR_REG_AES_BASE) + 0x94)
95 #define AES_BLOCK_NUM_REG       ((DR_REG_AES_BASE) + 0x98)
96 #define AES_INC_SEL_REG         ((DR_REG_AES_BASE) + 0x9C)
97 #define AES_AAD_BLOCK_NUM_REG   ((DR_REG_AES_BASE) + 0xA0)
98 #define AES_BIT_VALID_NUM_REG   ((DR_REG_AES_BASE) + 0xA4)
99 #define AES_CONTINUE_REG        ((DR_REG_AES_BASE) + 0xA8)
100 
101 #define AES_KEY_BASE            ((DR_REG_AES_BASE) + 0x00)
102 #define AES_TEXT_IN_BASE        ((DR_REG_AES_BASE) + 0x20)
103 #define AES_TEXT_OUT_BASE       ((DR_REG_AES_BASE) + 0x30)
104 #define AES_IV_BASE             ((DR_REG_AES_BASE) + 0x50)
105 #define AES_H_BASE              ((DR_REG_AES_BASE) + 0x60)
106 #define AES_J_BASE              ((DR_REG_AES_BASE) + 0x70)
107 #define AES_T_BASE              ((DR_REG_AES_BASE) + 0x80)
108 
109 /* AES_STATE_REG values */
110 #define AES_STATE_IDLE 0
111 #define AES_STATE_BUSY 1
112 #define AES_STATE_DONE 2
113 
114 /* HMAC Module */
115 #define HMAC_SET_START_REG             ((DR_REG_HMAC_BASE) + 0x40)
116 #define HMAC_SET_PARA_PURPOSE_REG      ((DR_REG_HMAC_BASE) + 0x44)
117 #define HMAC_SET_PARA_KEY_REG          ((DR_REG_HMAC_BASE) + 0x48)
118 #define HMAC_SET_PARA_FINISH_REG       ((DR_REG_HMAC_BASE) + 0x4c)
119 #define HMAC_SET_MESSAGE_ONE_REG       ((DR_REG_HMAC_BASE) + 0x50)
120 #define HMAC_SET_MESSAGE_ING_REG       ((DR_REG_HMAC_BASE) + 0x54)
121 #define HMAC_SET_MESSAGE_END_REG       ((DR_REG_HMAC_BASE) + 0x58)
122 #define HMAC_SET_RESULT_FINISH_REG     ((DR_REG_HMAC_BASE) + 0x5c)
123 #define HMAC_SET_INVALIDATE_JTAG_REG   ((DR_REG_HMAC_BASE) + 0x60)
124 #define HMAC_INVALIDATE_JTAG           BIT(0)
125 #define HMAC_SET_INVALIDATE_DS_REG     ((DR_REG_HMAC_BASE) + 0x64)
126 #define HMAC_QUERY_ERROR_REG           ((DR_REG_HMAC_BASE) + 0x68)
127 #define HMAC_QUERY_BUSY_REG            ((DR_REG_HMAC_BASE) + 0x6c)
128 
129 #define HMAC_WDATA_BASE                ((DR_REG_HMAC_BASE) + 0x80)
130 #define HMAC_RDATA_BASE                ((DR_REG_HMAC_BASE) + 0xC0)
131 #define HMAC_SET_MESSAGE_PAD_REG       ((DR_REG_HMAC_BASE) + 0xF0)
132 #define HMAC_ONE_BLOCK_REG             ((DR_REG_HMAC_BASE) + 0xF4)
133 
134 #define HMAC_SOFT_JTAG_CTRL_REG        ((DR_REG_HMAC_BASE) + 0xF8)
135 #define HMAC_WR_JTAG_REG               ((DR_REG_HMAC_BASE) + 0xFC)
136 
137 #define HMAC_DATE_REG                  ((DR_REG_HMAC_BASE) + 0xF8)
138 
139 
140 /* AES-XTS registers */
141 #define AES_XTS_PLAIN_BASE        ((DR_REG_AES_XTS_BASE) + 0x00)
142 #define AES_XTS_SIZE_REG          ((DR_REG_AES_XTS_BASE) + 0x40)
143 #define AES_XTS_DESTINATION_REG   ((DR_REG_AES_XTS_BASE) + 0x44)
144 #define AES_XTS_PHYSICAL_ADDR_REG ((DR_REG_AES_XTS_BASE) + 0x48)
145 
146 #define AES_XTS_TRIGGER_REG       ((DR_REG_AES_XTS_BASE) + 0x4C)
147 #define AES_XTS_RELEASE_REG       ((DR_REG_AES_XTS_BASE) + 0x50)
148 #define AES_XTS_DESTROY_REG       ((DR_REG_AES_XTS_BASE) + 0x54)
149 #define AES_XTS_STATE_REG         ((DR_REG_AES_XTS_BASE) + 0x58)
150 #define AES_XTS_DATE_REG          ((DR_REG_AES_XTS_BASE) + 0x5C)
151 
152 /* Digital Signature registers and memory blocks */
153 #define DS_C_BASE                 ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x000 )
154 #define DS_C_Y_BASE               ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x000 )
155 #define DS_C_M_BASE               ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x200 )
156 #define DS_C_RB_BASE              ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x400 )
157 #define DS_C_BOX_BASE             ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x600 )
158 #define DS_IV_BASE                ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x630 )
159 #define DS_X_BASE                 ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x800 )
160 #define DS_Z_BASE                 ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xA00 )
161 
162 #define DS_SET_START_REG          ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE00)
163 #define DS_SET_ME_REG             ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE04)
164 #define DS_SET_FINISH_REG         ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE08)
165 
166 #define DS_QUERY_BUSY_REG         ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE0C)
167 #define DS_QUERY_KEY_WRONG_REG    ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE10)
168 #define DS_QUERY_CHECK_REG        ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE14)
169 
170 #define DS_QUERY_CHECK_INVALID_DIGEST  (1<<0)
171 #define DS_QUERY_CHECK_INVALID_PADDING (1<<1)
172 
173 #define DS_DATE_REG               ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE20)
174 
175 #endif
176