Searched refs:CACHE_LL_L1_ACCESS_EVENT_MASK (Results 1 – 10 of 10) sorted by relevance
| /hal_espressif-latest/components/esp_system/port/soc/esp32s3/ |
| D | cache_err_int.c | 57 …_DRAM_LOGV(TAG, "core 0 access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK); in esp_cache_err_int_init()
58 cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); in esp_cache_err_int_init()
59 cache_ll_l1_enable_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); in esp_cache_err_int_init()
65 …_DRAM_LOGV(TAG, "core 1 access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK); in esp_cache_err_int_init()
66 cache_ll_l1_clear_access_error_intr(1, CACHE_LL_L1_ACCESS_EVENT_MASK); in esp_cache_err_int_init()
67 cache_ll_l1_enable_access_error_intr(1, CACHE_LL_L1_ACCESS_EVENT_MASK); in esp_cache_err_int_init()
75 if (cache_ll_l1_get_access_error_intr_status(0, CACHE_LL_L1_ACCESS_EVENT_MASK)) { in esp_cache_err_get_cpuid()
79 if (cache_ll_l1_get_access_error_intr_status(1, CACHE_LL_L1_ACCESS_EVENT_MASK)) { in esp_cache_err_get_cpuid()
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| /hal_espressif-latest/components/esp_system/port/soc/esp32c6/ |
| D | cache_err_int.c | 45 ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK); in esp_cache_err_int_init()
47 cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); in esp_cache_err_int_init()
49 cache_ll_l1_enable_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); in esp_cache_err_int_init()
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| /hal_espressif-latest/components/esp_system/port/soc/esp32h2/ |
| D | cache_err_int.c | 45 ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK); in esp_cache_err_int_init()
47 cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); in esp_cache_err_int_init()
49 cache_ll_l1_enable_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); in esp_cache_err_int_init()
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| /hal_espressif-latest/components/esp_system/port/soc/esp32c2/ |
| D | cache_err_int.c | 59 ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK); in esp_cache_err_int_init()
61 cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); in esp_cache_err_int_init()
63 cache_ll_l1_enable_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); in esp_cache_err_int_init()
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| /hal_espressif-latest/components/esp_system/port/soc/esp32c3/ |
| D | cache_err_int.c | 59 ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK); in esp_cache_err_int_init()
61 cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); in esp_cache_err_int_init()
63 cache_ll_l1_enable_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); in esp_cache_err_int_init()
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| /hal_espressif-latest/components/hal/esp32h2/include/hal/ |
| D | cache_ll.h | 24 #define CACHE_LL_L1_ACCESS_EVENT_MASK (1<<4) macro
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| /hal_espressif-latest/components/hal/esp32c6/include/hal/ |
| D | cache_ll.h | 24 #define CACHE_LL_L1_ACCESS_EVENT_MASK (1<<4) macro
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| /hal_espressif-latest/components/hal/esp32c2/include/hal/ |
| D | cache_ll.h | 25 #define CACHE_LL_L1_ACCESS_EVENT_MASK (0x3f) macro
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| /hal_espressif-latest/components/hal/esp32c3/include/hal/ |
| D | cache_ll.h | 25 #define CACHE_LL_L1_ACCESS_EVENT_MASK (0x3f) macro
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| /hal_espressif-latest/components/hal/esp32s3/include/hal/ |
| D | cache_ll.h | 26 #define CACHE_LL_L1_ACCESS_EVENT_MASK (0x1f) macro
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