1 /*
2  * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 /*
8  The cache has an interrupt that can be raised as soon as an access to a cached
9  region (flash) is done without the cache being enabled. We use that here
10  to panic the CPU, which from a debugging perspective is better than grabbing bad
11  data from the bus.
12 */
13 #include "esp_rom_sys.h"
14 #include "esp_attr.h"
15 #include "esp_log.h"
16 #include "esp_intr_alloc.h"
17 #include "soc/periph_defs.h"
18 #include "riscv/interrupt.h"
19 #include "hal/cache_ll.h"
20 
21 static const char *TAG = "CACHE_ERR";
22 
esp_cache_err_int_init(void)23 void esp_cache_err_int_init(void)
24 {
25     const uint32_t core_id = 0;
26 
27     /* Disable cache interrupts if enabled. */
28     ESP_INTR_DISABLE(ETS_CACHEERR_INUM);
29 
30     /**
31      *  Bind all cache errors to ETS_CACHEERR_INUM interrupt. we will deal with
32      * them in handler by different types
33      *
34      * On ESP32C6 boards, the cache is a shared one but buses are still
35      * distinct. So, we have an bus0 and a bus1 sharing the same cache.
36      * This error can occur if a bus performs a request but the cache
37      * is disabled.
38      */
39     esp_rom_route_intr_matrix(core_id, ETS_CACHE_INTR_SOURCE, ETS_CACHEERR_INUM);
40 
41     /* Set the type and priority to cache error interrupts. */
42     esprv_intc_int_set_type(ETS_CACHEERR_INUM, INTR_TYPE_LEVEL);
43     esprv_intc_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
44 
45     ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK);
46     /* On the hardware side, start by clearing all the bits reponsible for cache access error */
47     cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
48     /* Then enable cache access error interrupts. */
49     cache_ll_l1_enable_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
50 
51     /* Enable the interrupts for cache error. */
52     ESP_INTR_ENABLE(ETS_CACHEERR_INUM);
53 }
54 
esp_cache_err_get_cpuid(void)55 int esp_cache_err_get_cpuid(void)
56 {
57     return 0;
58 }
59