1 /*
2 * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 /*
8 The cache has an interrupt that can be raised as soon as an access to a cached
9 region (flash) is done without the cache being enabled. We use that here
10 to panic the CPU, which from a debugging perspective is better than grabbing bad
11 data from the bus.
12 */
13 #include "esp_rom_sys.h"
14 #include "esp_attr.h"
15 #include "esp_log.h"
16 #include "esp_intr_alloc.h"
17 #include "soc/periph_defs.h"
18 #include "riscv/interrupt.h"
19 #include "hal/cache_ll.h"
20
21 static const char *TAG = "CACHE_ERR";
22
esp_cache_err_int_init(void)23 void esp_cache_err_int_init(void)
24 {
25 const uint32_t core_id = 0;
26
27 /* Disable cache interrupts if enabled. */
28 ESP_INTR_DISABLE(ETS_CACHEERR_INUM);
29
30 /**
31 * Bind all cache errors to ETS_CACHEERR_INUM interrupt. we will deal with
32 * them in handler by different types
33 * I) Cache access error
34 * 1. dbus trying to write to icache
35 * 2. dbus authentication fail
36 * 3. cpu access icache while dbus is disabled [1]
37 * 4. ibus authentication fail
38 * 5. ibus trying to write icache
39 * 6. cpu access icache while ibus is disabled
40 * II) Cache illegal error
41 * 1. dbus counter overflow
42 * 2. ibus counter overflow
43 * 3. mmu entry fault
44 * 4. icache preload configurations fault
45 * 5. icache sync configuration fault
46 *
47 * [1]: On ESP32-C2 boards, the caches are shared but buses are still
48 * distinct. So, we have an ibus and a dbus sharing the same cache.
49 * This error can occur if the dbus performs a request but the icache
50 * (or simply cache) is disabled.
51 */
52 esp_rom_route_intr_matrix(core_id, ETS_CACHE_IA_INTR_SOURCE, ETS_CACHEERR_INUM);
53 esp_rom_route_intr_matrix(core_id, ETS_CACHE_CORE0_ACS_INTR_SOURCE, ETS_CACHEERR_INUM);
54
55 /* Set the type and priority to cache error interrupts. */
56 esprv_intc_int_set_type(ETS_CACHEERR_INUM, INTR_TYPE_LEVEL);
57 esprv_intc_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
58
59 ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK);
60 /* On the hardware side, start by clearing all the bits reponsible for cache access error */
61 cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
62 /* Then enable cache access error interrupts. */
63 cache_ll_l1_enable_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
64
65 /* Same goes for cache illegal error: start by clearing the bits and then
66 * set them back. */
67 ESP_DRAM_LOGV(TAG, "illegal error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ILG_EVENT_MASK);
68 cache_ll_l1_clear_illegal_error_intr(0, CACHE_LL_L1_ILG_EVENT_MASK);
69 cache_ll_l1_enable_illegal_error_intr(0, CACHE_LL_L1_ILG_EVENT_MASK);
70
71 /* Enable the interrupts for cache error. */
72 ESP_INTR_ENABLE(ETS_CACHEERR_INUM);
73 }
74
esp_cache_err_get_cpuid(void)75 int esp_cache_err_get_cpuid(void)
76 {
77 return 0;
78 }
79
