Searched refs:V (Results 1 – 25 of 514) sorted by relevance
12345678910>>...21
| /Zephyr-latest/samples/sensor/ina219/ |
| D | README.rst | 22 The supply voltage of the INA219 can be in the 3V to 5.5V range.
23 The common mode voltage of the measured bus can be in the 0V to 26V range.
35 When monitoring a 3.3 V bus with a 0.1 Ohm shunt resistor
40 Shunt: 0.001570 [V] -- Bus: 3.224000 [V] -- Power: 0.504000 [W] -- Current: 0.157000 [A]
47 Shunt: -0.001560 [V] -- Bus: 3.224000 [V] -- Power: 0.502000 [W] -- Current: -0.156000 [A]
|
| /Zephyr-latest/samples/shields/npm1300_ek/doc/ |
| D | index.rst | 49 1.000 V
50 1.100 V
62 # set BUCK2 voltage to exactly 2V
63 regulator vset BUCK2 2V
66 1.800 V
67 # set BUCK1 voltage to a value between 2.35V and 2.45V
68 regulator set BUCK1 2.35V 2.45V
71 2.400 V
|
| /Zephyr-latest/boards/microchip/m2gl025_miv/support/ |
| D | m2gl025_miv.resc | 1 :name: Mi-V
2 :description: This script is prepared to run Zephyr on a Mi-V RISC-V board.
4 $name?="Mi-V"
|
| /Zephyr-latest/boards/intel/niosv_g/doc/ |
| D | index.rst | 9 niosv_g board is based on Intel FPGA Design Store Nios® V/g Hello World Example Design system and t…
13 Nios® V/g Processor Intel® FPGA IP
17 Nios® V/g hello world example design system
20 Prebuilt Nios® V/g hello world example design system is available in Intel FPGA Design store.
23 For example, Arria10 Nios® V/g processor example design system prebuilt files can be downloaded fro…
28 Create Nios® V/g processor example design system in FPGA
31 Please use Intel Quartus Programmer tool to program Nios® V/g processor based system into the FPGA …
33 In order to create the Nios® V/g processor inside the FPGA device, please download the generated .s…
44 top.sof is referring to Nios® V/m processor based system SRAM Object File.
49 …inkable Format .elf file, please use the niosv-download command within Nios V Command Shell enviro…
[all …]
|
| /Zephyr-latest/boards/intel/niosv_m/doc/ |
| D | index.rst | 9 niosv_m board is based on Intel FPGA Design Store Nios® V/m Hello World Example Design system and t…
13 Nios® V/m Processor Intel® FPGA IP
17 Nios® V/m hello world example design system
20 Prebuilt Nios® V/m hello world example design system is available in Intel FPGA Design store.
23 For example, Arria10 Nios® V/m processor example design system prebuilt files can be downloaded fro…
28 Create Nios® V/m processor example design system in FPGA
31 Please use Intel Quartus Programmer tool to program Nios® V/m processor based system into the FPGA …
33 In order to create the Nios® V/m processor inside the FPGA device, please download the generated .s…
44 top.sof is referring to Nios® V/m processor based system SRAM Object File.
49 …inkable Format .elf file, please use the niosv-download command within Nios V Command Shell enviro…
[all …]
|
| /Zephyr-latest/boards/sparkfun/red_v_things_plus/doc/ |
| D | index.rst | 3 SparkFun RED-V Things Plus
9 The SparkFun RED-V Things Plus is a development board with
10 a SiFive FE310-G002 RISC-V SoC.
14 :alt: SparkFun RED-V Things Plus board
16 For more information about the SparkFun RED-V Things Plus and SiFive FE310-G002:
18 - `SparkFun RED-V Things Plus Website`_
38 The SparkFun RED-V Things Plus uses Segger J-Link OB for flashing and debugging.
57 .. _SparkFun RED-V Things Plus Website:
|
| /Zephyr-latest/drivers/serial/ |
| D | Kconfig.miv | 1 # Mi-V UART configuration option
7 bool "Mi-V serial driver"
12 This option enables the Mi-V serial driver.
|
| /Zephyr-latest/soc/altr/zephyr_nios2f/cpu/ |
| D | ghrd_10m50da.qsf | 180 set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL" -to clk_ddr3_100_p
181 set_instance_assignment -name IO_STANDARD "2.5 V" -to clk_50_max10
182 set_instance_assignment -name IO_STANDARD "2.5 V" -to clk_25_max10
184 set_instance_assignment -name IO_STANDARD "2.5 V" -to clk_10_adc
185 set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to fpga_resetn
186 set_instance_assignment -name IO_STANDARD "1.5 V" -to user_led[0]
187 set_instance_assignment -name IO_STANDARD "1.5 V" -to user_led[1]
188 set_instance_assignment -name IO_STANDARD "1.5 V" -to user_led[2]
189 set_instance_assignment -name IO_STANDARD "1.5 V" -to user_led[3]
190 set_instance_assignment -name IO_STANDARD "1.5 V" -to user_led[4]
[all …]
|
| /Zephyr-latest/samples/sensor/ccs811/ |
| D | README.rst | 48 Voltage: 0.000000V; Current: 0.000000A
53 Voltage: 0.000000V; Current: 0.000000A
61 Voltage: 0.677040V; Current: 0.000014A
66 Voltage: 0.675428V; Current: 0.000014A
71 Voltage: 0.677040V; Current: 0.000014A
76 Voltage: 0.677040V; Current: 0.000014A
81 Voltage: 0.677040V; Current: 0.000014A
86 Voltage: 0.677040V; Current: 0.000014A
|
| /Zephyr-latest/samples/sensor/max17262/ |
| D | README.rst | 51 V: 3.626406 V; I: -3.437500 mA; T: 28.011718 °C
52 V: 3.626406 V; I: -3.437500 mA; T: 28.011718 °C
53 V: 3.626406 V; I: -3.437500 mA; T: 28.011718 °C
|
| /Zephyr-latest/boards/shields/arduino_uno_click/ |
| D | arduino_uno_click.overlay | 19 /* +3.3V */
27 /* +5V */
42 /* +3.3V */
50 /* +5V */
|
| /Zephyr-latest/boards/adi/apard32690/doc/ |
| D | index.rst | 32 - TBDμW/MHz Executing from Cache at 1.1V
33 - 1.8V and 3.3V I/O with No Level Translators
38 …- Dedicated, Ultra-Low-Power, 32-Bit RISC-V Coprocessor to Offload Timing-Critical Bluetooth Proce…
80 - On-Board 5V, 3.3V, 1.8V, and 1.1V voltage regulators
81 - 2-Pin external power supply terminal block (5V - 28V DC)
139 | | | | 1-2 | | | Connects the SWD Vcc pin to 3.3V. …
141 | | | | 2-3 | | | Connects the SWD Vcc pin to 1.8V. …
160 | | | | On | | | Pulls the ADIN1110's SWPD_EN pin to 3.3V through a…
167 | | | | On | | | Pulls the ADIN1110's CFG0 pin to 3.3V through a re…
174 | | | | On | | | Pulls the ADIN1110's CFG1 pin to 3.3V through a re…
[all …]
|
| /Zephyr-latest/boards/shields/ftdi_vm800c/doc/ |
| D | index.rst | 56 | | 3.3V | POWER +3.3V |
58 | | 5V | POWER +5.0V or +3.3V |
|
| /Zephyr-latest/boards/olimex/stm32_e407/doc/ |
| D | index.rst | 71 | 1 | +3.3V | 11 | - |
73 | 2 | +3.3V | 12 | GND |
97 | 1 | +3.3V | - |
130 | 5V | VDD (5V) | N/A |
206 | 1 | +3.3V | 11 | PD8 |
222 | 9 | PD6 | 19 | +5V |
232 | 1 | +3.3V | 11 | PE8 |
248 | 9 | PE6/D5 | 19 | +5V |
258 | 1 | +3.3V | 11 | PF8/A3 |
274 | 9 | PF6/A1 | 19 | +5V |
[all …]
|
| /Zephyr-latest/boards/olimex/stm32_h407/doc/ |
| D | index.rst | 73 | 1 | +3.3V | 11 | - |
75 | 2 | +3.3V | 12 | GND |
99 | 1 | +3.3V | - |
132 | 5V | VDD (5V) | N/A |
208 | 1 | +3.3V | 11 | PD8 |
224 | 9 | PD6 | 19 | +5V |
234 | 1 | +3.3V | 11 | PE8 |
250 | 9 | PE6 | 19 | +5V |
260 | 1 | +3.3V | 11 | PF8 |
276 | 9 | PF6 | 19 | +5V |
[all …]
|
| /Zephyr-latest/soc/neorv32/ |
| D | Kconfig | 19 # NEORV32 RISC-V ISA A extension implements only LR/SC, not AMO
31 bool "RISC-V ISA Extension \"C\""
34 Enable this if the NEORV32 CPU implementation supports the RISC-V ISA
|
| /Zephyr-latest/soc/intel/intel_socfpga_std/cyclonev/ |
| D | Kconfig.soc | 8 Intel SoC FPGA Cyclone V Series
17 Intel SoC FPGA Cyclone V
|
| /Zephyr-latest/boards/ite/it8xxx2_evb/support/ |
| D | it8xxx2_evb.resc | 2 :description: This script is prepared to run Zephyr on a Mi-V RISC-V board.
|
| /Zephyr-latest/soc/microchip/miv/miv/ |
| D | Kconfig.soc | 10 Microchip Mi-V implementation#
16 Microchip Mi-V system implementation
|
| /Zephyr-latest/samples/sensor/sgp40_sht4x/ |
| D | Kconfig | 31 0 -> High power heater pulse -> ~200 mW @3.3V
32 1 -> Medium power heater pulse -> ~110 mW @3.3V
33 2 -> Low power heater pulse -> ~20 mW @3.3V
|
| /Zephyr-latest/samples/drivers/adc/adc_dt/boards/ |
| D | mimxrt685_evk_mimxrt685s_cm33.overlay | 23 * - Connect VREF_L to GND, and VREF_H to 1.8V (connect JP9 and JP10).
24 * - Connect LPADC0 CH0A signal to voltage between 0~1.8V (J30 pin 1)
25 * - Connect LPADC0 CH0B signal to voltage between 0~1.8V (J30 pin 2)
|
| /Zephyr-latest/soc/st/stm32/ |
| D | Kconfig | 72 bool "SMPS 1.8V supplies LDO (no external supply)"
76 bool "SMPS 2.5V supplies LDO (no external supply)"
80 bool "External SMPS 1.8V supply, supplies LDO"
84 bool "External SMPS 2.5V supply, supplies LDO"
88 bool "External SMPS 1.8V supply and bypass"
92 bool "External SMPS 2.5V supply and bypass"
|
| /Zephyr-latest/scripts/coccinelle/ |
| D | int_ms_to_timeout.cocci | 105 expression V;
113 - V * MSEC_PER_SEC
114 + K_SECONDS(V)
119 - K_MSEC(V * MSEC_PER_SEC)
120 + K_SECONDS(V)
129 expression V;
135 | V * MSEC_PER_SEC
144 expression V;
150 | K_MSEC(V * MSEC_PER_SEC)
259 expression V;
[all …]
|
| /Zephyr-latest/boards/adi/max32670evkit/doc/ |
| D | index.rst | 30 - Ultra-Low 0.9V to 1.1V VCORE Supply Voltage
31 - Internal LDO Operation from 1.7V to 3.6V SingleSupply
46 - 44μA/MHz Active at 0.9V up to 12MHz
47 - 50μA/MHz Active at 1.1V up to 100MHz
48 - 2.6μA Full Memory Retention Power in BACKUPMode at VDD = 1.8V
49 - 350nA Ultra-Low-Power RTC at VDD = 1.8V
169 | | | | 1-2 | | | Sets output 2 of the SIMO regulator to 0.9V. …
171 | | | | 3-4 | | | Sets output 2 of the SIMO regulator to 1.0V. …
173 | | | | 5-6 | | | Sets output 2 of the SIMO regulator to 1.1V. …
|
| /Zephyr-latest/samples/drivers/adc/adc_sequence/boards/ |
| D | mimxrt595_evk_cm33.overlay | 22 * - Connect LPADC0 CH0A signal to voltage between 0~1.8V (J30 pin 1)
23 * - Connect LPADC0 CH0B signal to voltage between 0~1.8V (J30 pin 2)
25 * - Connect LPADC0 CH2A signal to voltage between 0~1.8V (J30 pin 3)
|
12345678910>>...21
