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Searched refs:REG_READ (Results 1 – 25 of 95) sorted by relevance

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/hal_espressif-3.6.0/components/esp_system/port/arch/xtensa/
Dpanic_arch.c176 status[0] = REG_READ(EXTMEM_CACHE_DBG_STATUS0_REG); in print_cache_err_details()
177 status[1] = REG_READ(EXTMEM_CACHE_DBG_STATUS1_REG); in print_cache_err_details()
181 vaddr = REG_READ(EXTMEM_PRO_ICACHE_MEM_SYNC0_REG); in print_cache_err_details()
182 size = REG_READ(EXTMEM_PRO_ICACHE_MEM_SYNC1_REG); in print_cache_err_details()
190 vaddr = REG_READ(EXTMEM_PRO_ICACHE_PRELOAD_ADDR_REG); in print_cache_err_details()
191 size = REG_READ(EXTMEM_PRO_ICACHE_PRELOAD_SIZE_REG); in print_cache_err_details()
199 vaddr = REG_READ(EXTMEM_PRO_ICACHE_REJECT_VADDR_REG); in print_cache_err_details()
203 if (REG_READ(EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_REG) & MMU_INVALID) { in print_cache_err_details()
213 vaddr = REG_READ(EXTMEM_PRO_DCACHE_MEM_SYNC0_REG); in print_cache_err_details()
214 size = REG_READ(EXTMEM_PRO_DCACHE_MEM_SYNC1_REG); in print_cache_err_details()
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/hal_espressif-3.6.0/components/esp_timer/src/
Desp_timer_impl_frc_legacy.c149 return ((REG_READ(FRC_TIMER_CTRL_REG(1)) & FRC_TIMER_INT_STATUS) != 0 && in timer_overflow_happened()
150 …((REG_READ(FRC_TIMER_ALARM_REG(1)) == ALARM_OVERFLOW_VAL && TIMER_IS_AFTER_OVERFLOW(REG_READ(FRC_T… in timer_overflow_happened()
151 …(!TIMER_IS_AFTER_OVERFLOW(REG_READ(FRC_TIMER_ALARM_REG(1))) && TIMER_IS_AFTER_OVERFLOW(REG_READ(FR… in timer_overflow_happened()
157 assert(TIMER_IS_AFTER_OVERFLOW(REG_READ(FRC_TIMER_COUNT_REG(1)))); in timer_count_reload()
166 REG_WRITE(FRC_TIMER_LOAD_REG(1), REG_READ(FRC_TIMER_COUNT_REG(1)) - ALARM_OVERFLOW_VAL); in timer_count_reload()
191 timer_val = REG_READ(FRC_TIMER_COUNT_REG(1)); in esp_timer_impl_get_time()
200 if (REG_READ(FRC_TIMER_COUNT_REG(1)) > timer_val && in esp_timer_impl_get_time()
231 ((REG_READ(FRC_TIMER_COUNT_REG(1)) > ALARM_OVERFLOW_VAL) &&
232 ((REG_READ(FRC_TIMER_CTRL_REG(1)) & FRC_TIMER_INT_STATUS) == 0))) {
239 int64_t cur_count = REG_READ(FRC_TIMER_COUNT_REG(1));
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Desp_timer_impl_lac.c135 uint32_t lo_start = REG_READ(COUNT_LO_REG); in esp_timer_impl_get_counter_reg()
142 lo = REG_READ(COUNT_LO_REG); in esp_timer_impl_get_counter_reg()
152 hi = REG_READ(COUNT_HI_REG); in esp_timer_impl_get_counter_reg()
153 lo = REG_READ(COUNT_LO_REG); in esp_timer_impl_get_counter_reg()
281 uint32_t slowclk_ticks_per_us = REG_READ(RTC_SLOW_CLK_CAL_REG) * TICKS_PER_US; in esp_timer_impl_init()
304 .lo = REG_READ(ALARM_LO_REG), in esp_timer_impl_get_alarm_reg()
305 .hi = REG_READ(ALARM_HI_REG) in esp_timer_impl_get_alarm_reg()
/hal_espressif-3.6.0/components/hal/esp32c3/include/hal/
Dmemprot_ll.h27 return REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG) == 1; in memprot_ll_get_iram0_dram0_split_line_lock()
119 return REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG) & 0x3F; in memprot_ll_get_iram0_split_line_main_I_D_cat()
124 return REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG) & 0x3F; in memprot_ll_get_iram0_split_line_I_0_cat()
129 return REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG) & 0x3F; in memprot_ll_get_iram0_split_line_I_1_cat()
134 …return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CON… in memprot_ll_get_iram0_split_line_main_I_D()
139 …return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CON… in memprot_ll_get_iram0_split_line_I_0()
144 …return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CON… in memprot_ll_get_iram0_split_line_I_1()
158 return REG_READ(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG) == 1; in memprot_ll_iram0_get_pms_lock()
241 return REG_READ(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG) == 1; in memprot_ll_iram0_get_monitor_lock()
276 return REG_READ(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG); in memprot_ll_iram0_get_monitor_enable_register()
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Dhmac_ll.h103 return REG_READ(HMAC_QUERY_ERROR_REG); in hmac_ll_config_error()
113 query = REG_READ(HMAC_QUERY_BUSY_REG); in hmac_ll_wait_idle()
137 result[i] = REG_READ(HMAC_RDATA_BASE + (i * REG_WIDTH)); in hmac_ll_read_result_256()
Dds_ll.h43 return (REG_READ(DS_QUERY_BUSY_REG) > 0) ? true : false; in ds_ll_busy()
59 uint32_t key_error = REG_READ(DS_QUERY_KEY_WRONG_REG); in ds_ll_key_error_source()
137 uint32_t result = REG_READ(DS_QUERY_CHECK_REG); in ds_ll_check_signature()
Daes_ll.h100 output_word = REG_READ(AES_TEXT_OUT_BASE + (i * REG_WIDTH)); in aes_ll_read_block()
123 return REG_READ(AES_STATE_REG); in aes_ll_get_state()
195 iv_word = REG_READ(AES_IV_BASE + (i * REG_WIDTH)); in aes_ll_read_iv()
/hal_espressif-3.6.0/zephyr/esp32s3/src/boot/
Dbootloader_init.c170 inst = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST_REG); in wdt_reset_info_dump()
171 dstat = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS_REG); in wdt_reset_info_dump()
172 data = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_REG); in wdt_reset_info_dump()
173 pc = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG); in wdt_reset_info_dump()
174 lsstat = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT_REG); in wdt_reset_info_dump()
175 lsaddr = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_REG); in wdt_reset_info_dump()
176 lsdata = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_REG); in wdt_reset_info_dump()
178 inst = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_REG); in wdt_reset_info_dump()
179 dstat = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_REG); in wdt_reset_info_dump()
180 data = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA_REG); in wdt_reset_info_dump()
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/hal_espressif-3.6.0/components/bootloader_support/src/esp32s3/
Dbootloader_esp32s3.c156 uint32_t spi_ctrl = REG_READ(SPI_MEM_CTRL_REG(0)); in print_flash_info()
256 inst = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST_REG); in wdt_reset_info_dump()
257 dstat = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS_REG); in wdt_reset_info_dump()
258 data = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_REG); in wdt_reset_info_dump()
259 pc = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG); in wdt_reset_info_dump()
260 lsstat = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT_REG); in wdt_reset_info_dump()
261 lsaddr = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_REG); in wdt_reset_info_dump()
262 lsdata = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_REG); in wdt_reset_info_dump()
265 inst = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_REG); in wdt_reset_info_dump()
266 dstat = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_REG); in wdt_reset_info_dump()
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/hal_espressif-3.6.0/components/hal/esp32h2/include/hal/
Dmemprot_ll.h52 return REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG) == 1; in memprot_ll_get_iram0_dram0_split_line_lock()
144 …return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CON… in memprot_ll_get_iram0_split_line_main_I_D()
149 …return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CON… in memprot_ll_get_iram0_split_line_I_0()
154 …return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CON… in memprot_ll_get_iram0_split_line_I_1()
170 return REG_READ(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG) == 1; in memprot_ll_iram0_get_pms_lock()
254 return REG_READ(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG) == 1; in memprot_ll_iram0_get_monitor_lock()
284 return REG_READ(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG); in memprot_ll_iram0_get_monitor_enable_register()
316 return REG_READ(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG); in memprot_ll_iram0_get_monitor_status_register()
395 …return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CON… in memprot_ll_get_dram0_split_line_D_0()
400 …return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CON… in memprot_ll_get_dram0_split_line_D_1()
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Dhmac_ll.h103 return REG_READ(HMAC_QUERY_ERROR_REG); in hmac_ll_config_error()
113 query = REG_READ(HMAC_QUERY_BUSY_REG); in hmac_ll_wait_idle()
137 result[i] = REG_READ(HMAC_RDATA_BASE + (i * REG_WIDTH)); in hmac_ll_read_result_256()
Dds_ll.h43 return (REG_READ(DS_QUERY_BUSY_REG) > 0) ? true : false; in ds_ll_busy()
59 uint32_t key_error = REG_READ(DS_QUERY_KEY_WRONG_REG); in ds_ll_key_error_source()
137 uint32_t result = REG_READ(DS_QUERY_CHECK_REG); in ds_ll_check_signature()
Daes_ll.h100 output_word = REG_READ(AES_TEXT_OUT_BASE + (i * REG_WIDTH)); in aes_ll_read_block()
123 return REG_READ(AES_STATE_REG); in aes_ll_get_state()
195 iv_word = REG_READ(AES_IV_BASE + (i * REG_WIDTH)); in aes_ll_read_iv()
/hal_espressif-3.6.0/components/bootloader_support/src/esp32s2/
Dbootloader_esp32s2.c145 uint32_t spi_ctrl = REG_READ(SPI_MEM_CTRL_REG(0)); in print_flash_info()
230 inst = REG_READ(ASSIST_DEBUG_PRO_RCD_PDEBUGINST); in wdt_reset_info_dump()
231 dstat = REG_READ(ASSIST_DEBUG_PRO_RCD_PDEBUGSTATUS); in wdt_reset_info_dump()
232 data = REG_READ(ASSIST_DEBUG_PRO_RCD_PDEBUGDATA); in wdt_reset_info_dump()
233 pc = REG_READ(ASSIST_DEBUG_PRO_RCD_PDEBUGPC); in wdt_reset_info_dump()
234 lsstat = REG_READ(ASSIST_DEBUG_PRO_RCD_PDEBUGLS0STAT); in wdt_reset_info_dump()
235 lsaddr = REG_READ(ASSIST_DEBUG_PRO_RCD_PDEBUGLS0ADDR); in wdt_reset_info_dump()
236 lsdata = REG_READ(ASSIST_DEBUG_PRO_RCD_PDEBUGLS0DATA); in wdt_reset_info_dump()
/hal_espressif-3.6.0/components/hal/esp32s2/include/hal/
Daes_ll.h101 output_word = REG_READ(AES_TEXT_OUT_BASE + (i * REG_WIDTH)); in aes_ll_read_block()
134 return REG_READ(AES_STATE_REG); in aes_ll_get_state()
206 iv_word = REG_READ(AES_IV_BASE + (i * REG_WIDTH)); in aes_ll_read_iv()
252 hash_word = REG_READ(AES_H_BASE + (i * REG_WIDTH)); in aes_ll_gcm_read_hash()
312 tag_word = REG_READ(AES_T_BASE + (i * REG_WIDTH)); in aes_ll_gcm_read_tag()
/hal_espressif-3.6.0/components/bootloader_support/src/
Dbootloader_efuse_esp32.c15 eco_bit0 = (REG_READ(EFUSE_BLK0_RDATA3_REG) & 0xF000) >> 15; in bootloader_common_get_chip_revision()
16 eco_bit1 = (REG_READ(EFUSE_BLK0_RDATA5_REG) & 0x100000) >> 20; in bootloader_common_get_chip_revision()
17 eco_bit2 = (REG_READ(SYSCON_DATE_REG) & 0x80000000) >> 31; in bootloader_common_get_chip_revision()
/hal_espressif-3.6.0/components/spi_flash/esp32/
Dspi_flash_rom_patch.c36 while ((REG_READ(SPI_EXT2_REG(1)) & SPI_ST)) { in esp_rom_spiflash_wait_idle()
38 while ((REG_READ(SPI_EXT2_REG(0)) & SPI_ST)) { in esp_rom_spiflash_wait_idle()
41 while ((REG_READ(SPI_MEM_FSM_REG(1)) & SPI_MEM_ST)) { in esp_rom_spiflash_wait_idle()
43 while ((REG_READ(SPI_MEM_FSM_REG(0)) & SPI_MEM_ST)) { in esp_rom_spiflash_wait_idle()
102 while (REG_READ(SPI_CMD_REG(SPI_IDX)) != 0) { in esp_rom_spiflash_unlock()
109 while (REG_READ(SPI_CMD_REG(SPI_IDX)) != 0) { in esp_rom_spiflash_unlock()
295 while (REG_READ(PERIPHS_SPI_FLASH_CMD) != 0); in esp_rom_spiflash_read_data()
307 while (REG_READ(PERIPHS_SPI_FLASH_CMD) != 0); in esp_rom_spiflash_read_data()
404 while ((REG_READ(SPI_EXT2_REG(1)) & SPI_ST)) { in esp_rom_spiflash_config_readmode()
406 while ((REG_READ(SPI_EXT2_REG(0)) & SPI_ST)) { in esp_rom_spiflash_config_readmode()
/hal_espressif-3.6.0/components/hal/esp32s3/include/hal/
Dhmac_ll.h91 return REG_READ(HMAC_QUERY_ERROR_REG); in hmac_ll_query_config_error()
101 query = REG_READ(HMAC_QUERY_BUSY_REG); in hmac_ll_wait_idle()
125 result[i] = REG_READ(HMAC_RDATA_BASE + (i * REG_WIDTH)); in hmac_ll_read_result_256()
Dds_ll.h30 return (REG_READ(DS_QUERY_BUSY_REG) > 0) ? true : false; in ds_ll_busy()
46 uint32_t key_error = REG_READ(DS_QUERY_KEY_WRONG_REG); in ds_ll_key_error_source()
125 uint32_t result = REG_READ(DS_QUERY_CHECK_REG); in ds_ll_check_signature()
Daes_ll.h100 output_word = REG_READ(AES_TEXT_OUT_BASE + (i * REG_WIDTH)); in aes_ll_read_block()
123 return REG_READ(AES_STATE_REG); in aes_ll_get_state()
195 iv_word = REG_READ(AES_IV_BASE + (i * REG_WIDTH)); in aes_ll_read_iv()
/hal_espressif-3.6.0/components/efuse/esp32/
Desp_efuse_utility.c85 *((uint32_t*)buf + i) = REG_READ(addr_wr_block); in esp_efuse_utility_burn_chip()
98 virt_blocks[num_block][subblock++] |= REG_READ(addr_wr_block); in esp_efuse_utility_burn_chip()
109 while (REG_READ(EFUSE_CMD_REG) != 0) {}; in esp_efuse_utility_burn_chip()
112 while (REG_READ(EFUSE_CMD_REG) != 0) {}; in esp_efuse_utility_burn_chip()
151 buf_w_data[i] = REG_READ(addr_wr_block); in read_w_data_and_check_fill()
/hal_espressif-3.6.0/components/bootloader_support/src/esp32/
Dbootloader_sha.c47 while (REG_READ(SHA_256_BUSY_REG) != 0) { } in bootloader_sha256_data()
106 while (REG_READ(SHA_256_BUSY_REG) == 1) { } in bootloader_sha256_finish()
108 while (REG_READ(SHA_256_BUSY_REG) == 1) { } in bootloader_sha256_finish()
/hal_espressif-3.6.0/components/ulp/ulp_riscv/include/ulp_riscv/
Dulp_riscv_register_ops.h51 #define REG_READ(_r) ({ … macro
77 …((REG_READ(_r) >> (_f##_S)) & (_f##_V)); …
82 …(REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S))))); …
/hal_espressif-3.6.0/components/mbedtls/test/
Dtest_apb_dport_access.c38 uint32_t initial = REG_READ(UART_DATE_REG(0)); in apb_access_loop_task()
40 if (REG_READ(UART_DATE_REG(0)) != initial) { in apb_access_loop_task()
/hal_espressif-3.6.0/components/esp_system/port/soc/esp32s2/
Dcache_err_int.c81 if (REG_READ(EXTMEM_CACHE_DBG_STATUS0_REG) != 0 || in esp_cache_err_get_cpuid()
82 REG_READ(EXTMEM_CACHE_DBG_STATUS1_REG) != 0) { in esp_cache_err_get_cpuid()

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