1 /*
2 * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <zephyr/kernel.h>
8 #include <zephyr/logging/log.h>
9
10 #if defined(__ZEPHYR__)
11 #include <stdlib.h>
12 #endif
13
14 #include "sys/param.h"
15 #include "esp_timer_impl.h"
16 #include "esp_timer.h"
17 #include "esp_err.h"
18 #include "esp_system.h"
19 #include "esp_task.h"
20 #include "esp_attr.h"
21 #include "esp_log.h"
22 #include "driver/periph_ctrl.h"
23 #include "soc/soc.h"
24 #include "soc/timer_group_reg.h"
25 #include "soc/rtc.h"
26
27 #ifdef CONFIG_SOC_SERIES_ESP32C3
28 #include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
29 #else
30 #include <zephyr/drivers/interrupt_controller/intc_esp32.h>
31 #endif
32
33 #if CONFIG_SOC_SERIES_ESP32
34 #include "esp32/rom/rtc.h"
35 #include "esp32/clk.h"
36 #elif CONFIG_SOC_SERIES_ESP32S2
37 #include "esp32s2/rom/rtc.h"
38 #include "esp32s2/clk.h"
39 #elif CONFIG_SOC_SERIES_ESP32S3
40 #include "esp32s3/rom/rtc.h"
41 #include "esp32s3/clk.h"
42 #elif CONFIG_SOC_SERIES_ESP32C3
43 #include "esp32c3/rom/rtc.h"
44 #include "esp32c3/clk.h"
45 #endif
46
47 /**
48 * @file esp_timer_lac.c
49 * @brief Implementation of chip-specific part of esp_timer
50 *
51 * This implementation uses TG0 LAC timer of the ESP32. This timer is
52 * a 64-bit up-counting timer, with a programmable compare value (called 'alarm'
53 * hereafter). When the timer reaches compare value, interrupt is raised.
54 * The timer can be configured to produce an edge or a level interrupt.
55 */
56
57 /* Selects which Timer Group peripheral to use */
58 #define LACT_MODULE 0
59
60 #if LACT_MODULE == 0
61 #define INTR_SOURCE_LACT ETS_TG0_LACT_LEVEL_INTR_SOURCE
62 #define PERIPH_LACT PERIPH_TIMG0_MODULE
63 #elif LACT_MODULE == 1
64 #define INTR_SOURCE_LACT ETS_TG1_LACT_LEVEL_INTR_SOURCE
65 #define PERIPH_LACT PERIPH_TIMG1_MODULE
66 #else
67 #error "Incorrect the number of LACT module (only 0 or 1)"
68 #endif
69
70 /* Desired number of timer ticks per microsecond.
71 * This value should be small enough so that all possible APB frequencies
72 * could be divided by it without remainder.
73 * On the other hand, the smaller this value is, the longer we need to wait
74 * after setting UPDATE_REG before the timer value can be read.
75 * If TICKS_PER_US == 1, then we need to wait up to 1 microsecond, which
76 * makes esp_timer_impl_get_time function take too much time.
77 * The value TICKS_PER_US == 2 allows for most of the APB frequencies, and
78 * allows reading the counter quickly enough.
79 */
80 #define TICKS_PER_US 2
81
82 /* Shorter register names, used in this file */
83 #define CONFIG_REG (TIMG_LACTCONFIG_REG(LACT_MODULE))
84 #define RTC_STEP_REG (TIMG_LACTRTC_REG(LACT_MODULE))
85 #define ALARM_LO_REG (TIMG_LACTALARMLO_REG(LACT_MODULE))
86 #define ALARM_HI_REG (TIMG_LACTALARMHI_REG(LACT_MODULE))
87 #define COUNT_LO_REG (TIMG_LACTLO_REG(LACT_MODULE))
88 #define COUNT_HI_REG (TIMG_LACTHI_REG(LACT_MODULE))
89 #define UPDATE_REG (TIMG_LACTUPDATE_REG(LACT_MODULE))
90 #define LOAD_REG (TIMG_LACTLOAD_REG(LACT_MODULE))
91 #define LOAD_LO_REG (TIMG_LACTLOADLO_REG(LACT_MODULE))
92 #define LOAD_HI_REG (TIMG_LACTLOADHI_REG(LACT_MODULE))
93 #define INT_ENA_REG (TIMG_INT_ENA_TIMERS_REG(LACT_MODULE))
94 #define INT_ST_REG (TIMG_INT_ST_TIMERS_REG(LACT_MODULE))
95 #define INT_CLR_REG (TIMG_INT_CLR_TIMERS_REG(LACT_MODULE))
96
97 /* Function prototype for alarm interrupt handler function */
98 typedef void (*alarm_intr_handler_t)(const void *arg);
99
100 /* Helper type to convert between a 64-bit value and a pair of 32-bit values without shifts and masks */
101 typedef struct {
102 union {
103 struct {
104 uint32_t lo;
105 uint32_t hi;
106 };
107 uint64_t val;
108 };
109 } timer_64b_reg_t;
110
111 static const char* TAG = "esp_timer_impl";
112
113 /* Function from the upper layer to be called when the interrupt happens.
114 * Registered in esp_timer_impl_init.
115 */
116 static alarm_intr_handler_t s_alarm_handler;
117
118 /* Spinlock used to protect access to the hardware registers. */
119 static unsigned int s_time_update_lock;
120
121
esp_timer_impl_lock(void)122 void esp_timer_impl_lock(void)
123 {
124 s_time_update_lock = irq_lock();
125 }
126
esp_timer_impl_unlock(void)127 void esp_timer_impl_unlock(void)
128 {
129 irq_unlock(s_time_update_lock);
130 }
131
esp_timer_impl_get_counter_reg(void)132 uint64_t IRAM_ATTR esp_timer_impl_get_counter_reg(void)
133 {
134 uint32_t lo, hi;
135 uint32_t lo_start = REG_READ(COUNT_LO_REG);
136 uint32_t div = REG_GET_FIELD(CONFIG_REG, TIMG_LACT_DIVIDER);
137 /* The peripheral doesn't have a bit to indicate that the update is done, so we poll the
138 * lower 32 bit part of the counter until it changes, or a timeout expires.
139 */
140 REG_WRITE(UPDATE_REG, 1);
141 do {
142 lo = REG_READ(COUNT_LO_REG);
143 } while (lo == lo_start && div-- > 0);
144
145 /* Since this function is called without a critical section, verify that LO and HI
146 * registers are consistent. That is, if an interrupt happens between reading LO and
147 * HI registers, and esp_timer_impl_get_time is called from an ISR, then try to
148 * detect this by the change in LO register value, and re-read both registers.
149 */
150 do {
151 lo_start = lo;
152 hi = REG_READ(COUNT_HI_REG);
153 lo = REG_READ(COUNT_LO_REG);
154 } while (lo != lo_start);
155
156 timer_64b_reg_t result = {
157 .lo = lo,
158 .hi = hi
159 };
160 return result.val;
161 }
162
esp_timer_impl_get_time(void)163 int64_t IRAM_ATTR esp_timer_impl_get_time(void)
164 {
165 if (s_alarm_handler == NULL) {
166 return 0;
167 }
168 return esp_timer_impl_get_counter_reg() / TICKS_PER_US;
169 }
170
171 int64_t esp_timer_get_time(void) __attribute__((alias("esp_timer_impl_get_time")));
172
esp_timer_impl_set_alarm_id(uint64_t timestamp,unsigned alarm_id)173 void IRAM_ATTR esp_timer_impl_set_alarm_id(uint64_t timestamp, unsigned alarm_id)
174 {
175 static uint64_t timestamp_id[2] = { UINT64_MAX, UINT64_MAX };
176 s_time_update_lock = irq_lock();
177 timestamp_id[alarm_id] = timestamp;
178 timestamp = MIN(timestamp_id[0], timestamp_id[1]);
179 if (timestamp != UINT64_MAX) {
180 int64_t offset = TICKS_PER_US * 2;
181 uint64_t now_time = esp_timer_impl_get_counter_reg();
182 timer_64b_reg_t alarm = { .val = MAX(timestamp * TICKS_PER_US, now_time + offset) };
183 do {
184 REG_CLR_BIT(CONFIG_REG, TIMG_LACT_ALARM_EN);
185 REG_WRITE(ALARM_LO_REG, alarm.lo);
186 REG_WRITE(ALARM_HI_REG, alarm.hi);
187 REG_SET_BIT(CONFIG_REG, TIMG_LACT_ALARM_EN);
188 now_time = esp_timer_impl_get_counter_reg();
189 int64_t delta = (int64_t)alarm.val - (int64_t)now_time;
190 if (delta <= 0 && REG_GET_FIELD(INT_ST_REG, TIMG_LACT_INT_ST) == 0) {
191 // new alarm is less than the counter and the interrupt flag is not set
192 offset += abs((int)delta) + TICKS_PER_US * 2;
193 alarm.val = now_time + offset;
194 } else {
195 // finish if either (alarm > counter) or the interrupt flag is already set.
196 break;
197 }
198 } while(1);
199 }
200 irq_unlock(s_time_update_lock);
201 }
202
esp_timer_impl_set_alarm(uint64_t timestamp)203 void IRAM_ATTR esp_timer_impl_set_alarm(uint64_t timestamp)
204 {
205 esp_timer_impl_set_alarm_id(timestamp, 0);
206 }
207
timer_alarm_isr(void * arg)208 static void IRAM_ATTR timer_alarm_isr(void *arg)
209 {
210 /* Clear interrupt status */
211 REG_WRITE(INT_CLR_REG, TIMG_LACT_INT_CLR);
212 /* Call the upper layer handler */
213 (*s_alarm_handler)(arg);
214 }
215
esp_timer_impl_update_apb_freq(uint32_t apb_ticks_per_us)216 void IRAM_ATTR esp_timer_impl_update_apb_freq(uint32_t apb_ticks_per_us)
217 {
218 s_time_update_lock = irq_lock();
219 assert(apb_ticks_per_us >= 3 && "divider value too low");
220 assert(apb_ticks_per_us % TICKS_PER_US == 0 && "APB frequency (in MHz) should be divisible by TICK_PER_US");
221 REG_SET_FIELD(CONFIG_REG, TIMG_LACT_DIVIDER, apb_ticks_per_us / TICKS_PER_US);
222 irq_unlock(s_time_update_lock);
223 }
224
esp_timer_impl_advance(int64_t time_diff_us)225 void esp_timer_impl_advance(int64_t time_diff_us)
226 {
227 s_time_update_lock = irq_lock();
228 uint64_t now = esp_timer_impl_get_time();
229 timer_64b_reg_t dst = { .val = (now + time_diff_us) * TICKS_PER_US };
230 REG_WRITE(LOAD_LO_REG, dst.lo);
231 REG_WRITE(LOAD_HI_REG, dst.hi);
232 REG_WRITE(LOAD_REG, 1);
233 irq_unlock(s_time_update_lock);
234 }
235
esp_timer_impl_early_init(void)236 esp_err_t esp_timer_impl_early_init(void)
237 {
238 periph_module_enable(PERIPH_LACT);
239
240 REG_WRITE(CONFIG_REG, 0);
241 REG_WRITE(LOAD_LO_REG, 0);
242 REG_WRITE(LOAD_HI_REG, 0);
243 REG_WRITE(ALARM_LO_REG, UINT32_MAX);
244 REG_WRITE(ALARM_HI_REG, UINT32_MAX);
245 REG_WRITE(LOAD_REG, 1);
246 REG_SET_BIT(INT_CLR_REG, TIMG_LACT_INT_CLR);
247 REG_SET_FIELD(CONFIG_REG, TIMG_LACT_DIVIDER, APB_CLK_FREQ / 1000000 / TICKS_PER_US);
248 REG_SET_BIT(CONFIG_REG, TIMG_LACT_INCREASE |
249 TIMG_LACT_LEVEL_INT_EN |
250 TIMG_LACT_EN);
251
252 return ESP_OK;
253 }
254
255 #define ETS_TG0_T1_INUM 10 /**< use edge interrupt*/
256
esp_timer_impl_init(intr_handler_t alarm_handler)257 esp_err_t esp_timer_impl_init(intr_handler_t alarm_handler)
258 {
259 s_alarm_handler = (alarm_intr_handler_t) alarm_handler;
260 esp_err_t err = ESP_OK;
261
262 const int interrupt_lvl = (1 << 1) & ESP_INTR_FLAG_LEVELMASK;
263 err = esp_intr_alloc(INTR_SOURCE_LACT, ESP_INTR_FLAG_IRAM | interrupt_lvl,
264 (intr_handler_t)timer_alarm_isr, NULL, NULL);
265
266 if (err != ESP_OK) {
267 ESP_EARLY_LOGE(TAG, "irq_connect_dynamic failed (0x%0x)", err);
268 return err;
269 }
270
271 /* In theory, this needs a shared spinlock with the timer group driver.
272 * However since esp_timer_impl_init is called early at startup, this
273 * will not cause issues in practice.
274 */
275 REG_SET_BIT(INT_ENA_REG, TIMG_LACT_INT_ENA);
276
277 esp_timer_impl_update_apb_freq(esp_clk_apb_freq() / 1000000);
278
279 // Set the step for the sleep mode when the timer will work
280 // from a slow_clk frequency instead of the APB frequency.
281 uint32_t slowclk_ticks_per_us = REG_READ(RTC_SLOW_CLK_CAL_REG) * TICKS_PER_US;
282 REG_SET_FIELD(RTC_STEP_REG, TIMG_LACT_RTC_STEP_LEN, slowclk_ticks_per_us);
283
284 return ESP_OK;
285 }
286
esp_timer_impl_deinit(void)287 void esp_timer_impl_deinit(void)
288 {
289 REG_WRITE(CONFIG_REG, 0);
290 REG_SET_BIT(INT_CLR_REG, TIMG_LACT_INT_CLR);
291 /* TODO: also clear TIMG_LACT_INT_ENA; however see the note in esp_timer_impl_init. */
292 }
293
294 /* FIXME: This value is safe for 80MHz APB frequency, should be modified to depend on clock frequency. */
esp_timer_impl_get_min_period_us(void)295 uint64_t IRAM_ATTR esp_timer_impl_get_min_period_us(void)
296 {
297 return 50;
298 }
299
esp_timer_impl_get_alarm_reg(void)300 uint64_t esp_timer_impl_get_alarm_reg(void)
301 {
302 s_time_update_lock = irq_lock();
303 timer_64b_reg_t alarm = {
304 .lo = REG_READ(ALARM_LO_REG),
305 .hi = REG_READ(ALARM_HI_REG)
306 };
307 irq_unlock(s_time_update_lock);
308 return alarm.val;
309 }
310
311 void esp_timer_private_update_apb_freq(uint32_t apb_ticks_per_us) __attribute__((alias("esp_timer_impl_update_apb_freq")));
312 void esp_timer_private_advance(int64_t time_us) __attribute__((alias("esp_timer_impl_advance")));
313 void esp_timer_private_lock(void) __attribute__((alias("esp_timer_impl_lock")));
314 void esp_timer_private_unlock(void) __attribute__((alias("esp_timer_impl_unlock")));
315
