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Searched refs:BIT5 (Results 1 – 19 of 19) sorted by relevance

/hal_espressif-3.6.0/components/esp_common/include/
Desp_bit_defs.h44 #define BIT5 0x00000020 macro
/hal_espressif-3.6.0/components/bt/host/bluedroid/external/sbc/decoder/include/
Doi_stddefs.h191 #define BIT5 0x00000020 /**< preprocessor alias for 32-bit value with bit 5 set, used to specify… macro
/hal_espressif-3.6.0/components/soc/esp32c3/include/soc/
Dsoc_caps.h114 … SOC_GPIO_DEEP_SLEEP_WAKEUP_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
/hal_espressif-3.6.0/components/soc/esp32h2/include/soc/
Dsoc_caps.h102 … SOC_GPIO_DEEP_SLEEP_WAKEUP_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
/hal_espressif-3.6.0/components/esp_rom/include/esp32/rom/
Drtc.h122 MAC_TRIG = BIT5,
Duart.h61 #define UART_TRX_FIFO_EMPTY_FLAG BIT5
Dspi_flash.h124 #define ESP_ROM_SPIFLASH_BP_MASK_ISSI (BIT7 | BIT5 | BIT4 | BIT3 | BIT2)
/hal_espressif-3.6.0/components/freemodbus/common/include/
Desp_modbus_common.h103 MB_EVENT_COILS_RD = BIT5, /*!< Modbus Event Read Coils. */
/hal_espressif-3.6.0/components/esp_rom/include/esp32s2/rom/
Drtc.h124 MAC_TRIG = BIT5,
Duart.h61 #define UART_TRX_FIFO_EMPTY_FLAG BIT5
/hal_espressif-3.6.0/components/esp_rom/include/esp32h2/rom/
Drtc.h128 MAC_TRIG = BIT5,
Duart.h61 #define UART_TRX_FIFO_EMPTY_FLAG BIT5
/hal_espressif-3.6.0/components/esp_rom/include/esp32c3/rom/
Drtc.h134 MAC_TRIG = BIT5,
Duart.h61 #define UART_TRX_FIFO_EMPTY_FLAG BIT5
/hal_espressif-3.6.0/components/esp_rom/include/esp32s3/rom/
Drtc.h121 MAC_TRIG = BIT5,
Duart.h59 #define UART_TRX_FIFO_EMPTY_FLAG BIT5
/hal_espressif-3.6.0/components/bt/host/bluedroid/external/sbc/decoder/srce/
Ddecoder-private.c140 frame->blocks = (d1 & (BIT5 | BIT4)) >> 4; in OI_SBC_ReadHeader()
Ddecoder-sbc.c393 blocks = block_values[(blocks & (BIT5 | BIT4)) >> 4]; in OI_CODEC_SBC_FrameCount()
/hal_espressif-3.6.0/components/bootloader_support/src/
Dbootloader_flash.c51 #define ESP_BOOTLOADER_SPIFLASH_BP_MASK_ISSI (BIT7 | BIT5 | BIT4 | BIT3 | BIT2)