1 // Copyright 2020 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #ifndef _ROM_RTC_H_
16 #define _ROM_RTC_H_
17
18 #include "ets_sys.h"
19
20 #include <stdbool.h>
21 #include <stdint.h>
22
23 #include "soc/soc.h"
24 #include "soc/rtc_cntl_reg.h"
25 #include "soc/reset_reasons.h"
26
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30
31 /** \defgroup rtc_apis, rtc registers and memory related apis
32 * @brief rtc apis
33 */
34
35 /** @addtogroup rtc_apis
36 * @{
37 */
38
39 /**************************************************************************************
40 * Note: *
41 * Some Rtc memory and registers are used, in ROM or in internal library. *
42 * Please do not use reserved or used rtc memory or registers. *
43 * *
44 *************************************************************************************
45 * RTC Memory & Store Register usage
46 *************************************************************************************
47 * rtc memory addr type size usage
48 * 0x3f421000(0x50000000) Slow SIZE_CP Co-Processor code/Reset Entry
49 * 0x3f421000+SIZE_CP Slow 8192-SIZE_CP
50 *
51 * 0x3ff80000(0x40070000) Fast 8192 deep sleep entry code
52 *
53 *************************************************************************************
54 * RTC store registers usage
55 * RTC_CNTL_STORE0_REG Reserved
56 * RTC_CNTL_STORE1_REG RTC_SLOW_CLK calibration value
57 * RTC_CNTL_STORE2_REG Boot time, low word
58 * RTC_CNTL_STORE3_REG Boot time, high word
59 * RTC_CNTL_STORE4_REG External XTAL frequency
60 * RTC_CNTL_STORE5_REG APB bus frequency
61 * RTC_CNTL_STORE6_REG FAST_RTC_MEMORY_ENTRY
62 * RTC_CNTL_STORE7_REG FAST_RTC_MEMORY_CRC
63 *************************************************************************************
64 */
65
66 #define RTC_SLOW_CLK_CAL_REG RTC_CNTL_STORE1_REG
67 #define RTC_BOOT_TIME_LOW_REG RTC_CNTL_STORE2_REG
68 #define RTC_BOOT_TIME_HIGH_REG RTC_CNTL_STORE3_REG
69 #define RTC_XTAL_FREQ_REG RTC_CNTL_STORE4_REG
70 #define RTC_APB_FREQ_REG RTC_CNTL_STORE5_REG
71 #define RTC_ENTRY_ADDR_REG RTC_CNTL_STORE6_REG
72 #define RTC_RESET_CAUSE_REG RTC_CNTL_STORE6_REG
73 #define RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG
74
75 #define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code.
76
77
78 typedef enum {
79 AWAKE = 0, //<CPU ON
80 LIGHT_SLEEP = BIT0, //CPU waiti, PLL ON. We don't need explicitly set this mode.
81 DEEP_SLEEP = BIT1 //CPU OFF, PLL OFF, only specific timer could wake up
82 } SLEEP_MODE;
83
84 typedef enum {
85 NO_MEAN = 0,
86 POWERON_RESET = 1, /**<1, Vbat power on reset*/
87 RTC_SW_SYS_RESET = 3, /**<3, Software reset digital core*/
88 DEEPSLEEP_RESET = 5, /**<5, Deep Sleep reset digital core*/
89 TG0WDT_SYS_RESET = 7, /**<7, Timer Group0 Watch dog reset digital core*/
90 TG1WDT_SYS_RESET = 8, /**<8, Timer Group1 Watch dog reset digital core*/
91 RTCWDT_SYS_RESET = 9, /**<9, RTC Watch dog Reset digital core*/
92 INTRUSION_RESET = 10, /**<10, Instrusion tested to reset CPU*/
93 TG0WDT_CPU_RESET = 11, /**<11, Time Group0 reset CPU*/
94 RTC_SW_CPU_RESET = 12, /**<12, Software reset CPU*/
95 RTCWDT_CPU_RESET = 13, /**<13, RTC Watch dog Reset CPU*/
96 RTCWDT_BROWN_OUT_RESET = 15, /**<15, Reset when the vdd voltage is not stable*/
97 RTCWDT_RTC_RESET = 16, /**<16, RTC Watch dog reset digital core and rtc module*/
98 TG1WDT_CPU_RESET = 17, /**<17, Time Group1 reset CPU*/
99 SUPER_WDT_RESET = 18, /**<18, super watchdog reset digital core and rtc module*/
100 GLITCH_RTC_RESET = 19, /**<19, glitch reset digital core and rtc module*/
101 EFUSE_RESET = 20, /**<20, efuse reset digital core*/
102 USB_UART_CHIP_RESET = 21, /**<21, usb uart reset digital core */
103 USB_JTAG_CHIP_RESET = 22, /**<22, usb jtag reset digital core */
104 POWER_GLITCH_RESET = 23, /**<23, power glitch reset digital core and rtc module*/
105 } RESET_REASON;
106
107 // Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h
108 _Static_assert((soc_reset_reason_t)POWERON_RESET == RESET_REASON_CHIP_POWER_ON, "POWERON_RESET != RESET_REASON_CHIP_POWER_ON");
109 _Static_assert((soc_reset_reason_t)RTC_SW_SYS_RESET == RESET_REASON_CORE_SW, "RTC_SW_SYS_RESET != RESET_REASON_CORE_SW");
110 _Static_assert((soc_reset_reason_t)DEEPSLEEP_RESET == RESET_REASON_CORE_DEEP_SLEEP, "DEEPSLEEP_RESET != RESET_REASON_CORE_DEEP_SLEEP");
111 _Static_assert((soc_reset_reason_t)TG0WDT_SYS_RESET == RESET_REASON_CORE_MWDT0, "TG0WDT_SYS_RESET != RESET_REASON_CORE_MWDT0");
112 _Static_assert((soc_reset_reason_t)TG1WDT_SYS_RESET == RESET_REASON_CORE_MWDT1, "TG1WDT_SYS_RESET != RESET_REASON_CORE_MWDT1");
113 _Static_assert((soc_reset_reason_t)RTCWDT_SYS_RESET == RESET_REASON_CORE_RTC_WDT, "RTCWDT_SYS_RESET != RESET_REASON_CORE_RTC_WDT");
114 _Static_assert((soc_reset_reason_t)TG0WDT_CPU_RESET == RESET_REASON_CPU0_MWDT0, "TG0WDT_CPU_RESET != RESET_REASON_CPU0_MWDT0");
115 _Static_assert((soc_reset_reason_t)RTC_SW_CPU_RESET == RESET_REASON_CPU0_SW, "RTC_SW_CPU_RESET != RESET_REASON_CPU0_SW");
116 _Static_assert((soc_reset_reason_t)RTCWDT_CPU_RESET == RESET_REASON_CPU0_RTC_WDT, "RTCWDT_CPU_RESET != RESET_REASON_CPU0_RTC_WDT");
117 _Static_assert((soc_reset_reason_t)RTCWDT_BROWN_OUT_RESET == RESET_REASON_SYS_BROWN_OUT, "RTCWDT_BROWN_OUT_RESET != RESET_REASON_SYS_BROWN_OUT");
118 _Static_assert((soc_reset_reason_t)RTCWDT_RTC_RESET == RESET_REASON_SYS_RTC_WDT, "RTCWDT_RTC_RESET != RESET_REASON_SYS_RTC_WDT");
119 _Static_assert((soc_reset_reason_t)TG1WDT_CPU_RESET == RESET_REASON_CPU0_MWDT1, "TG1WDT_CPU_RESET != RESET_REASON_CPU0_MWDT1");
120 _Static_assert((soc_reset_reason_t)SUPER_WDT_RESET == RESET_REASON_SYS_SUPER_WDT, "SUPER_WDT_RESET != RESET_REASON_SYS_SUPER_WDT");
121 _Static_assert((soc_reset_reason_t)GLITCH_RTC_RESET == RESET_REASON_SYS_CLK_GLITCH, "GLITCH_RTC_RESET != RESET_REASON_SYS_CLK_GLITCH");
122 _Static_assert((soc_reset_reason_t)EFUSE_RESET == RESET_REASON_CORE_EFUSE_CRC, "EFUSE_RESET != RESET_REASON_CORE_EFUSE_CRC");
123 _Static_assert((soc_reset_reason_t)USB_UART_CHIP_RESET == RESET_REASON_CORE_USB_UART, "USB_UART_CHIP_RESET != RESET_REASON_CORE_USB_UART");
124 _Static_assert((soc_reset_reason_t)USB_JTAG_CHIP_RESET == RESET_REASON_CORE_USB_JTAG, "USB_JTAG_CHIP_RESET != RESET_REASON_CORE_USB_JTAG");
125 _Static_assert((soc_reset_reason_t)POWER_GLITCH_RESET == RESET_REASON_CORE_PWR_GLITCH, "POWER_GLITCH_RESET != RESET_REASON_CORE_PWR_GLITCH");
126
127 typedef enum {
128 NO_SLEEP = 0,
129 EXT_EVENT0_TRIG = BIT0,
130 EXT_EVENT1_TRIG = BIT1,
131 GPIO_TRIG = BIT2,
132 TIMER_EXPIRE = BIT3,
133 SDIO_TRIG = BIT4,
134 MAC_TRIG = BIT5,
135 UART0_TRIG = BIT6,
136 UART1_TRIG = BIT7,
137 TOUCH_TRIG = BIT8,
138 SAR_TRIG = BIT9,
139 BT_TRIG = BIT10,
140 RISCV_TRIG = BIT11,
141 XTAL_DEAD_TRIG = BIT12,
142 RISCV_TRAP_TRIG = BIT13,
143 USB_TRIG = BIT14
144 } WAKEUP_REASON;
145
146 typedef enum {
147 DISEN_WAKEUP = NO_SLEEP,
148 EXT_EVENT0_TRIG_EN = EXT_EVENT0_TRIG,
149 EXT_EVENT1_TRIG_EN = EXT_EVENT1_TRIG,
150 GPIO_TRIG_EN = GPIO_TRIG,
151 TIMER_EXPIRE_EN = TIMER_EXPIRE,
152 SDIO_TRIG_EN = SDIO_TRIG,
153 MAC_TRIG_EN = MAC_TRIG,
154 UART0_TRIG_EN = UART0_TRIG,
155 UART1_TRIG_EN = UART1_TRIG,
156 TOUCH_TRIG_EN = TOUCH_TRIG,
157 SAR_TRIG_EN = SAR_TRIG,
158 BT_TRIG_EN = BT_TRIG,
159 RISCV_TRIG_EN = RISCV_TRIG,
160 XTAL_DEAD_TRIG_EN = XTAL_DEAD_TRIG,
161 RISCV_TRAP_TRIG_EN = RISCV_TRAP_TRIG,
162 USB_TRIG_EN = USB_TRIG
163 } WAKEUP_ENABLE;
164
165 /**
166 * @brief Get the reset reason for CPU.
167 *
168 * @param int cpu_no : CPU no.
169 *
170 * @return RESET_REASON
171 */
172 RESET_REASON rtc_get_reset_reason(int cpu_no);
173
174 /**
175 * @brief Get the wakeup cause for CPU.
176 *
177 * @param int cpu_no : CPU no.
178 *
179 * @return WAKEUP_REASON
180 */
181 WAKEUP_REASON rtc_get_wakeup_cause(void);
182
183 /**
184 * @brief Get CRC for Fast RTC Memory.
185 *
186 * @param uint32_t start_addr : 0 - 0x7ff for Fast RTC Memory.
187 *
188 * @param uint32_t crc_len : 0 - 0x7ff, 0 for 4 byte, 0x7ff for 0x2000 byte.
189 *
190 * @return uint32_t : CRC32 result
191 */
192 uint32_t calc_rtc_memory_crc(uint32_t start_addr, uint32_t crc_len);
193
194 /**
195 * @brief Suppress ROM log by setting specific RTC control register.
196 * @note This is not a permanent disable of ROM logging since the RTC register can not retain after chip reset.
197 *
198 * @param None
199 *
200 * @return None
201 */
rtc_suppress_rom_log(void)202 static inline void rtc_suppress_rom_log(void)
203 {
204 /* To disable logging in the ROM, only the least significant bit of the register is used,
205 * but since this register is also used to store the frequency of the main crystal (RTC_XTAL_FREQ_REG),
206 * you need to write to this register in the same format.
207 * Namely, the upper 16 bits and lower should be the same.
208 */
209 REG_SET_BIT(RTC_CNTL_STORE4_REG, RTC_DISABLE_ROM_LOG);
210 }
211
212 /**
213 * @brief Set CRC of Fast RTC memory 0-0x7ff into RTC STORE7.
214 *
215 * @param None
216 *
217 * @return None
218 */
219 void set_rtc_memory_crc(void);
220
221 /**
222 * @brief Fetch entry from RTC memory and RTC STORE reg
223 *
224 * @param uint32_t * entry_addr : the address to save entry
225 *
226 * @param RESET_REASON reset_reason : reset reason this time
227 *
228 * @return None
229 */
230 void rtc_boot_control(uint32_t *entry_addr, RESET_REASON reset_reason);
231
232 /**
233 * @brief Software Reset digital core.
234 *
235 * It is not recommended to use this function in esp-idf, use
236 * esp_restart() instead.
237 *
238 * @param None
239 *
240 * @return None
241 */
242 void software_reset(void);
243
244 /**
245 * @brief Software Reset digital core.
246 *
247 * It is not recommended to use this function in esp-idf, use
248 * esp_restart() instead.
249 *
250 * @param int cpu_no : The CPU to reset, 0 for PRO CPU, 1 for APP CPU.
251 *
252 * @return None
253 */
254 void software_reset_cpu(int cpu_no);
255
256 /**
257 * @}
258 */
259
260 #ifdef __cplusplus
261 }
262 #endif
263
264 #endif /* _ROM_RTC_H_ */
265
