1 /*
2 * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #ifndef _ROM_RTC_H_
8 #define _ROM_RTC_H_
9
10 #include "ets_sys.h"
11
12 #include <stdbool.h>
13 #include <stdint.h>
14
15 #include "soc/soc.h"
16 #include "soc/rtc_cntl_reg.h"
17 #include "soc/reset_reasons.h"
18
19 #ifdef __cplusplus
20 extern "C" {
21 #endif
22
23 /** \defgroup rtc_apis, rtc registers and memory related apis
24 * @brief rtc apis
25 */
26
27 /** @addtogroup rtc_apis
28 * @{
29 */
30
31 /**************************************************************************************
32 * Note: *
33 * Some Rtc memory and registers are used, in ROM or in internal library. *
34 * Please do not use reserved or used rtc memory or registers. *
35 * *
36 *************************************************************************************
37 * RTC Memory & Store Register usage
38 *************************************************************************************
39 * rtc memory addr type size usage
40 * 0x3f421000(0x50000000) Slow SIZE_CP Co-Processor code/Reset Entry
41 * 0x3f421000+SIZE_CP Slow 8192-SIZE_CP
42 *
43 * 0x3ff80000(0x40070000) Fast 8192 deep sleep entry code
44 *
45 *************************************************************************************
46 * RTC store registers usage
47 * RTC_CNTL_STORE0_REG Reserved
48 * RTC_CNTL_STORE1_REG RTC_SLOW_CLK calibration value
49 * RTC_CNTL_STORE2_REG Boot time, low word
50 * RTC_CNTL_STORE3_REG Boot time, high word
51 * RTC_CNTL_STORE4_REG External XTAL frequency
52 * RTC_CNTL_STORE5_REG APB bus frequency
53 * RTC_CNTL_STORE6_REG FAST_RTC_MEMORY_ENTRY
54 * RTC_CNTL_STORE7_REG FAST_RTC_MEMORY_CRC
55 *************************************************************************************
56 */
57
58 #define RTC_SLOW_CLK_CAL_REG RTC_CNTL_STORE1_REG
59 #define RTC_BOOT_TIME_LOW_REG RTC_CNTL_STORE2_REG
60 #define RTC_BOOT_TIME_HIGH_REG RTC_CNTL_STORE3_REG
61 #define RTC_XTAL_FREQ_REG RTC_CNTL_STORE4_REG
62 #define RTC_APB_FREQ_REG RTC_CNTL_STORE5_REG
63 #define RTC_ENTRY_ADDR_REG RTC_CNTL_STORE6_REG
64 #define RTC_RESET_CAUSE_REG RTC_CNTL_STORE6_REG
65 #define RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG
66
67 #define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code.
68
69
70 typedef enum {
71 AWAKE = 0, //<CPU ON
72 LIGHT_SLEEP = BIT0, //CPU waiti, PLL ON. We don't need explicitly set this mode.
73 DEEP_SLEEP = BIT1 //CPU OFF, PLL OFF, only specific timer could wake up
74 } SLEEP_MODE;
75
76 typedef enum {
77 NO_MEAN = 0,
78 POWERON_RESET = 1, /**<1, Vbat power on reset*/
79 RTC_SW_SYS_RESET = 3, /**<3, Software reset digital core*/
80 DEEPSLEEP_RESET = 5, /**<5, Deep Sleep reset digital core*/
81 TG0WDT_SYS_RESET = 7, /**<7, Timer Group0 Watch dog reset digital core*/
82 TG1WDT_SYS_RESET = 8, /**<8, Timer Group1 Watch dog reset digital core*/
83 RTCWDT_SYS_RESET = 9, /**<9, RTC Watch dog Reset digital core*/
84 INTRUSION_RESET = 10, /**<10, Instrusion tested to reset CPU*/
85 TG0WDT_CPU_RESET = 11, /**<11, Time Group0 reset CPU*/
86 RTC_SW_CPU_RESET = 12, /**<12, Software reset CPU*/
87 RTCWDT_CPU_RESET = 13, /**<13, RTC Watch dog Reset CPU*/
88 RTCWDT_BROWN_OUT_RESET = 15, /**<15, Reset when the vdd voltage is not stable*/
89 RTCWDT_RTC_RESET = 16, /**<16, RTC Watch dog reset digital core and rtc module*/
90 TG1WDT_CPU_RESET = 17, /**<17, Time Group1 reset CPU*/
91 SUPER_WDT_RESET = 18, /**<18, super watchdog reset digital core and rtc module*/
92 GLITCH_RTC_RESET = 19, /**<19, glitch reset digital core and rtc module*/
93 EFUSE_RESET = 20, /**<20, efuse reset digital core*/
94 USB_UART_CHIP_RESET = 21, /**<21, usb uart reset digital core */
95 USB_JTAG_CHIP_RESET = 22, /**<22, usb jtag reset digital core */
96 POWER_GLITCH_RESET = 23, /**<23, power glitch reset digital core and rtc module*/
97 JTAG_RESET = 24, /**<24, jtag reset CPU*/
98 } RESET_REASON;
99
100 // Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h
101 _Static_assert((soc_reset_reason_t)POWERON_RESET == RESET_REASON_CHIP_POWER_ON, "POWERON_RESET != RESET_REASON_CHIP_POWER_ON");
102 _Static_assert((soc_reset_reason_t)RTC_SW_SYS_RESET == RESET_REASON_CORE_SW, "RTC_SW_SYS_RESET != RESET_REASON_CORE_SW");
103 _Static_assert((soc_reset_reason_t)DEEPSLEEP_RESET == RESET_REASON_CORE_DEEP_SLEEP, "DEEPSLEEP_RESET != RESET_REASON_CORE_DEEP_SLEEP");
104 _Static_assert((soc_reset_reason_t)TG0WDT_SYS_RESET == RESET_REASON_CORE_MWDT0, "TG0WDT_SYS_RESET != RESET_REASON_CORE_MWDT0");
105 _Static_assert((soc_reset_reason_t)TG1WDT_SYS_RESET == RESET_REASON_CORE_MWDT1, "TG1WDT_SYS_RESET != RESET_REASON_CORE_MWDT1");
106 _Static_assert((soc_reset_reason_t)RTCWDT_SYS_RESET == RESET_REASON_CORE_RTC_WDT, "RTCWDT_SYS_RESET != RESET_REASON_CORE_RTC_WDT");
107 _Static_assert((soc_reset_reason_t)TG0WDT_CPU_RESET == RESET_REASON_CPU0_MWDT0, "TG0WDT_CPU_RESET != RESET_REASON_CPU0_MWDT0");
108 _Static_assert((soc_reset_reason_t)RTC_SW_CPU_RESET == RESET_REASON_CPU0_SW, "RTC_SW_CPU_RESET != RESET_REASON_CPU0_SW");
109 _Static_assert((soc_reset_reason_t)RTCWDT_CPU_RESET == RESET_REASON_CPU0_RTC_WDT, "RTCWDT_CPU_RESET != RESET_REASON_CPU0_RTC_WDT");
110 _Static_assert((soc_reset_reason_t)RTCWDT_BROWN_OUT_RESET == RESET_REASON_SYS_BROWN_OUT, "RTCWDT_BROWN_OUT_RESET != RESET_REASON_SYS_BROWN_OUT");
111 _Static_assert((soc_reset_reason_t)RTCWDT_RTC_RESET == RESET_REASON_SYS_RTC_WDT, "RTCWDT_RTC_RESET != RESET_REASON_SYS_RTC_WDT");
112 _Static_assert((soc_reset_reason_t)TG1WDT_CPU_RESET == RESET_REASON_CPU0_MWDT1, "TG1WDT_CPU_RESET != RESET_REASON_CPU0_MWDT1");
113 _Static_assert((soc_reset_reason_t)SUPER_WDT_RESET == RESET_REASON_SYS_SUPER_WDT, "SUPER_WDT_RESET != RESET_REASON_SYS_SUPER_WDT");
114 _Static_assert((soc_reset_reason_t)GLITCH_RTC_RESET == RESET_REASON_SYS_CLK_GLITCH, "GLITCH_RTC_RESET != RESET_REASON_SYS_CLK_GLITCH");
115 _Static_assert((soc_reset_reason_t)EFUSE_RESET == RESET_REASON_CORE_EFUSE_CRC, "EFUSE_RESET != RESET_REASON_CORE_EFUSE_CRC");
116 _Static_assert((soc_reset_reason_t)USB_UART_CHIP_RESET == RESET_REASON_CORE_USB_UART, "USB_UART_CHIP_RESET != RESET_REASON_CORE_USB_UART");
117 _Static_assert((soc_reset_reason_t)USB_JTAG_CHIP_RESET == RESET_REASON_CORE_USB_JTAG, "USB_JTAG_CHIP_RESET != RESET_REASON_CORE_USB_JTAG");
118 _Static_assert((soc_reset_reason_t)POWER_GLITCH_RESET == RESET_REASON_CORE_PWR_GLITCH, "POWER_GLITCH_RESET != RESET_REASON_CORE_PWR_GLITCH");
119 _Static_assert((soc_reset_reason_t)JTAG_RESET == RESET_REASON_CPU0_JTAG, "JTAG_RESET != RESET_REASON_CPU0_JTAG");
120
121 typedef enum {
122 NO_SLEEP = 0,
123 EXT_EVENT0_TRIG = BIT0,
124 EXT_EVENT1_TRIG = BIT1,
125 GPIO_TRIG = BIT2,
126 TIMER_EXPIRE = BIT3,
127 SDIO_TRIG = BIT4,
128 MAC_TRIG = BIT5,
129 UART0_TRIG = BIT6,
130 UART1_TRIG = BIT7,
131 TOUCH_TRIG = BIT8,
132 SAR_TRIG = BIT9,
133 BT_TRIG = BIT10,
134 RISCV_TRIG = BIT11,
135 XTAL_DEAD_TRIG = BIT12,
136 RISCV_TRAP_TRIG = BIT13,
137 USB_TRIG = BIT14
138 } WAKEUP_REASON;
139
140 typedef enum {
141 DISEN_WAKEUP = NO_SLEEP,
142 EXT_EVENT0_TRIG_EN = EXT_EVENT0_TRIG,
143 EXT_EVENT1_TRIG_EN = EXT_EVENT1_TRIG,
144 GPIO_TRIG_EN = GPIO_TRIG,
145 TIMER_EXPIRE_EN = TIMER_EXPIRE,
146 SDIO_TRIG_EN = SDIO_TRIG,
147 MAC_TRIG_EN = MAC_TRIG,
148 UART0_TRIG_EN = UART0_TRIG,
149 UART1_TRIG_EN = UART1_TRIG,
150 TOUCH_TRIG_EN = TOUCH_TRIG,
151 SAR_TRIG_EN = SAR_TRIG,
152 BT_TRIG_EN = BT_TRIG,
153 RISCV_TRIG_EN = RISCV_TRIG,
154 XTAL_DEAD_TRIG_EN = XTAL_DEAD_TRIG,
155 RISCV_TRAP_TRIG_EN = RISCV_TRAP_TRIG,
156 USB_TRIG_EN = USB_TRIG
157 } WAKEUP_ENABLE;
158
159 /**
160 * @brief Get the reset reason for CPU.
161 *
162 * @param int cpu_no : CPU no.
163 *
164 * @return RESET_REASON
165 */
166 RESET_REASON rtc_get_reset_reason(int cpu_no);
167
168 /**
169 * @brief Get the wakeup cause for CPU.
170 *
171 * @param int cpu_no : CPU no.
172 *
173 * @return WAKEUP_REASON
174 */
175 WAKEUP_REASON rtc_get_wakeup_cause(void);
176
177 /**
178 * @brief Get CRC for Fast RTC Memory.
179 *
180 * @param uint32_t start_addr : 0 - 0x7ff for Fast RTC Memory.
181 *
182 * @param uint32_t crc_len : 0 - 0x7ff, 0 for 4 byte, 0x7ff for 0x2000 byte.
183 *
184 * @return uint32_t : CRC32 result
185 */
186 uint32_t calc_rtc_memory_crc(uint32_t start_addr, uint32_t crc_len);
187
188 /**
189 * @brief Suppress ROM log by setting specific RTC control register.
190 * @note This is not a permanent disable of ROM logging since the RTC register can not retain after chip reset.
191 *
192 * @param None
193 *
194 * @return None
195 */
rtc_suppress_rom_log(void)196 static inline void rtc_suppress_rom_log(void)
197 {
198 /* To disable logging in the ROM, only the least significant bit of the register is used,
199 * but since this register is also used to store the frequency of the main crystal (RTC_XTAL_FREQ_REG),
200 * you need to write to this register in the same format.
201 * Namely, the upper 16 bits and lower should be the same.
202 */
203 REG_SET_BIT(RTC_CNTL_STORE4_REG, RTC_DISABLE_ROM_LOG);
204 }
205
206 /**
207 * @brief Set CRC of Fast RTC memory 0-0x7ff into RTC STORE7.
208 *
209 * @param None
210 *
211 * @return None
212 */
213 void set_rtc_memory_crc(void);
214
215 /**
216 * @brief Fetch entry from RTC memory and RTC STORE reg
217 *
218 * @param uint32_t * entry_addr : the address to save entry
219 *
220 * @param RESET_REASON reset_reason : reset reason this time
221 *
222 * @return None
223 */
224 void rtc_boot_control(uint32_t *entry_addr, RESET_REASON reset_reason);
225
226 /**
227 * @brief Software Reset digital core.
228 *
229 * It is not recommended to use this function in esp-idf, use
230 * esp_restart() instead.
231 *
232 * @param None
233 *
234 * @return None
235 */
236 void software_reset(void);
237
238 /**
239 * @brief Software Reset digital core.
240 *
241 * It is not recommended to use this function in esp-idf, use
242 * esp_restart() instead.
243 *
244 * @param int cpu_no : The CPU to reset, 0 for PRO CPU, 1 for APP CPU.
245 *
246 * @return None
247 */
248 void software_reset_cpu(int cpu_no);
249
250 /**
251 * @}
252 */
253
254 #ifdef __cplusplus
255 }
256 #endif
257
258 #endif /* _ROM_RTC_H_ */
259
