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Searched refs:NVMCTRL_SW0 (Results 1 – 25 of 27) sorted by relevance

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/hal_atmel-3.6.0/asf/sam0/include/same51/component/
Dnvmctrl.h615 #define AC_FUSES_BIAS0_ADDR NVMCTRL_SW0
620 #define ADC0_FUSES_BIASCOMP_ADDR NVMCTRL_SW0
625 #define ADC0_FUSES_BIASR2R_ADDR NVMCTRL_SW0
630 #define ADC0_FUSES_BIASREFBUF_ADDR NVMCTRL_SW0
635 #define ADC1_FUSES_BIASCOMP_ADDR NVMCTRL_SW0
640 #define ADC1_FUSES_BIASR2R_ADDR NVMCTRL_SW0
645 #define ADC1_FUSES_BIASREFBUF_ADDR NVMCTRL_SW0
743 #define USB_FUSES_TRANSN_ADDR (NVMCTRL_SW0 + 4)
748 #define USB_FUSES_TRANSP_ADDR (NVMCTRL_SW0 + 4)
753 #define USB_FUSES_TRIM_ADDR (NVMCTRL_SW0 + 4)
/hal_atmel-3.6.0/asf/sam0/include/samd51/component/
Dnvmctrl.h615 #define AC_FUSES_BIAS0_ADDR NVMCTRL_SW0
620 #define ADC0_FUSES_BIASCOMP_ADDR NVMCTRL_SW0
625 #define ADC0_FUSES_BIASR2R_ADDR NVMCTRL_SW0
630 #define ADC0_FUSES_BIASREFBUF_ADDR NVMCTRL_SW0
635 #define ADC1_FUSES_BIASCOMP_ADDR NVMCTRL_SW0
640 #define ADC1_FUSES_BIASR2R_ADDR NVMCTRL_SW0
645 #define ADC1_FUSES_BIASREFBUF_ADDR NVMCTRL_SW0
743 #define USB_FUSES_TRANSN_ADDR (NVMCTRL_SW0 + 4)
748 #define USB_FUSES_TRANSP_ADDR (NVMCTRL_SW0 + 4)
753 #define USB_FUSES_TRIM_ADDR (NVMCTRL_SW0 + 4)
/hal_atmel-3.6.0/asf/sam0/include/same53/component/
Dnvmctrl.h615 #define AC_FUSES_BIAS0_ADDR NVMCTRL_SW0
620 #define ADC0_FUSES_BIASCOMP_ADDR NVMCTRL_SW0
625 #define ADC0_FUSES_BIASR2R_ADDR NVMCTRL_SW0
630 #define ADC0_FUSES_BIASREFBUF_ADDR NVMCTRL_SW0
635 #define ADC1_FUSES_BIASCOMP_ADDR NVMCTRL_SW0
640 #define ADC1_FUSES_BIASR2R_ADDR NVMCTRL_SW0
645 #define ADC1_FUSES_BIASREFBUF_ADDR NVMCTRL_SW0
743 #define USB_FUSES_TRANSN_ADDR (NVMCTRL_SW0 + 4)
748 #define USB_FUSES_TRANSP_ADDR (NVMCTRL_SW0 + 4)
753 #define USB_FUSES_TRIM_ADDR (NVMCTRL_SW0 + 4)
/hal_atmel-3.6.0/asf/sam0/include/same54/component/
Dnvmctrl.h615 #define AC_FUSES_BIAS0_ADDR NVMCTRL_SW0
620 #define ADC0_FUSES_BIASCOMP_ADDR NVMCTRL_SW0
625 #define ADC0_FUSES_BIASR2R_ADDR NVMCTRL_SW0
630 #define ADC0_FUSES_BIASREFBUF_ADDR NVMCTRL_SW0
635 #define ADC1_FUSES_BIASCOMP_ADDR NVMCTRL_SW0
640 #define ADC1_FUSES_BIASR2R_ADDR NVMCTRL_SW0
645 #define ADC1_FUSES_BIASREFBUF_ADDR NVMCTRL_SW0
743 #define USB_FUSES_TRANSN_ADDR (NVMCTRL_SW0 + 4)
748 #define USB_FUSES_TRANSP_ADDR (NVMCTRL_SW0 + 4)
753 #define USB_FUSES_TRIM_ADDR (NVMCTRL_SW0 + 4)
/hal_atmel-3.6.0/asf/sam0/include/samd51/
Dsamd51g18a.h719 #define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ macro
818 #define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ macro
Dsamd51g19a.h719 #define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ macro
818 #define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ macro
Dsamd51j18a.h749 #define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ macro
856 #define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ macro
Dsamd51j19a.h749 #define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ macro
856 #define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ macro
Dsamd51j20a.h749 #define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ macro
856 #define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ macro
Dsamd51n19a.h781 #define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ macro
893 #define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ macro
Dsamd51n20a.h781 #define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ macro
893 #define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ macro
Dsamd51p19a.h781 #define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ macro
893 #define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ macro
Dsamd51p20a.h781 #define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ macro
893 #define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ macro
/hal_atmel-3.6.0/asf/sam0/include/same51/
Dsame51j18a.h760 #define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ macro
872 #define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ macro
Dsame51j19a.h760 #define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ macro
872 #define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ macro
Dsame51j20a.h760 #define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ macro
872 #define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ macro
Dsame51n19a.h788 #define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ macro
904 #define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ macro
Dsame51n20a.h788 #define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ macro
904 #define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ macro
/hal_atmel-3.6.0/asf/sam0/include/same53/
Dsame53j18a.h755 #define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ macro
866 #define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ macro
Dsame53j19a.h755 #define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ macro
866 #define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ macro
Dsame53j20a.h755 #define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ macro
866 #define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ macro
Dsame53n20a.h787 #define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ macro
903 #define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ macro
/hal_atmel-3.6.0/asf/sam0/include/same54/
Dsame54n19a.h798 #define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ macro
919 #define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ macro
Dsame54n20a.h798 #define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ macro
919 #define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ macro
Dsame54p20a.h798 #define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ macro
919 #define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ macro

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