1 /** 2 * \file 3 * 4 * \brief Component description for NVMCTRL 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAME53_NVMCTRL_COMPONENT_ 31 #define _SAME53_NVMCTRL_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR NVMCTRL */ 35 /* ========================================================================== */ 36 /** \addtogroup SAME53_NVMCTRL Non-Volatile Memory Controller */ 37 /*@{*/ 38 39 #define NVMCTRL_U2409 40 #define REV_NVMCTRL 0x100 41 42 /* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint16_t :2; /*!< bit: 0.. 1 Reserved */ 47 uint16_t AUTOWS:1; /*!< bit: 2 Auto Wait State Enable */ 48 uint16_t SUSPEN:1; /*!< bit: 3 Suspend Enable */ 49 uint16_t WMODE:2; /*!< bit: 4.. 5 Write Mode */ 50 uint16_t PRM:2; /*!< bit: 6.. 7 Power Reduction Mode during Sleep */ 51 uint16_t RWS:4; /*!< bit: 8..11 NVM Read Wait States */ 52 uint16_t AHBNS0:1; /*!< bit: 12 Force AHB0 access to NONSEQ, burst transfers are continuously rearbitrated */ 53 uint16_t AHBNS1:1; /*!< bit: 13 Force AHB1 access to NONSEQ, burst transfers are continuously rearbitrated */ 54 uint16_t CACHEDIS0:1; /*!< bit: 14 AHB0 Cache Disable */ 55 uint16_t CACHEDIS1:1; /*!< bit: 15 AHB1 Cache Disable */ 56 } bit; /*!< Structure used for bit access */ 57 uint16_t reg; /*!< Type used for register access */ 58 } NVMCTRL_CTRLA_Type; 59 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 60 61 #define NVMCTRL_CTRLA_OFFSET 0x00 /**< \brief (NVMCTRL_CTRLA offset) Control A */ 62 #define NVMCTRL_CTRLA_RESETVALUE _U_(0x0004) /**< \brief (NVMCTRL_CTRLA reset_value) Control A */ 63 64 #define NVMCTRL_CTRLA_AUTOWS_Pos 2 /**< \brief (NVMCTRL_CTRLA) Auto Wait State Enable */ 65 #define NVMCTRL_CTRLA_AUTOWS (_U_(0x1) << NVMCTRL_CTRLA_AUTOWS_Pos) 66 #define NVMCTRL_CTRLA_SUSPEN_Pos 3 /**< \brief (NVMCTRL_CTRLA) Suspend Enable */ 67 #define NVMCTRL_CTRLA_SUSPEN (_U_(0x1) << NVMCTRL_CTRLA_SUSPEN_Pos) 68 #define NVMCTRL_CTRLA_WMODE_Pos 4 /**< \brief (NVMCTRL_CTRLA) Write Mode */ 69 #define NVMCTRL_CTRLA_WMODE_Msk (_U_(0x3) << NVMCTRL_CTRLA_WMODE_Pos) 70 #define NVMCTRL_CTRLA_WMODE(value) (NVMCTRL_CTRLA_WMODE_Msk & ((value) << NVMCTRL_CTRLA_WMODE_Pos)) 71 #define NVMCTRL_CTRLA_WMODE_MAN_Val _U_(0x0) /**< \brief (NVMCTRL_CTRLA) Manual Write */ 72 #define NVMCTRL_CTRLA_WMODE_ADW_Val _U_(0x1) /**< \brief (NVMCTRL_CTRLA) Automatic Double Word Write */ 73 #define NVMCTRL_CTRLA_WMODE_AQW_Val _U_(0x2) /**< \brief (NVMCTRL_CTRLA) Automatic Quad Word */ 74 #define NVMCTRL_CTRLA_WMODE_AP_Val _U_(0x3) /**< \brief (NVMCTRL_CTRLA) Automatic Page Write */ 75 #define NVMCTRL_CTRLA_WMODE_MAN (NVMCTRL_CTRLA_WMODE_MAN_Val << NVMCTRL_CTRLA_WMODE_Pos) 76 #define NVMCTRL_CTRLA_WMODE_ADW (NVMCTRL_CTRLA_WMODE_ADW_Val << NVMCTRL_CTRLA_WMODE_Pos) 77 #define NVMCTRL_CTRLA_WMODE_AQW (NVMCTRL_CTRLA_WMODE_AQW_Val << NVMCTRL_CTRLA_WMODE_Pos) 78 #define NVMCTRL_CTRLA_WMODE_AP (NVMCTRL_CTRLA_WMODE_AP_Val << NVMCTRL_CTRLA_WMODE_Pos) 79 #define NVMCTRL_CTRLA_PRM_Pos 6 /**< \brief (NVMCTRL_CTRLA) Power Reduction Mode during Sleep */ 80 #define NVMCTRL_CTRLA_PRM_Msk (_U_(0x3) << NVMCTRL_CTRLA_PRM_Pos) 81 #define NVMCTRL_CTRLA_PRM(value) (NVMCTRL_CTRLA_PRM_Msk & ((value) << NVMCTRL_CTRLA_PRM_Pos)) 82 #define NVMCTRL_CTRLA_PRM_SEMIAUTO_Val _U_(0x0) /**< \brief (NVMCTRL_CTRLA) NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access. */ 83 #define NVMCTRL_CTRLA_PRM_FULLAUTO_Val _U_(0x1) /**< \brief (NVMCTRL_CTRLA) NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode when system is not in standby mode. */ 84 #define NVMCTRL_CTRLA_PRM_MANUAL_Val _U_(0x3) /**< \brief (NVMCTRL_CTRLA) NVM block does not enter low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access. */ 85 #define NVMCTRL_CTRLA_PRM_SEMIAUTO (NVMCTRL_CTRLA_PRM_SEMIAUTO_Val << NVMCTRL_CTRLA_PRM_Pos) 86 #define NVMCTRL_CTRLA_PRM_FULLAUTO (NVMCTRL_CTRLA_PRM_FULLAUTO_Val << NVMCTRL_CTRLA_PRM_Pos) 87 #define NVMCTRL_CTRLA_PRM_MANUAL (NVMCTRL_CTRLA_PRM_MANUAL_Val << NVMCTRL_CTRLA_PRM_Pos) 88 #define NVMCTRL_CTRLA_RWS_Pos 8 /**< \brief (NVMCTRL_CTRLA) NVM Read Wait States */ 89 #define NVMCTRL_CTRLA_RWS_Msk (_U_(0xF) << NVMCTRL_CTRLA_RWS_Pos) 90 #define NVMCTRL_CTRLA_RWS(value) (NVMCTRL_CTRLA_RWS_Msk & ((value) << NVMCTRL_CTRLA_RWS_Pos)) 91 #define NVMCTRL_CTRLA_AHBNS0_Pos 12 /**< \brief (NVMCTRL_CTRLA) Force AHB0 access to NONSEQ, burst transfers are continuously rearbitrated */ 92 #define NVMCTRL_CTRLA_AHBNS0 (_U_(0x1) << NVMCTRL_CTRLA_AHBNS0_Pos) 93 #define NVMCTRL_CTRLA_AHBNS1_Pos 13 /**< \brief (NVMCTRL_CTRLA) Force AHB1 access to NONSEQ, burst transfers are continuously rearbitrated */ 94 #define NVMCTRL_CTRLA_AHBNS1 (_U_(0x1) << NVMCTRL_CTRLA_AHBNS1_Pos) 95 #define NVMCTRL_CTRLA_CACHEDIS0_Pos 14 /**< \brief (NVMCTRL_CTRLA) AHB0 Cache Disable */ 96 #define NVMCTRL_CTRLA_CACHEDIS0 (_U_(0x1) << NVMCTRL_CTRLA_CACHEDIS0_Pos) 97 #define NVMCTRL_CTRLA_CACHEDIS1_Pos 15 /**< \brief (NVMCTRL_CTRLA) AHB1 Cache Disable */ 98 #define NVMCTRL_CTRLA_CACHEDIS1 (_U_(0x1) << NVMCTRL_CTRLA_CACHEDIS1_Pos) 99 #define NVMCTRL_CTRLA_MASK _U_(0xFFFC) /**< \brief (NVMCTRL_CTRLA) MASK Register */ 100 101 /* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) ( /W 16) Control B -------- */ 102 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 103 typedef union { 104 struct { 105 uint16_t CMD:7; /*!< bit: 0.. 6 Command */ 106 uint16_t :1; /*!< bit: 7 Reserved */ 107 uint16_t CMDEX:8; /*!< bit: 8..15 Command Execution */ 108 } bit; /*!< Structure used for bit access */ 109 uint16_t reg; /*!< Type used for register access */ 110 } NVMCTRL_CTRLB_Type; 111 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 112 113 #define NVMCTRL_CTRLB_OFFSET 0x04 /**< \brief (NVMCTRL_CTRLB offset) Control B */ 114 #define NVMCTRL_CTRLB_RESETVALUE _U_(0x0000) /**< \brief (NVMCTRL_CTRLB reset_value) Control B */ 115 116 #define NVMCTRL_CTRLB_CMD_Pos 0 /**< \brief (NVMCTRL_CTRLB) Command */ 117 #define NVMCTRL_CTRLB_CMD_Msk (_U_(0x7F) << NVMCTRL_CTRLB_CMD_Pos) 118 #define NVMCTRL_CTRLB_CMD(value) (NVMCTRL_CTRLB_CMD_Msk & ((value) << NVMCTRL_CTRLB_CMD_Pos)) 119 #define NVMCTRL_CTRLB_CMD_EP_Val _U_(0x0) /**< \brief (NVMCTRL_CTRLB) Erase Page - Only supported in the USER and AUX pages. */ 120 #define NVMCTRL_CTRLB_CMD_EB_Val _U_(0x1) /**< \brief (NVMCTRL_CTRLB) Erase Block - Erases the block addressed by the ADDR register, not supported in the user page */ 121 #define NVMCTRL_CTRLB_CMD_WP_Val _U_(0x3) /**< \brief (NVMCTRL_CTRLB) Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register, not supported in the user page */ 122 #define NVMCTRL_CTRLB_CMD_WQW_Val _U_(0x4) /**< \brief (NVMCTRL_CTRLB) Write Quad Word - Writes a 128-bit word at the location addressed by the ADDR register. */ 123 #define NVMCTRL_CTRLB_CMD_SWRST_Val _U_(0x10) /**< \brief (NVMCTRL_CTRLB) Software Reset - Power-Cycle the NVM memory and replay the device automatic calibration procedure and resets the module configuration registers */ 124 #define NVMCTRL_CTRLB_CMD_LR_Val _U_(0x11) /**< \brief (NVMCTRL_CTRLB) Lock Region - Locks the region containing the address location in the ADDR register. */ 125 #define NVMCTRL_CTRLB_CMD_UR_Val _U_(0x12) /**< \brief (NVMCTRL_CTRLB) Unlock Region - Unlocks the region containing the address location in the ADDR register. */ 126 #define NVMCTRL_CTRLB_CMD_SPRM_Val _U_(0x13) /**< \brief (NVMCTRL_CTRLB) Sets the power reduction mode. */ 127 #define NVMCTRL_CTRLB_CMD_CPRM_Val _U_(0x14) /**< \brief (NVMCTRL_CTRLB) Clears the power reduction mode. */ 128 #define NVMCTRL_CTRLB_CMD_PBC_Val _U_(0x15) /**< \brief (NVMCTRL_CTRLB) Page Buffer Clear - Clears the page buffer. */ 129 #define NVMCTRL_CTRLB_CMD_SSB_Val _U_(0x16) /**< \brief (NVMCTRL_CTRLB) Set Security Bit */ 130 #define NVMCTRL_CTRLB_CMD_BKSWRST_Val _U_(0x17) /**< \brief (NVMCTRL_CTRLB) Bank swap and system reset, if SMEE is used also reallocate SMEE data into the opposite BANK */ 131 #define NVMCTRL_CTRLB_CMD_CELCK_Val _U_(0x18) /**< \brief (NVMCTRL_CTRLB) Chip Erase Lock - DSU.CE command is not available */ 132 #define NVMCTRL_CTRLB_CMD_CEULCK_Val _U_(0x19) /**< \brief (NVMCTRL_CTRLB) Chip Erase Unlock - DSU.CE command is available */ 133 #define NVMCTRL_CTRLB_CMD_SBPDIS_Val _U_(0x1A) /**< \brief (NVMCTRL_CTRLB) Sets STATUS.BPDIS, Boot loader protection is discarded until CBPDIS is issued or next start-up sequence */ 134 #define NVMCTRL_CTRLB_CMD_CBPDIS_Val _U_(0x1B) /**< \brief (NVMCTRL_CTRLB) Clears STATUS.BPDIS, Boot loader protection is not discarded */ 135 #define NVMCTRL_CTRLB_CMD_ASEES0_Val _U_(0x30) /**< \brief (NVMCTRL_CTRLB) Activate SmartEEPROM Sector 0, deactivate Sector 1 */ 136 #define NVMCTRL_CTRLB_CMD_ASEES1_Val _U_(0x31) /**< \brief (NVMCTRL_CTRLB) Activate SmartEEPROM Sector 1, deactivate Sector 0 */ 137 #define NVMCTRL_CTRLB_CMD_SEERALOC_Val _U_(0x32) /**< \brief (NVMCTRL_CTRLB) Starts SmartEEPROM sector reallocation algorithm */ 138 #define NVMCTRL_CTRLB_CMD_SEEFLUSH_Val _U_(0x33) /**< \brief (NVMCTRL_CTRLB) Flush SMEE data when in buffered mode */ 139 #define NVMCTRL_CTRLB_CMD_LSEE_Val _U_(0x34) /**< \brief (NVMCTRL_CTRLB) Lock access to SmartEEPROM data from any mean */ 140 #define NVMCTRL_CTRLB_CMD_USEE_Val _U_(0x35) /**< \brief (NVMCTRL_CTRLB) Unlock access to SmartEEPROM data */ 141 #define NVMCTRL_CTRLB_CMD_LSEER_Val _U_(0x36) /**< \brief (NVMCTRL_CTRLB) Lock access to the SmartEEPROM Register Address Space (above 64KB) */ 142 #define NVMCTRL_CTRLB_CMD_USEER_Val _U_(0x37) /**< \brief (NVMCTRL_CTRLB) Unlock access to the SmartEEPROM Register Address Space (above 64KB) */ 143 #define NVMCTRL_CTRLB_CMD_EP (NVMCTRL_CTRLB_CMD_EP_Val << NVMCTRL_CTRLB_CMD_Pos) 144 #define NVMCTRL_CTRLB_CMD_EB (NVMCTRL_CTRLB_CMD_EB_Val << NVMCTRL_CTRLB_CMD_Pos) 145 #define NVMCTRL_CTRLB_CMD_WP (NVMCTRL_CTRLB_CMD_WP_Val << NVMCTRL_CTRLB_CMD_Pos) 146 #define NVMCTRL_CTRLB_CMD_WQW (NVMCTRL_CTRLB_CMD_WQW_Val << NVMCTRL_CTRLB_CMD_Pos) 147 #define NVMCTRL_CTRLB_CMD_SWRST (NVMCTRL_CTRLB_CMD_SWRST_Val << NVMCTRL_CTRLB_CMD_Pos) 148 #define NVMCTRL_CTRLB_CMD_LR (NVMCTRL_CTRLB_CMD_LR_Val << NVMCTRL_CTRLB_CMD_Pos) 149 #define NVMCTRL_CTRLB_CMD_UR (NVMCTRL_CTRLB_CMD_UR_Val << NVMCTRL_CTRLB_CMD_Pos) 150 #define NVMCTRL_CTRLB_CMD_SPRM (NVMCTRL_CTRLB_CMD_SPRM_Val << NVMCTRL_CTRLB_CMD_Pos) 151 #define NVMCTRL_CTRLB_CMD_CPRM (NVMCTRL_CTRLB_CMD_CPRM_Val << NVMCTRL_CTRLB_CMD_Pos) 152 #define NVMCTRL_CTRLB_CMD_PBC (NVMCTRL_CTRLB_CMD_PBC_Val << NVMCTRL_CTRLB_CMD_Pos) 153 #define NVMCTRL_CTRLB_CMD_SSB (NVMCTRL_CTRLB_CMD_SSB_Val << NVMCTRL_CTRLB_CMD_Pos) 154 #define NVMCTRL_CTRLB_CMD_BKSWRST (NVMCTRL_CTRLB_CMD_BKSWRST_Val << NVMCTRL_CTRLB_CMD_Pos) 155 #define NVMCTRL_CTRLB_CMD_CELCK (NVMCTRL_CTRLB_CMD_CELCK_Val << NVMCTRL_CTRLB_CMD_Pos) 156 #define NVMCTRL_CTRLB_CMD_CEULCK (NVMCTRL_CTRLB_CMD_CEULCK_Val << NVMCTRL_CTRLB_CMD_Pos) 157 #define NVMCTRL_CTRLB_CMD_SBPDIS (NVMCTRL_CTRLB_CMD_SBPDIS_Val << NVMCTRL_CTRLB_CMD_Pos) 158 #define NVMCTRL_CTRLB_CMD_CBPDIS (NVMCTRL_CTRLB_CMD_CBPDIS_Val << NVMCTRL_CTRLB_CMD_Pos) 159 #define NVMCTRL_CTRLB_CMD_ASEES0 (NVMCTRL_CTRLB_CMD_ASEES0_Val << NVMCTRL_CTRLB_CMD_Pos) 160 #define NVMCTRL_CTRLB_CMD_ASEES1 (NVMCTRL_CTRLB_CMD_ASEES1_Val << NVMCTRL_CTRLB_CMD_Pos) 161 #define NVMCTRL_CTRLB_CMD_SEERALOC (NVMCTRL_CTRLB_CMD_SEERALOC_Val << NVMCTRL_CTRLB_CMD_Pos) 162 #define NVMCTRL_CTRLB_CMD_SEEFLUSH (NVMCTRL_CTRLB_CMD_SEEFLUSH_Val << NVMCTRL_CTRLB_CMD_Pos) 163 #define NVMCTRL_CTRLB_CMD_LSEE (NVMCTRL_CTRLB_CMD_LSEE_Val << NVMCTRL_CTRLB_CMD_Pos) 164 #define NVMCTRL_CTRLB_CMD_USEE (NVMCTRL_CTRLB_CMD_USEE_Val << NVMCTRL_CTRLB_CMD_Pos) 165 #define NVMCTRL_CTRLB_CMD_LSEER (NVMCTRL_CTRLB_CMD_LSEER_Val << NVMCTRL_CTRLB_CMD_Pos) 166 #define NVMCTRL_CTRLB_CMD_USEER (NVMCTRL_CTRLB_CMD_USEER_Val << NVMCTRL_CTRLB_CMD_Pos) 167 #define NVMCTRL_CTRLB_CMDEX_Pos 8 /**< \brief (NVMCTRL_CTRLB) Command Execution */ 168 #define NVMCTRL_CTRLB_CMDEX_Msk (_U_(0xFF) << NVMCTRL_CTRLB_CMDEX_Pos) 169 #define NVMCTRL_CTRLB_CMDEX(value) (NVMCTRL_CTRLB_CMDEX_Msk & ((value) << NVMCTRL_CTRLB_CMDEX_Pos)) 170 #define NVMCTRL_CTRLB_CMDEX_KEY_Val _U_(0xA5) /**< \brief (NVMCTRL_CTRLB) Execution Key */ 171 #define NVMCTRL_CTRLB_CMDEX_KEY (NVMCTRL_CTRLB_CMDEX_KEY_Val << NVMCTRL_CTRLB_CMDEX_Pos) 172 #define NVMCTRL_CTRLB_MASK _U_(0xFF7F) /**< \brief (NVMCTRL_CTRLB) MASK Register */ 173 174 /* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) (R/ 32) NVM Parameter -------- */ 175 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 176 typedef union { 177 struct { 178 uint32_t NVMP:16; /*!< bit: 0..15 NVM Pages */ 179 uint32_t PSZ:3; /*!< bit: 16..18 Page Size */ 180 uint32_t :12; /*!< bit: 19..30 Reserved */ 181 uint32_t SEE:1; /*!< bit: 31 SmartEEPROM Supported */ 182 } bit; /*!< Structure used for bit access */ 183 uint32_t reg; /*!< Type used for register access */ 184 } NVMCTRL_PARAM_Type; 185 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 186 187 #define NVMCTRL_PARAM_OFFSET 0x08 /**< \brief (NVMCTRL_PARAM offset) NVM Parameter */ 188 #define NVMCTRL_PARAM_RESETVALUE _U_(0x00060000) /**< \brief (NVMCTRL_PARAM reset_value) NVM Parameter */ 189 190 #define NVMCTRL_PARAM_NVMP_Pos 0 /**< \brief (NVMCTRL_PARAM) NVM Pages */ 191 #define NVMCTRL_PARAM_NVMP_Msk (_U_(0xFFFF) << NVMCTRL_PARAM_NVMP_Pos) 192 #define NVMCTRL_PARAM_NVMP(value) (NVMCTRL_PARAM_NVMP_Msk & ((value) << NVMCTRL_PARAM_NVMP_Pos)) 193 #define NVMCTRL_PARAM_PSZ_Pos 16 /**< \brief (NVMCTRL_PARAM) Page Size */ 194 #define NVMCTRL_PARAM_PSZ_Msk (_U_(0x7) << NVMCTRL_PARAM_PSZ_Pos) 195 #define NVMCTRL_PARAM_PSZ(value) (NVMCTRL_PARAM_PSZ_Msk & ((value) << NVMCTRL_PARAM_PSZ_Pos)) 196 #define NVMCTRL_PARAM_PSZ_8_Val _U_(0x0) /**< \brief (NVMCTRL_PARAM) 8 bytes */ 197 #define NVMCTRL_PARAM_PSZ_16_Val _U_(0x1) /**< \brief (NVMCTRL_PARAM) 16 bytes */ 198 #define NVMCTRL_PARAM_PSZ_32_Val _U_(0x2) /**< \brief (NVMCTRL_PARAM) 32 bytes */ 199 #define NVMCTRL_PARAM_PSZ_64_Val _U_(0x3) /**< \brief (NVMCTRL_PARAM) 64 bytes */ 200 #define NVMCTRL_PARAM_PSZ_128_Val _U_(0x4) /**< \brief (NVMCTRL_PARAM) 128 bytes */ 201 #define NVMCTRL_PARAM_PSZ_256_Val _U_(0x5) /**< \brief (NVMCTRL_PARAM) 256 bytes */ 202 #define NVMCTRL_PARAM_PSZ_512_Val _U_(0x6) /**< \brief (NVMCTRL_PARAM) 512 bytes */ 203 #define NVMCTRL_PARAM_PSZ_1024_Val _U_(0x7) /**< \brief (NVMCTRL_PARAM) 1024 bytes */ 204 #define NVMCTRL_PARAM_PSZ_8 (NVMCTRL_PARAM_PSZ_8_Val << NVMCTRL_PARAM_PSZ_Pos) 205 #define NVMCTRL_PARAM_PSZ_16 (NVMCTRL_PARAM_PSZ_16_Val << NVMCTRL_PARAM_PSZ_Pos) 206 #define NVMCTRL_PARAM_PSZ_32 (NVMCTRL_PARAM_PSZ_32_Val << NVMCTRL_PARAM_PSZ_Pos) 207 #define NVMCTRL_PARAM_PSZ_64 (NVMCTRL_PARAM_PSZ_64_Val << NVMCTRL_PARAM_PSZ_Pos) 208 #define NVMCTRL_PARAM_PSZ_128 (NVMCTRL_PARAM_PSZ_128_Val << NVMCTRL_PARAM_PSZ_Pos) 209 #define NVMCTRL_PARAM_PSZ_256 (NVMCTRL_PARAM_PSZ_256_Val << NVMCTRL_PARAM_PSZ_Pos) 210 #define NVMCTRL_PARAM_PSZ_512 (NVMCTRL_PARAM_PSZ_512_Val << NVMCTRL_PARAM_PSZ_Pos) 211 #define NVMCTRL_PARAM_PSZ_1024 (NVMCTRL_PARAM_PSZ_1024_Val << NVMCTRL_PARAM_PSZ_Pos) 212 #define NVMCTRL_PARAM_SEE_Pos 31 /**< \brief (NVMCTRL_PARAM) SmartEEPROM Supported */ 213 #define NVMCTRL_PARAM_SEE (_U_(0x1) << NVMCTRL_PARAM_SEE_Pos) 214 #define NVMCTRL_PARAM_MASK _U_(0x8007FFFF) /**< \brief (NVMCTRL_PARAM) MASK Register */ 215 216 /* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W 16) Interrupt Enable Clear -------- */ 217 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 218 typedef union { 219 struct { 220 uint16_t DONE:1; /*!< bit: 0 Command Done Interrupt Clear */ 221 uint16_t ADDRE:1; /*!< bit: 1 Address Error */ 222 uint16_t PROGE:1; /*!< bit: 2 Programming Error Interrupt Clear */ 223 uint16_t LOCKE:1; /*!< bit: 3 Lock Error Interrupt Clear */ 224 uint16_t ECCSE:1; /*!< bit: 4 ECC Single Error Interrupt Clear */ 225 uint16_t ECCDE:1; /*!< bit: 5 ECC Dual Error Interrupt Clear */ 226 uint16_t NVME:1; /*!< bit: 6 NVM Error Interrupt Clear */ 227 uint16_t SUSP:1; /*!< bit: 7 Suspended Write Or Erase Interrupt Clear */ 228 uint16_t SEESFULL:1; /*!< bit: 8 Active SEES Full Interrupt Clear */ 229 uint16_t SEESOVF:1; /*!< bit: 9 Active SEES Overflow Interrupt Clear */ 230 uint16_t SEEWRC:1; /*!< bit: 10 SEE Write Completed Interrupt Clear */ 231 uint16_t :5; /*!< bit: 11..15 Reserved */ 232 } bit; /*!< Structure used for bit access */ 233 uint16_t reg; /*!< Type used for register access */ 234 } NVMCTRL_INTENCLR_Type; 235 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 236 237 #define NVMCTRL_INTENCLR_OFFSET 0x0C /**< \brief (NVMCTRL_INTENCLR offset) Interrupt Enable Clear */ 238 #define NVMCTRL_INTENCLR_RESETVALUE _U_(0x0000) /**< \brief (NVMCTRL_INTENCLR reset_value) Interrupt Enable Clear */ 239 240 #define NVMCTRL_INTENCLR_DONE_Pos 0 /**< \brief (NVMCTRL_INTENCLR) Command Done Interrupt Clear */ 241 #define NVMCTRL_INTENCLR_DONE (_U_(0x1) << NVMCTRL_INTENCLR_DONE_Pos) 242 #define NVMCTRL_INTENCLR_ADDRE_Pos 1 /**< \brief (NVMCTRL_INTENCLR) Address Error */ 243 #define NVMCTRL_INTENCLR_ADDRE (_U_(0x1) << NVMCTRL_INTENCLR_ADDRE_Pos) 244 #define NVMCTRL_INTENCLR_PROGE_Pos 2 /**< \brief (NVMCTRL_INTENCLR) Programming Error Interrupt Clear */ 245 #define NVMCTRL_INTENCLR_PROGE (_U_(0x1) << NVMCTRL_INTENCLR_PROGE_Pos) 246 #define NVMCTRL_INTENCLR_LOCKE_Pos 3 /**< \brief (NVMCTRL_INTENCLR) Lock Error Interrupt Clear */ 247 #define NVMCTRL_INTENCLR_LOCKE (_U_(0x1) << NVMCTRL_INTENCLR_LOCKE_Pos) 248 #define NVMCTRL_INTENCLR_ECCSE_Pos 4 /**< \brief (NVMCTRL_INTENCLR) ECC Single Error Interrupt Clear */ 249 #define NVMCTRL_INTENCLR_ECCSE (_U_(0x1) << NVMCTRL_INTENCLR_ECCSE_Pos) 250 #define NVMCTRL_INTENCLR_ECCDE_Pos 5 /**< \brief (NVMCTRL_INTENCLR) ECC Dual Error Interrupt Clear */ 251 #define NVMCTRL_INTENCLR_ECCDE (_U_(0x1) << NVMCTRL_INTENCLR_ECCDE_Pos) 252 #define NVMCTRL_INTENCLR_NVME_Pos 6 /**< \brief (NVMCTRL_INTENCLR) NVM Error Interrupt Clear */ 253 #define NVMCTRL_INTENCLR_NVME (_U_(0x1) << NVMCTRL_INTENCLR_NVME_Pos) 254 #define NVMCTRL_INTENCLR_SUSP_Pos 7 /**< \brief (NVMCTRL_INTENCLR) Suspended Write Or Erase Interrupt Clear */ 255 #define NVMCTRL_INTENCLR_SUSP (_U_(0x1) << NVMCTRL_INTENCLR_SUSP_Pos) 256 #define NVMCTRL_INTENCLR_SEESFULL_Pos 8 /**< \brief (NVMCTRL_INTENCLR) Active SEES Full Interrupt Clear */ 257 #define NVMCTRL_INTENCLR_SEESFULL (_U_(0x1) << NVMCTRL_INTENCLR_SEESFULL_Pos) 258 #define NVMCTRL_INTENCLR_SEESOVF_Pos 9 /**< \brief (NVMCTRL_INTENCLR) Active SEES Overflow Interrupt Clear */ 259 #define NVMCTRL_INTENCLR_SEESOVF (_U_(0x1) << NVMCTRL_INTENCLR_SEESOVF_Pos) 260 #define NVMCTRL_INTENCLR_SEEWRC_Pos 10 /**< \brief (NVMCTRL_INTENCLR) SEE Write Completed Interrupt Clear */ 261 #define NVMCTRL_INTENCLR_SEEWRC (_U_(0x1) << NVMCTRL_INTENCLR_SEEWRC_Pos) 262 #define NVMCTRL_INTENCLR_MASK _U_(0x07FF) /**< \brief (NVMCTRL_INTENCLR) MASK Register */ 263 264 /* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x0E) (R/W 16) Interrupt Enable Set -------- */ 265 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 266 typedef union { 267 struct { 268 uint16_t DONE:1; /*!< bit: 0 Command Done Interrupt Enable */ 269 uint16_t ADDRE:1; /*!< bit: 1 Address Error Interrupt Enable */ 270 uint16_t PROGE:1; /*!< bit: 2 Programming Error Interrupt Enable */ 271 uint16_t LOCKE:1; /*!< bit: 3 Lock Error Interrupt Enable */ 272 uint16_t ECCSE:1; /*!< bit: 4 ECC Single Error Interrupt Enable */ 273 uint16_t ECCDE:1; /*!< bit: 5 ECC Dual Error Interrupt Enable */ 274 uint16_t NVME:1; /*!< bit: 6 NVM Error Interrupt Enable */ 275 uint16_t SUSP:1; /*!< bit: 7 Suspended Write Or Erase Interrupt Enable */ 276 uint16_t SEESFULL:1; /*!< bit: 8 Active SEES Full Interrupt Enable */ 277 uint16_t SEESOVF:1; /*!< bit: 9 Active SEES Overflow Interrupt Enable */ 278 uint16_t SEEWRC:1; /*!< bit: 10 SEE Write Completed Interrupt Enable */ 279 uint16_t :5; /*!< bit: 11..15 Reserved */ 280 } bit; /*!< Structure used for bit access */ 281 uint16_t reg; /*!< Type used for register access */ 282 } NVMCTRL_INTENSET_Type; 283 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 284 285 #define NVMCTRL_INTENSET_OFFSET 0x0E /**< \brief (NVMCTRL_INTENSET offset) Interrupt Enable Set */ 286 #define NVMCTRL_INTENSET_RESETVALUE _U_(0x0000) /**< \brief (NVMCTRL_INTENSET reset_value) Interrupt Enable Set */ 287 288 #define NVMCTRL_INTENSET_DONE_Pos 0 /**< \brief (NVMCTRL_INTENSET) Command Done Interrupt Enable */ 289 #define NVMCTRL_INTENSET_DONE (_U_(0x1) << NVMCTRL_INTENSET_DONE_Pos) 290 #define NVMCTRL_INTENSET_ADDRE_Pos 1 /**< \brief (NVMCTRL_INTENSET) Address Error Interrupt Enable */ 291 #define NVMCTRL_INTENSET_ADDRE (_U_(0x1) << NVMCTRL_INTENSET_ADDRE_Pos) 292 #define NVMCTRL_INTENSET_PROGE_Pos 2 /**< \brief (NVMCTRL_INTENSET) Programming Error Interrupt Enable */ 293 #define NVMCTRL_INTENSET_PROGE (_U_(0x1) << NVMCTRL_INTENSET_PROGE_Pos) 294 #define NVMCTRL_INTENSET_LOCKE_Pos 3 /**< \brief (NVMCTRL_INTENSET) Lock Error Interrupt Enable */ 295 #define NVMCTRL_INTENSET_LOCKE (_U_(0x1) << NVMCTRL_INTENSET_LOCKE_Pos) 296 #define NVMCTRL_INTENSET_ECCSE_Pos 4 /**< \brief (NVMCTRL_INTENSET) ECC Single Error Interrupt Enable */ 297 #define NVMCTRL_INTENSET_ECCSE (_U_(0x1) << NVMCTRL_INTENSET_ECCSE_Pos) 298 #define NVMCTRL_INTENSET_ECCDE_Pos 5 /**< \brief (NVMCTRL_INTENSET) ECC Dual Error Interrupt Enable */ 299 #define NVMCTRL_INTENSET_ECCDE (_U_(0x1) << NVMCTRL_INTENSET_ECCDE_Pos) 300 #define NVMCTRL_INTENSET_NVME_Pos 6 /**< \brief (NVMCTRL_INTENSET) NVM Error Interrupt Enable */ 301 #define NVMCTRL_INTENSET_NVME (_U_(0x1) << NVMCTRL_INTENSET_NVME_Pos) 302 #define NVMCTRL_INTENSET_SUSP_Pos 7 /**< \brief (NVMCTRL_INTENSET) Suspended Write Or Erase Interrupt Enable */ 303 #define NVMCTRL_INTENSET_SUSP (_U_(0x1) << NVMCTRL_INTENSET_SUSP_Pos) 304 #define NVMCTRL_INTENSET_SEESFULL_Pos 8 /**< \brief (NVMCTRL_INTENSET) Active SEES Full Interrupt Enable */ 305 #define NVMCTRL_INTENSET_SEESFULL (_U_(0x1) << NVMCTRL_INTENSET_SEESFULL_Pos) 306 #define NVMCTRL_INTENSET_SEESOVF_Pos 9 /**< \brief (NVMCTRL_INTENSET) Active SEES Overflow Interrupt Enable */ 307 #define NVMCTRL_INTENSET_SEESOVF (_U_(0x1) << NVMCTRL_INTENSET_SEESOVF_Pos) 308 #define NVMCTRL_INTENSET_SEEWRC_Pos 10 /**< \brief (NVMCTRL_INTENSET) SEE Write Completed Interrupt Enable */ 309 #define NVMCTRL_INTENSET_SEEWRC (_U_(0x1) << NVMCTRL_INTENSET_SEEWRC_Pos) 310 #define NVMCTRL_INTENSET_MASK _U_(0x07FF) /**< \brief (NVMCTRL_INTENSET) MASK Register */ 311 312 /* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x10) (R/W 16) Interrupt Flag Status and Clear -------- */ 313 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 314 typedef union { // __I to avoid read-modify-write on write-to-clear register 315 struct { 316 __I uint16_t DONE:1; /*!< bit: 0 Command Done */ 317 __I uint16_t ADDRE:1; /*!< bit: 1 Address Error */ 318 __I uint16_t PROGE:1; /*!< bit: 2 Programming Error */ 319 __I uint16_t LOCKE:1; /*!< bit: 3 Lock Error */ 320 __I uint16_t ECCSE:1; /*!< bit: 4 ECC Single Error */ 321 __I uint16_t ECCDE:1; /*!< bit: 5 ECC Dual Error */ 322 __I uint16_t NVME:1; /*!< bit: 6 NVM Error */ 323 __I uint16_t SUSP:1; /*!< bit: 7 Suspended Write Or Erase Operation */ 324 __I uint16_t SEESFULL:1; /*!< bit: 8 Active SEES Full */ 325 __I uint16_t SEESOVF:1; /*!< bit: 9 Active SEES Overflow */ 326 __I uint16_t SEEWRC:1; /*!< bit: 10 SEE Write Completed */ 327 __I uint16_t :5; /*!< bit: 11..15 Reserved */ 328 } bit; /*!< Structure used for bit access */ 329 uint16_t reg; /*!< Type used for register access */ 330 } NVMCTRL_INTFLAG_Type; 331 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 332 333 #define NVMCTRL_INTFLAG_OFFSET 0x10 /**< \brief (NVMCTRL_INTFLAG offset) Interrupt Flag Status and Clear */ 334 #define NVMCTRL_INTFLAG_RESETVALUE _U_(0x0000) /**< \brief (NVMCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */ 335 336 #define NVMCTRL_INTFLAG_DONE_Pos 0 /**< \brief (NVMCTRL_INTFLAG) Command Done */ 337 #define NVMCTRL_INTFLAG_DONE (_U_(0x1) << NVMCTRL_INTFLAG_DONE_Pos) 338 #define NVMCTRL_INTFLAG_ADDRE_Pos 1 /**< \brief (NVMCTRL_INTFLAG) Address Error */ 339 #define NVMCTRL_INTFLAG_ADDRE (_U_(0x1) << NVMCTRL_INTFLAG_ADDRE_Pos) 340 #define NVMCTRL_INTFLAG_PROGE_Pos 2 /**< \brief (NVMCTRL_INTFLAG) Programming Error */ 341 #define NVMCTRL_INTFLAG_PROGE (_U_(0x1) << NVMCTRL_INTFLAG_PROGE_Pos) 342 #define NVMCTRL_INTFLAG_LOCKE_Pos 3 /**< \brief (NVMCTRL_INTFLAG) Lock Error */ 343 #define NVMCTRL_INTFLAG_LOCKE (_U_(0x1) << NVMCTRL_INTFLAG_LOCKE_Pos) 344 #define NVMCTRL_INTFLAG_ECCSE_Pos 4 /**< \brief (NVMCTRL_INTFLAG) ECC Single Error */ 345 #define NVMCTRL_INTFLAG_ECCSE (_U_(0x1) << NVMCTRL_INTFLAG_ECCSE_Pos) 346 #define NVMCTRL_INTFLAG_ECCDE_Pos 5 /**< \brief (NVMCTRL_INTFLAG) ECC Dual Error */ 347 #define NVMCTRL_INTFLAG_ECCDE (_U_(0x1) << NVMCTRL_INTFLAG_ECCDE_Pos) 348 #define NVMCTRL_INTFLAG_NVME_Pos 6 /**< \brief (NVMCTRL_INTFLAG) NVM Error */ 349 #define NVMCTRL_INTFLAG_NVME (_U_(0x1) << NVMCTRL_INTFLAG_NVME_Pos) 350 #define NVMCTRL_INTFLAG_SUSP_Pos 7 /**< \brief (NVMCTRL_INTFLAG) Suspended Write Or Erase Operation */ 351 #define NVMCTRL_INTFLAG_SUSP (_U_(0x1) << NVMCTRL_INTFLAG_SUSP_Pos) 352 #define NVMCTRL_INTFLAG_SEESFULL_Pos 8 /**< \brief (NVMCTRL_INTFLAG) Active SEES Full */ 353 #define NVMCTRL_INTFLAG_SEESFULL (_U_(0x1) << NVMCTRL_INTFLAG_SEESFULL_Pos) 354 #define NVMCTRL_INTFLAG_SEESOVF_Pos 9 /**< \brief (NVMCTRL_INTFLAG) Active SEES Overflow */ 355 #define NVMCTRL_INTFLAG_SEESOVF (_U_(0x1) << NVMCTRL_INTFLAG_SEESOVF_Pos) 356 #define NVMCTRL_INTFLAG_SEEWRC_Pos 10 /**< \brief (NVMCTRL_INTFLAG) SEE Write Completed */ 357 #define NVMCTRL_INTFLAG_SEEWRC (_U_(0x1) << NVMCTRL_INTFLAG_SEEWRC_Pos) 358 #define NVMCTRL_INTFLAG_MASK _U_(0x07FF) /**< \brief (NVMCTRL_INTFLAG) MASK Register */ 359 360 /* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x12) (R/ 16) Status -------- */ 361 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 362 typedef union { 363 struct { 364 uint16_t READY:1; /*!< bit: 0 Ready to accept a command */ 365 uint16_t PRM:1; /*!< bit: 1 Power Reduction Mode */ 366 uint16_t LOAD:1; /*!< bit: 2 NVM Page Buffer Active Loading */ 367 uint16_t SUSP:1; /*!< bit: 3 NVM Write Or Erase Operation Is Suspended */ 368 uint16_t AFIRST:1; /*!< bit: 4 BANKA First */ 369 uint16_t BPDIS:1; /*!< bit: 5 Boot Loader Protection Disable */ 370 uint16_t :2; /*!< bit: 6.. 7 Reserved */ 371 uint16_t BOOTPROT:4; /*!< bit: 8..11 Boot Loader Protection Size */ 372 uint16_t :4; /*!< bit: 12..15 Reserved */ 373 } bit; /*!< Structure used for bit access */ 374 uint16_t reg; /*!< Type used for register access */ 375 } NVMCTRL_STATUS_Type; 376 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 377 378 #define NVMCTRL_STATUS_OFFSET 0x12 /**< \brief (NVMCTRL_STATUS offset) Status */ 379 #define NVMCTRL_STATUS_RESETVALUE _U_(0x0000) /**< \brief (NVMCTRL_STATUS reset_value) Status */ 380 381 #define NVMCTRL_STATUS_READY_Pos 0 /**< \brief (NVMCTRL_STATUS) Ready to accept a command */ 382 #define NVMCTRL_STATUS_READY (_U_(0x1) << NVMCTRL_STATUS_READY_Pos) 383 #define NVMCTRL_STATUS_PRM_Pos 1 /**< \brief (NVMCTRL_STATUS) Power Reduction Mode */ 384 #define NVMCTRL_STATUS_PRM (_U_(0x1) << NVMCTRL_STATUS_PRM_Pos) 385 #define NVMCTRL_STATUS_LOAD_Pos 2 /**< \brief (NVMCTRL_STATUS) NVM Page Buffer Active Loading */ 386 #define NVMCTRL_STATUS_LOAD (_U_(0x1) << NVMCTRL_STATUS_LOAD_Pos) 387 #define NVMCTRL_STATUS_SUSP_Pos 3 /**< \brief (NVMCTRL_STATUS) NVM Write Or Erase Operation Is Suspended */ 388 #define NVMCTRL_STATUS_SUSP (_U_(0x1) << NVMCTRL_STATUS_SUSP_Pos) 389 #define NVMCTRL_STATUS_AFIRST_Pos 4 /**< \brief (NVMCTRL_STATUS) BANKA First */ 390 #define NVMCTRL_STATUS_AFIRST (_U_(0x1) << NVMCTRL_STATUS_AFIRST_Pos) 391 #define NVMCTRL_STATUS_BPDIS_Pos 5 /**< \brief (NVMCTRL_STATUS) Boot Loader Protection Disable */ 392 #define NVMCTRL_STATUS_BPDIS (_U_(0x1) << NVMCTRL_STATUS_BPDIS_Pos) 393 #define NVMCTRL_STATUS_BOOTPROT_Pos 8 /**< \brief (NVMCTRL_STATUS) Boot Loader Protection Size */ 394 #define NVMCTRL_STATUS_BOOTPROT_Msk (_U_(0xF) << NVMCTRL_STATUS_BOOTPROT_Pos) 395 #define NVMCTRL_STATUS_BOOTPROT(value) (NVMCTRL_STATUS_BOOTPROT_Msk & ((value) << NVMCTRL_STATUS_BOOTPROT_Pos)) 396 #define NVMCTRL_STATUS_MASK _U_(0x0F3F) /**< \brief (NVMCTRL_STATUS) MASK Register */ 397 398 /* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x14) (R/W 32) Address -------- */ 399 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 400 typedef union { 401 struct { 402 uint32_t ADDR:24; /*!< bit: 0..23 NVM Address */ 403 uint32_t :8; /*!< bit: 24..31 Reserved */ 404 } bit; /*!< Structure used for bit access */ 405 uint32_t reg; /*!< Type used for register access */ 406 } NVMCTRL_ADDR_Type; 407 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 408 409 #define NVMCTRL_ADDR_OFFSET 0x14 /**< \brief (NVMCTRL_ADDR offset) Address */ 410 #define NVMCTRL_ADDR_RESETVALUE _U_(0x00000000) /**< \brief (NVMCTRL_ADDR reset_value) Address */ 411 412 #define NVMCTRL_ADDR_ADDR_Pos 0 /**< \brief (NVMCTRL_ADDR) NVM Address */ 413 #define NVMCTRL_ADDR_ADDR_Msk (_U_(0xFFFFFF) << NVMCTRL_ADDR_ADDR_Pos) 414 #define NVMCTRL_ADDR_ADDR(value) (NVMCTRL_ADDR_ADDR_Msk & ((value) << NVMCTRL_ADDR_ADDR_Pos)) 415 #define NVMCTRL_ADDR_MASK _U_(0x00FFFFFF) /**< \brief (NVMCTRL_ADDR) MASK Register */ 416 417 /* -------- NVMCTRL_RUNLOCK : (NVMCTRL Offset: 0x18) (R/ 32) Lock Section -------- */ 418 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 419 typedef union { 420 struct { 421 uint32_t RUNLOCK:32; /*!< bit: 0..31 Region Un-Lock Bits */ 422 } bit; /*!< Structure used for bit access */ 423 uint32_t reg; /*!< Type used for register access */ 424 } NVMCTRL_RUNLOCK_Type; 425 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 426 427 #define NVMCTRL_RUNLOCK_OFFSET 0x18 /**< \brief (NVMCTRL_RUNLOCK offset) Lock Section */ 428 #define NVMCTRL_RUNLOCK_RESETVALUE _U_(0x00000000) /**< \brief (NVMCTRL_RUNLOCK reset_value) Lock Section */ 429 430 #define NVMCTRL_RUNLOCK_RUNLOCK_Pos 0 /**< \brief (NVMCTRL_RUNLOCK) Region Un-Lock Bits */ 431 #define NVMCTRL_RUNLOCK_RUNLOCK_Msk (_U_(0xFFFFFFFF) << NVMCTRL_RUNLOCK_RUNLOCK_Pos) 432 #define NVMCTRL_RUNLOCK_RUNLOCK(value) (NVMCTRL_RUNLOCK_RUNLOCK_Msk & ((value) << NVMCTRL_RUNLOCK_RUNLOCK_Pos)) 433 #define NVMCTRL_RUNLOCK_MASK _U_(0xFFFFFFFF) /**< \brief (NVMCTRL_RUNLOCK) MASK Register */ 434 435 /* -------- NVMCTRL_PBLDATA : (NVMCTRL Offset: 0x1C) (R/ 32) Page Buffer Load Data x -------- */ 436 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 437 typedef union { 438 struct { 439 uint32_t DATA:32; /*!< bit: 0..31 Page Buffer Data */ 440 } bit; /*!< Structure used for bit access */ 441 uint32_t reg; /*!< Type used for register access */ 442 } NVMCTRL_PBLDATA_Type; 443 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 444 445 #define NVMCTRL_PBLDATA_OFFSET 0x1C /**< \brief (NVMCTRL_PBLDATA offset) Page Buffer Load Data x */ 446 #define NVMCTRL_PBLDATA_RESETVALUE _U_(0xFFFFFFFF) /**< \brief (NVMCTRL_PBLDATA reset_value) Page Buffer Load Data x */ 447 448 #define NVMCTRL_PBLDATA_DATA_Pos 0 /**< \brief (NVMCTRL_PBLDATA) Page Buffer Data */ 449 #define NVMCTRL_PBLDATA_DATA_Msk (_U_(0xFFFFFFFF) << NVMCTRL_PBLDATA_DATA_Pos) 450 #define NVMCTRL_PBLDATA_DATA(value) (NVMCTRL_PBLDATA_DATA_Msk & ((value) << NVMCTRL_PBLDATA_DATA_Pos)) 451 #define NVMCTRL_PBLDATA_MASK _U_(0xFFFFFFFF) /**< \brief (NVMCTRL_PBLDATA) MASK Register */ 452 453 /* -------- NVMCTRL_ECCERR : (NVMCTRL Offset: 0x24) (R/ 32) ECC Error Status Register -------- */ 454 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 455 typedef union { 456 struct { 457 uint32_t ADDR:24; /*!< bit: 0..23 Error Address */ 458 uint32_t :4; /*!< bit: 24..27 Reserved */ 459 uint32_t TYPEL:2; /*!< bit: 28..29 Low Double-Word Error Type */ 460 uint32_t TYPEH:2; /*!< bit: 30..31 High Double-Word Error Type */ 461 } bit; /*!< Structure used for bit access */ 462 uint32_t reg; /*!< Type used for register access */ 463 } NVMCTRL_ECCERR_Type; 464 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 465 466 #define NVMCTRL_ECCERR_OFFSET 0x24 /**< \brief (NVMCTRL_ECCERR offset) ECC Error Status Register */ 467 #define NVMCTRL_ECCERR_RESETVALUE _U_(0x00000000) /**< \brief (NVMCTRL_ECCERR reset_value) ECC Error Status Register */ 468 469 #define NVMCTRL_ECCERR_ADDR_Pos 0 /**< \brief (NVMCTRL_ECCERR) Error Address */ 470 #define NVMCTRL_ECCERR_ADDR_Msk (_U_(0xFFFFFF) << NVMCTRL_ECCERR_ADDR_Pos) 471 #define NVMCTRL_ECCERR_ADDR(value) (NVMCTRL_ECCERR_ADDR_Msk & ((value) << NVMCTRL_ECCERR_ADDR_Pos)) 472 #define NVMCTRL_ECCERR_TYPEL_Pos 28 /**< \brief (NVMCTRL_ECCERR) Low Double-Word Error Type */ 473 #define NVMCTRL_ECCERR_TYPEL_Msk (_U_(0x3) << NVMCTRL_ECCERR_TYPEL_Pos) 474 #define NVMCTRL_ECCERR_TYPEL(value) (NVMCTRL_ECCERR_TYPEL_Msk & ((value) << NVMCTRL_ECCERR_TYPEL_Pos)) 475 #define NVMCTRL_ECCERR_TYPEL_NONE_Val _U_(0x0) /**< \brief (NVMCTRL_ECCERR) No Error Detected Since Last Read */ 476 #define NVMCTRL_ECCERR_TYPEL_SINGLE_Val _U_(0x1) /**< \brief (NVMCTRL_ECCERR) At Least One Single Error Detected Since last Read */ 477 #define NVMCTRL_ECCERR_TYPEL_DUAL_Val _U_(0x2) /**< \brief (NVMCTRL_ECCERR) At Least One Dual Error Detected Since Last Read */ 478 #define NVMCTRL_ECCERR_TYPEL_NONE (NVMCTRL_ECCERR_TYPEL_NONE_Val << NVMCTRL_ECCERR_TYPEL_Pos) 479 #define NVMCTRL_ECCERR_TYPEL_SINGLE (NVMCTRL_ECCERR_TYPEL_SINGLE_Val << NVMCTRL_ECCERR_TYPEL_Pos) 480 #define NVMCTRL_ECCERR_TYPEL_DUAL (NVMCTRL_ECCERR_TYPEL_DUAL_Val << NVMCTRL_ECCERR_TYPEL_Pos) 481 #define NVMCTRL_ECCERR_TYPEH_Pos 30 /**< \brief (NVMCTRL_ECCERR) High Double-Word Error Type */ 482 #define NVMCTRL_ECCERR_TYPEH_Msk (_U_(0x3) << NVMCTRL_ECCERR_TYPEH_Pos) 483 #define NVMCTRL_ECCERR_TYPEH(value) (NVMCTRL_ECCERR_TYPEH_Msk & ((value) << NVMCTRL_ECCERR_TYPEH_Pos)) 484 #define NVMCTRL_ECCERR_TYPEH_NONE_Val _U_(0x0) /**< \brief (NVMCTRL_ECCERR) No Error Detected Since Last Read */ 485 #define NVMCTRL_ECCERR_TYPEH_SINGLE_Val _U_(0x1) /**< \brief (NVMCTRL_ECCERR) At Least One Single Error Detected Since last Read */ 486 #define NVMCTRL_ECCERR_TYPEH_DUAL_Val _U_(0x2) /**< \brief (NVMCTRL_ECCERR) At Least One Dual Error Detected Since Last Read */ 487 #define NVMCTRL_ECCERR_TYPEH_NONE (NVMCTRL_ECCERR_TYPEH_NONE_Val << NVMCTRL_ECCERR_TYPEH_Pos) 488 #define NVMCTRL_ECCERR_TYPEH_SINGLE (NVMCTRL_ECCERR_TYPEH_SINGLE_Val << NVMCTRL_ECCERR_TYPEH_Pos) 489 #define NVMCTRL_ECCERR_TYPEH_DUAL (NVMCTRL_ECCERR_TYPEH_DUAL_Val << NVMCTRL_ECCERR_TYPEH_Pos) 490 #define NVMCTRL_ECCERR_MASK _U_(0xF0FFFFFF) /**< \brief (NVMCTRL_ECCERR) MASK Register */ 491 492 /* -------- NVMCTRL_DBGCTRL : (NVMCTRL Offset: 0x28) (R/W 8) Debug Control -------- */ 493 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 494 typedef union { 495 struct { 496 uint8_t ECCDIS:1; /*!< bit: 0 Debugger ECC Read Disable */ 497 uint8_t ECCELOG:1; /*!< bit: 1 Debugger ECC Error Tracking Mode */ 498 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 499 } bit; /*!< Structure used for bit access */ 500 uint8_t reg; /*!< Type used for register access */ 501 } NVMCTRL_DBGCTRL_Type; 502 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 503 504 #define NVMCTRL_DBGCTRL_OFFSET 0x28 /**< \brief (NVMCTRL_DBGCTRL offset) Debug Control */ 505 #define NVMCTRL_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (NVMCTRL_DBGCTRL reset_value) Debug Control */ 506 507 #define NVMCTRL_DBGCTRL_ECCDIS_Pos 0 /**< \brief (NVMCTRL_DBGCTRL) Debugger ECC Read Disable */ 508 #define NVMCTRL_DBGCTRL_ECCDIS (_U_(0x1) << NVMCTRL_DBGCTRL_ECCDIS_Pos) 509 #define NVMCTRL_DBGCTRL_ECCELOG_Pos 1 /**< \brief (NVMCTRL_DBGCTRL) Debugger ECC Error Tracking Mode */ 510 #define NVMCTRL_DBGCTRL_ECCELOG (_U_(0x1) << NVMCTRL_DBGCTRL_ECCELOG_Pos) 511 #define NVMCTRL_DBGCTRL_MASK _U_(0x03) /**< \brief (NVMCTRL_DBGCTRL) MASK Register */ 512 513 /* -------- NVMCTRL_SEECFG : (NVMCTRL Offset: 0x2A) (R/W 8) SmartEEPROM Configuration Register -------- */ 514 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 515 typedef union { 516 struct { 517 uint8_t WMODE:1; /*!< bit: 0 Write Mode */ 518 uint8_t APRDIS:1; /*!< bit: 1 Automatic Page Reallocation Disable */ 519 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 520 } bit; /*!< Structure used for bit access */ 521 uint8_t reg; /*!< Type used for register access */ 522 } NVMCTRL_SEECFG_Type; 523 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 524 525 #define NVMCTRL_SEECFG_OFFSET 0x2A /**< \brief (NVMCTRL_SEECFG offset) SmartEEPROM Configuration Register */ 526 #define NVMCTRL_SEECFG_RESETVALUE _U_(0x00) /**< \brief (NVMCTRL_SEECFG reset_value) SmartEEPROM Configuration Register */ 527 528 #define NVMCTRL_SEECFG_WMODE_Pos 0 /**< \brief (NVMCTRL_SEECFG) Write Mode */ 529 #define NVMCTRL_SEECFG_WMODE (_U_(0x1) << NVMCTRL_SEECFG_WMODE_Pos) 530 #define NVMCTRL_SEECFG_WMODE_UNBUFFERED_Val _U_(0x0) /**< \brief (NVMCTRL_SEECFG) A NVM write command is issued after each write in the pagebuffer */ 531 #define NVMCTRL_SEECFG_WMODE_BUFFERED_Val _U_(0x1) /**< \brief (NVMCTRL_SEECFG) A NVM write command is issued when a write to a new page is requested */ 532 #define NVMCTRL_SEECFG_WMODE_UNBUFFERED (NVMCTRL_SEECFG_WMODE_UNBUFFERED_Val << NVMCTRL_SEECFG_WMODE_Pos) 533 #define NVMCTRL_SEECFG_WMODE_BUFFERED (NVMCTRL_SEECFG_WMODE_BUFFERED_Val << NVMCTRL_SEECFG_WMODE_Pos) 534 #define NVMCTRL_SEECFG_APRDIS_Pos 1 /**< \brief (NVMCTRL_SEECFG) Automatic Page Reallocation Disable */ 535 #define NVMCTRL_SEECFG_APRDIS (_U_(0x1) << NVMCTRL_SEECFG_APRDIS_Pos) 536 #define NVMCTRL_SEECFG_MASK _U_(0x03) /**< \brief (NVMCTRL_SEECFG) MASK Register */ 537 538 /* -------- NVMCTRL_SEESTAT : (NVMCTRL Offset: 0x2C) (R/ 32) SmartEEPROM Status Register -------- */ 539 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 540 typedef union { 541 struct { 542 uint32_t ASEES:1; /*!< bit: 0 Active SmartEEPROM Sector */ 543 uint32_t LOAD:1; /*!< bit: 1 Page Buffer Loaded */ 544 uint32_t BUSY:1; /*!< bit: 2 Busy */ 545 uint32_t LOCK:1; /*!< bit: 3 SmartEEPROM Write Access Is Locked */ 546 uint32_t RLOCK:1; /*!< bit: 4 SmartEEPROM Write Access To Register Address Space Is Locked */ 547 uint32_t :3; /*!< bit: 5.. 7 Reserved */ 548 uint32_t SBLK:4; /*!< bit: 8..11 Blocks Number In a Sector */ 549 uint32_t :4; /*!< bit: 12..15 Reserved */ 550 uint32_t PSZ:3; /*!< bit: 16..18 SmartEEPROM Page Size */ 551 uint32_t :13; /*!< bit: 19..31 Reserved */ 552 } bit; /*!< Structure used for bit access */ 553 uint32_t reg; /*!< Type used for register access */ 554 } NVMCTRL_SEESTAT_Type; 555 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 556 557 #define NVMCTRL_SEESTAT_OFFSET 0x2C /**< \brief (NVMCTRL_SEESTAT offset) SmartEEPROM Status Register */ 558 #define NVMCTRL_SEESTAT_RESETVALUE _U_(0x00000000) /**< \brief (NVMCTRL_SEESTAT reset_value) SmartEEPROM Status Register */ 559 560 #define NVMCTRL_SEESTAT_ASEES_Pos 0 /**< \brief (NVMCTRL_SEESTAT) Active SmartEEPROM Sector */ 561 #define NVMCTRL_SEESTAT_ASEES (_U_(0x1) << NVMCTRL_SEESTAT_ASEES_Pos) 562 #define NVMCTRL_SEESTAT_LOAD_Pos 1 /**< \brief (NVMCTRL_SEESTAT) Page Buffer Loaded */ 563 #define NVMCTRL_SEESTAT_LOAD (_U_(0x1) << NVMCTRL_SEESTAT_LOAD_Pos) 564 #define NVMCTRL_SEESTAT_BUSY_Pos 2 /**< \brief (NVMCTRL_SEESTAT) Busy */ 565 #define NVMCTRL_SEESTAT_BUSY (_U_(0x1) << NVMCTRL_SEESTAT_BUSY_Pos) 566 #define NVMCTRL_SEESTAT_LOCK_Pos 3 /**< \brief (NVMCTRL_SEESTAT) SmartEEPROM Write Access Is Locked */ 567 #define NVMCTRL_SEESTAT_LOCK (_U_(0x1) << NVMCTRL_SEESTAT_LOCK_Pos) 568 #define NVMCTRL_SEESTAT_RLOCK_Pos 4 /**< \brief (NVMCTRL_SEESTAT) SmartEEPROM Write Access To Register Address Space Is Locked */ 569 #define NVMCTRL_SEESTAT_RLOCK (_U_(0x1) << NVMCTRL_SEESTAT_RLOCK_Pos) 570 #define NVMCTRL_SEESTAT_SBLK_Pos 8 /**< \brief (NVMCTRL_SEESTAT) Blocks Number In a Sector */ 571 #define NVMCTRL_SEESTAT_SBLK_Msk (_U_(0xF) << NVMCTRL_SEESTAT_SBLK_Pos) 572 #define NVMCTRL_SEESTAT_SBLK(value) (NVMCTRL_SEESTAT_SBLK_Msk & ((value) << NVMCTRL_SEESTAT_SBLK_Pos)) 573 #define NVMCTRL_SEESTAT_PSZ_Pos 16 /**< \brief (NVMCTRL_SEESTAT) SmartEEPROM Page Size */ 574 #define NVMCTRL_SEESTAT_PSZ_Msk (_U_(0x7) << NVMCTRL_SEESTAT_PSZ_Pos) 575 #define NVMCTRL_SEESTAT_PSZ(value) (NVMCTRL_SEESTAT_PSZ_Msk & ((value) << NVMCTRL_SEESTAT_PSZ_Pos)) 576 #define NVMCTRL_SEESTAT_MASK _U_(0x00070F1F) /**< \brief (NVMCTRL_SEESTAT) MASK Register */ 577 578 /** \brief NVMCTRL APB hardware registers */ 579 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 580 typedef struct { 581 __IO NVMCTRL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ 582 RoReg8 Reserved1[0x2]; 583 __O NVMCTRL_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 ( /W 16) Control B */ 584 RoReg8 Reserved2[0x2]; 585 __I NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/ 32) NVM Parameter */ 586 __IO NVMCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 16) Interrupt Enable Clear */ 587 __IO NVMCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x0E (R/W 16) Interrupt Enable Set */ 588 __IO NVMCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x10 (R/W 16) Interrupt Flag Status and Clear */ 589 __I NVMCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x12 (R/ 16) Status */ 590 __IO NVMCTRL_ADDR_Type ADDR; /**< \brief Offset: 0x14 (R/W 32) Address */ 591 __I NVMCTRL_RUNLOCK_Type RUNLOCK; /**< \brief Offset: 0x18 (R/ 32) Lock Section */ 592 __I NVMCTRL_PBLDATA_Type PBLDATA[2]; /**< \brief Offset: 0x1C (R/ 32) Page Buffer Load Data x */ 593 __I NVMCTRL_ECCERR_Type ECCERR; /**< \brief Offset: 0x24 (R/ 32) ECC Error Status Register */ 594 __IO NVMCTRL_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x28 (R/W 8) Debug Control */ 595 RoReg8 Reserved3[0x1]; 596 __IO NVMCTRL_SEECFG_Type SEECFG; /**< \brief Offset: 0x2A (R/W 8) SmartEEPROM Configuration Register */ 597 RoReg8 Reserved4[0x1]; 598 __I NVMCTRL_SEESTAT_Type SEESTAT; /**< \brief Offset: 0x2C (R/ 32) SmartEEPROM Status Register */ 599 } Nvmctrl; 600 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 601 602 #define SECTION_NVMCTRL_SW0 603 #define SECTION_NVMCTRL_TEMP_LOG 604 #define SECTION_NVMCTRL_USER 605 606 /*@}*/ 607 608 /* ************************************************************************** */ 609 /** SOFTWARE PERIPHERAL API DEFINITION FOR NON-VOLATILE FUSES */ 610 /* ************************************************************************** */ 611 /** \addtogroup fuses_api Peripheral Software API */ 612 /*@{*/ 613 614 615 #define AC_FUSES_BIAS0_ADDR NVMCTRL_SW0 616 #define AC_FUSES_BIAS0_Pos 0 /**< \brief (NVMCTRL_SW0) PAIR0 Bias Calibration */ 617 #define AC_FUSES_BIAS0_Msk (_U_(0x3) << AC_FUSES_BIAS0_Pos) 618 #define AC_FUSES_BIAS0(value) (AC_FUSES_BIAS0_Msk & ((value) << AC_FUSES_BIAS0_Pos)) 619 620 #define ADC0_FUSES_BIASCOMP_ADDR NVMCTRL_SW0 621 #define ADC0_FUSES_BIASCOMP_Pos 2 /**< \brief (NVMCTRL_SW0) ADC Comparator Scaling */ 622 #define ADC0_FUSES_BIASCOMP_Msk (_U_(0x7) << ADC0_FUSES_BIASCOMP_Pos) 623 #define ADC0_FUSES_BIASCOMP(value) (ADC0_FUSES_BIASCOMP_Msk & ((value) << ADC0_FUSES_BIASCOMP_Pos)) 624 625 #define ADC0_FUSES_BIASR2R_ADDR NVMCTRL_SW0 626 #define ADC0_FUSES_BIASR2R_Pos 8 /**< \brief (NVMCTRL_SW0) ADC Bias R2R ampli scaling */ 627 #define ADC0_FUSES_BIASR2R_Msk (_U_(0x7) << ADC0_FUSES_BIASR2R_Pos) 628 #define ADC0_FUSES_BIASR2R(value) (ADC0_FUSES_BIASR2R_Msk & ((value) << ADC0_FUSES_BIASR2R_Pos)) 629 630 #define ADC0_FUSES_BIASREFBUF_ADDR NVMCTRL_SW0 631 #define ADC0_FUSES_BIASREFBUF_Pos 5 /**< \brief (NVMCTRL_SW0) ADC Bias Reference Buffer Scaling */ 632 #define ADC0_FUSES_BIASREFBUF_Msk (_U_(0x7) << ADC0_FUSES_BIASREFBUF_Pos) 633 #define ADC0_FUSES_BIASREFBUF(value) (ADC0_FUSES_BIASREFBUF_Msk & ((value) << ADC0_FUSES_BIASREFBUF_Pos)) 634 635 #define ADC1_FUSES_BIASCOMP_ADDR NVMCTRL_SW0 636 #define ADC1_FUSES_BIASCOMP_Pos 16 /**< \brief (NVMCTRL_SW0) ADC Comparator Scaling */ 637 #define ADC1_FUSES_BIASCOMP_Msk (_U_(0x7) << ADC1_FUSES_BIASCOMP_Pos) 638 #define ADC1_FUSES_BIASCOMP(value) (ADC1_FUSES_BIASCOMP_Msk & ((value) << ADC1_FUSES_BIASCOMP_Pos)) 639 640 #define ADC1_FUSES_BIASR2R_ADDR NVMCTRL_SW0 641 #define ADC1_FUSES_BIASR2R_Pos 22 /**< \brief (NVMCTRL_SW0) ADC Bias R2R ampli scaling */ 642 #define ADC1_FUSES_BIASR2R_Msk (_U_(0x7) << ADC1_FUSES_BIASR2R_Pos) 643 #define ADC1_FUSES_BIASR2R(value) (ADC1_FUSES_BIASR2R_Msk & ((value) << ADC1_FUSES_BIASR2R_Pos)) 644 645 #define ADC1_FUSES_BIASREFBUF_ADDR NVMCTRL_SW0 646 #define ADC1_FUSES_BIASREFBUF_Pos 19 /**< \brief (NVMCTRL_SW0) ADC Bias Reference Buffer Scaling */ 647 #define ADC1_FUSES_BIASREFBUF_Msk (_U_(0x7) << ADC1_FUSES_BIASREFBUF_Pos) 648 #define ADC1_FUSES_BIASREFBUF(value) (ADC1_FUSES_BIASREFBUF_Msk & ((value) << ADC1_FUSES_BIASREFBUF_Pos)) 649 650 #define FUSES_BOD33USERLEVEL_ADDR NVMCTRL_USER 651 #define FUSES_BOD33USERLEVEL_Pos 1 /**< \brief (NVMCTRL_USER) BOD33 User Level */ 652 #define FUSES_BOD33USERLEVEL_Msk (_U_(0xFF) << FUSES_BOD33USERLEVEL_Pos) 653 #define FUSES_BOD33USERLEVEL(value) (FUSES_BOD33USERLEVEL_Msk & ((value) << FUSES_BOD33USERLEVEL_Pos)) 654 655 #define FUSES_BOD33_ACTION_ADDR NVMCTRL_USER 656 #define FUSES_BOD33_ACTION_Pos 9 /**< \brief (NVMCTRL_USER) BOD33 Action */ 657 #define FUSES_BOD33_ACTION_Msk (_U_(0x3) << FUSES_BOD33_ACTION_Pos) 658 #define FUSES_BOD33_ACTION(value) (FUSES_BOD33_ACTION_Msk & ((value) << FUSES_BOD33_ACTION_Pos)) 659 660 #define FUSES_BOD33_DIS_ADDR NVMCTRL_USER 661 #define FUSES_BOD33_DIS_Pos 0 /**< \brief (NVMCTRL_USER) BOD33 Disable */ 662 #define FUSES_BOD33_DIS_Msk (_U_(0x1) << FUSES_BOD33_DIS_Pos) 663 664 #define FUSES_BOD33_HYST_ADDR NVMCTRL_USER 665 #define FUSES_BOD33_HYST_Pos 11 /**< \brief (NVMCTRL_USER) BOD33 Hysteresis */ 666 #define FUSES_BOD33_HYST_Msk (_U_(0xF) << FUSES_BOD33_HYST_Pos) 667 #define FUSES_BOD33_HYST(value) (FUSES_BOD33_HYST_Msk & ((value) << FUSES_BOD33_HYST_Pos)) 668 669 #define FUSES_HOT_ADC_VAL_CTAT_ADDR (NVMCTRL_TEMP_LOG + 8) 670 #define FUSES_HOT_ADC_VAL_CTAT_Pos 12 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at hot temperature CTAT */ 671 #define FUSES_HOT_ADC_VAL_CTAT_Msk (_U_(0xFFF) << FUSES_HOT_ADC_VAL_CTAT_Pos) 672 #define FUSES_HOT_ADC_VAL_CTAT(value) (FUSES_HOT_ADC_VAL_CTAT_Msk & ((value) << FUSES_HOT_ADC_VAL_CTAT_Pos)) 673 674 #define FUSES_HOT_ADC_VAL_PTAT_ADDR (NVMCTRL_TEMP_LOG + 4) 675 #define FUSES_HOT_ADC_VAL_PTAT_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at hot temperature PTAT */ 676 #define FUSES_HOT_ADC_VAL_PTAT_Msk (_U_(0xFFF) << FUSES_HOT_ADC_VAL_PTAT_Pos) 677 #define FUSES_HOT_ADC_VAL_PTAT(value) (FUSES_HOT_ADC_VAL_PTAT_Msk & ((value) << FUSES_HOT_ADC_VAL_PTAT_Pos)) 678 679 #define FUSES_HOT_INT1V_VAL_ADDR (NVMCTRL_TEMP_LOG + 4) 680 #define FUSES_HOT_INT1V_VAL_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value) */ 681 #define FUSES_HOT_INT1V_VAL_Msk (_U_(0xFF) << FUSES_HOT_INT1V_VAL_Pos) 682 #define FUSES_HOT_INT1V_VAL(value) (FUSES_HOT_INT1V_VAL_Msk & ((value) << FUSES_HOT_INT1V_VAL_Pos)) 683 684 #define FUSES_HOT_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG 685 #define FUSES_HOT_TEMP_VAL_DEC_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of hot temperature */ 686 #define FUSES_HOT_TEMP_VAL_DEC_Msk (_U_(0xF) << FUSES_HOT_TEMP_VAL_DEC_Pos) 687 #define FUSES_HOT_TEMP_VAL_DEC(value) (FUSES_HOT_TEMP_VAL_DEC_Msk & ((value) << FUSES_HOT_TEMP_VAL_DEC_Pos)) 688 689 #define FUSES_HOT_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG 690 #define FUSES_HOT_TEMP_VAL_INT_Pos 12 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of hot temperature in oC */ 691 #define FUSES_HOT_TEMP_VAL_INT_Msk (_U_(0xFF) << FUSES_HOT_TEMP_VAL_INT_Pos) 692 #define FUSES_HOT_TEMP_VAL_INT(value) (FUSES_HOT_TEMP_VAL_INT_Msk & ((value) << FUSES_HOT_TEMP_VAL_INT_Pos)) 693 694 #define FUSES_ROOM_ADC_VAL_CTAT_ADDR (NVMCTRL_TEMP_LOG + 8) 695 #define FUSES_ROOM_ADC_VAL_CTAT_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at room temperature CTAT */ 696 #define FUSES_ROOM_ADC_VAL_CTAT_Msk (_U_(0xFFF) << FUSES_ROOM_ADC_VAL_CTAT_Pos) 697 #define FUSES_ROOM_ADC_VAL_CTAT(value) (FUSES_ROOM_ADC_VAL_CTAT_Msk & ((value) << FUSES_ROOM_ADC_VAL_CTAT_Pos)) 698 699 #define FUSES_ROOM_ADC_VAL_PTAT_ADDR (NVMCTRL_TEMP_LOG + 4) 700 #define FUSES_ROOM_ADC_VAL_PTAT_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at room temperature PTAT */ 701 #define FUSES_ROOM_ADC_VAL_PTAT_Msk (_U_(0xFFF) << FUSES_ROOM_ADC_VAL_PTAT_Pos) 702 #define FUSES_ROOM_ADC_VAL_PTAT(value) (FUSES_ROOM_ADC_VAL_PTAT_Msk & ((value) << FUSES_ROOM_ADC_VAL_PTAT_Pos)) 703 704 #define FUSES_ROOM_INT1V_VAL_ADDR NVMCTRL_TEMP_LOG 705 #define FUSES_ROOM_INT1V_VAL_Pos 24 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value) */ 706 #define FUSES_ROOM_INT1V_VAL_Msk (_U_(0xFF) << FUSES_ROOM_INT1V_VAL_Pos) 707 #define FUSES_ROOM_INT1V_VAL(value) (FUSES_ROOM_INT1V_VAL_Msk & ((value) << FUSES_ROOM_INT1V_VAL_Pos)) 708 709 #define FUSES_ROOM_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG 710 #define FUSES_ROOM_TEMP_VAL_DEC_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of room temperature */ 711 #define FUSES_ROOM_TEMP_VAL_DEC_Msk (_U_(0xF) << FUSES_ROOM_TEMP_VAL_DEC_Pos) 712 #define FUSES_ROOM_TEMP_VAL_DEC(value) (FUSES_ROOM_TEMP_VAL_DEC_Msk & ((value) << FUSES_ROOM_TEMP_VAL_DEC_Pos)) 713 714 #define FUSES_ROOM_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG 715 #define FUSES_ROOM_TEMP_VAL_INT_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of room temperature in oC */ 716 #define FUSES_ROOM_TEMP_VAL_INT_Msk (_U_(0xFF) << FUSES_ROOM_TEMP_VAL_INT_Pos) 717 #define FUSES_ROOM_TEMP_VAL_INT(value) (FUSES_ROOM_TEMP_VAL_INT_Msk & ((value) << FUSES_ROOM_TEMP_VAL_INT_Pos)) 718 719 #define NVMCTRL_FUSES_BOOTPROT_ADDR NVMCTRL_USER 720 #define NVMCTRL_FUSES_BOOTPROT_Pos 26 /**< \brief (NVMCTRL_USER) Bootloader Size */ 721 #define NVMCTRL_FUSES_BOOTPROT_Msk (_U_(0xF) << NVMCTRL_FUSES_BOOTPROT_Pos) 722 #define NVMCTRL_FUSES_BOOTPROT(value) (NVMCTRL_FUSES_BOOTPROT_Msk & ((value) << NVMCTRL_FUSES_BOOTPROT_Pos)) 723 724 #define NVMCTRL_FUSES_REGION_LOCKS_ADDR (NVMCTRL_USER + 8) 725 #define NVMCTRL_FUSES_REGION_LOCKS_Pos 0 /**< \brief (NVMCTRL_USER) NVM Region Locks */ 726 #define NVMCTRL_FUSES_REGION_LOCKS_Msk (_U_(0xFFFFFFFF) << NVMCTRL_FUSES_REGION_LOCKS_Pos) 727 #define NVMCTRL_FUSES_REGION_LOCKS(value) (NVMCTRL_FUSES_REGION_LOCKS_Msk & ((value) << NVMCTRL_FUSES_REGION_LOCKS_Pos)) 728 729 #define NVMCTRL_FUSES_SEEPSZ_ADDR (NVMCTRL_USER + 4) 730 #define NVMCTRL_FUSES_SEEPSZ_Pos 4 /**< \brief (NVMCTRL_USER) Size Of SmartEEPROM Page */ 731 #define NVMCTRL_FUSES_SEEPSZ_Msk (_U_(0x7) << NVMCTRL_FUSES_SEEPSZ_Pos) 732 #define NVMCTRL_FUSES_SEEPSZ(value) (NVMCTRL_FUSES_SEEPSZ_Msk & ((value) << NVMCTRL_FUSES_SEEPSZ_Pos)) 733 734 #define NVMCTRL_FUSES_SEESBLK_ADDR (NVMCTRL_USER + 4) 735 #define NVMCTRL_FUSES_SEESBLK_Pos 0 /**< \brief (NVMCTRL_USER) Number Of Physical NVM Blocks Composing a SmartEEPROM Sector */ 736 #define NVMCTRL_FUSES_SEESBLK_Msk (_U_(0xF) << NVMCTRL_FUSES_SEESBLK_Pos) 737 #define NVMCTRL_FUSES_SEESBLK(value) (NVMCTRL_FUSES_SEESBLK_Msk & ((value) << NVMCTRL_FUSES_SEESBLK_Pos)) 738 739 #define RAMECC_FUSES_ECCDIS_ADDR (NVMCTRL_USER + 4) 740 #define RAMECC_FUSES_ECCDIS_Pos 7 /**< \brief (NVMCTRL_USER) RAM ECC Disable fuse */ 741 #define RAMECC_FUSES_ECCDIS_Msk (_U_(0x1) << RAMECC_FUSES_ECCDIS_Pos) 742 743 #define USB_FUSES_TRANSN_ADDR (NVMCTRL_SW0 + 4) 744 #define USB_FUSES_TRANSN_Pos 0 /**< \brief (NVMCTRL_SW0) USB pad Transn calibration */ 745 #define USB_FUSES_TRANSN_Msk (_U_(0x1F) << USB_FUSES_TRANSN_Pos) 746 #define USB_FUSES_TRANSN(value) (USB_FUSES_TRANSN_Msk & ((value) << USB_FUSES_TRANSN_Pos)) 747 748 #define USB_FUSES_TRANSP_ADDR (NVMCTRL_SW0 + 4) 749 #define USB_FUSES_TRANSP_Pos 5 /**< \brief (NVMCTRL_SW0) USB pad Transp calibration */ 750 #define USB_FUSES_TRANSP_Msk (_U_(0x1F) << USB_FUSES_TRANSP_Pos) 751 #define USB_FUSES_TRANSP(value) (USB_FUSES_TRANSP_Msk & ((value) << USB_FUSES_TRANSP_Pos)) 752 753 #define USB_FUSES_TRIM_ADDR (NVMCTRL_SW0 + 4) 754 #define USB_FUSES_TRIM_Pos 10 /**< \brief (NVMCTRL_SW0) USB pad Trim calibration */ 755 #define USB_FUSES_TRIM_Msk (_U_(0x7) << USB_FUSES_TRIM_Pos) 756 #define USB_FUSES_TRIM(value) (USB_FUSES_TRIM_Msk & ((value) << USB_FUSES_TRIM_Pos)) 757 758 #define WDT_FUSES_ALWAYSON_ADDR (NVMCTRL_USER + 4) 759 #define WDT_FUSES_ALWAYSON_Pos 17 /**< \brief (NVMCTRL_USER) WDT Always On */ 760 #define WDT_FUSES_ALWAYSON_Msk (_U_(0x1) << WDT_FUSES_ALWAYSON_Pos) 761 762 #define WDT_FUSES_ENABLE_ADDR (NVMCTRL_USER + 4) 763 #define WDT_FUSES_ENABLE_Pos 16 /**< \brief (NVMCTRL_USER) WDT Enable */ 764 #define WDT_FUSES_ENABLE_Msk (_U_(0x1) << WDT_FUSES_ENABLE_Pos) 765 766 #define WDT_FUSES_EWOFFSET_ADDR (NVMCTRL_USER + 4) 767 #define WDT_FUSES_EWOFFSET_Pos 26 /**< \brief (NVMCTRL_USER) WDT Early Warning Offset */ 768 #define WDT_FUSES_EWOFFSET_Msk (_U_(0xF) << WDT_FUSES_EWOFFSET_Pos) 769 #define WDT_FUSES_EWOFFSET(value) (WDT_FUSES_EWOFFSET_Msk & ((value) << WDT_FUSES_EWOFFSET_Pos)) 770 771 #define WDT_FUSES_PER_ADDR (NVMCTRL_USER + 4) 772 #define WDT_FUSES_PER_Pos 18 /**< \brief (NVMCTRL_USER) WDT Period */ 773 #define WDT_FUSES_PER_Msk (_U_(0xF) << WDT_FUSES_PER_Pos) 774 #define WDT_FUSES_PER(value) (WDT_FUSES_PER_Msk & ((value) << WDT_FUSES_PER_Pos)) 775 776 #define WDT_FUSES_WEN_ADDR (NVMCTRL_USER + 4) 777 #define WDT_FUSES_WEN_Pos 30 /**< \brief (NVMCTRL_USER) WDT Window Mode Enable */ 778 #define WDT_FUSES_WEN_Msk (_U_(0x1) << WDT_FUSES_WEN_Pos) 779 780 #define WDT_FUSES_WINDOW_ADDR (NVMCTRL_USER + 4) 781 #define WDT_FUSES_WINDOW_Pos 22 /**< \brief (NVMCTRL_USER) WDT Window */ 782 #define WDT_FUSES_WINDOW_Msk (_U_(0xF) << WDT_FUSES_WINDOW_Pos) 783 #define WDT_FUSES_WINDOW(value) (WDT_FUSES_WINDOW_Msk & ((value) << WDT_FUSES_WINDOW_Pos)) 784 785 /*@}*/ 786 787 #endif /* _SAME53_NVMCTRL_COMPONENT_ */ 788
