1 /** 2 * \file 3 * 4 * \brief Header file for SAMD51J20A 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMD51J20A_ 31 #define _SAMD51J20A_ 32 33 /** 34 * \ingroup SAMD51_definitions 35 * \addtogroup SAMD51J20A_definitions SAMD51J20A definitions 36 * This file defines all structures and symbols for SAMD51J20A: 37 * - registers and bitfields 38 * - peripheral base address 39 * - peripheral ID 40 * - PIO definitions 41 */ 42 /*@{*/ 43 44 #ifdef __cplusplus 45 extern "C" { 46 #endif 47 48 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 49 #include <stdint.h> 50 #ifndef __cplusplus 51 typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ 52 typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ 53 typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ 54 #else 55 typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ 56 typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ 57 typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ 58 #endif 59 typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ 60 typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ 61 typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ 62 typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ 63 typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ 64 typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ 65 #endif 66 67 #if !defined(SKIP_INTEGER_LITERALS) 68 #if defined(_U_) || defined(_L_) || defined(_UL_) 69 #error "Integer Literals macros already defined elsewhere" 70 #endif 71 72 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 73 /* Macros that deal with adding suffixes to integer literal constants for C/C++ */ 74 #define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ 75 #define _L_(x) x ## L /**< C code: Long integer literal constant value */ 76 #define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ 77 #else /* Assembler */ 78 #define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ 79 #define _L_(x) x /**< Assembler: Long integer literal constant value */ 80 #define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ 81 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 82 #endif /* SKIP_INTEGER_LITERALS */ 83 84 /* ************************************************************************** */ 85 /** CMSIS DEFINITIONS FOR SAMD51J20A */ 86 /* ************************************************************************** */ 87 /** \defgroup SAMD51J20A_cmsis CMSIS Definitions */ 88 /*@{*/ 89 90 /** Interrupt Number Definition */ 91 typedef enum IRQn 92 { 93 /****** Cortex-M4 Processor Exceptions Numbers *******************/ 94 NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ 95 HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ 96 MemoryManagement_IRQn = -12,/**< 4 Memory Management Interrupt */ 97 BusFault_IRQn = -11,/**< 5 Bus Fault Interrupt */ 98 UsageFault_IRQn = -10,/**< 6 Usage Fault Interrupt */ 99 SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ 100 DebugMonitor_IRQn = -4, /**< 12 Debug Monitor Interrupt */ 101 PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ 102 SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ 103 /****** SAMD51J20A-specific Interrupt Numbers *********************/ 104 PM_IRQn = 0, /**< 0 SAMD51J20A Power Manager (PM) */ 105 MCLK_IRQn = 1, /**< 1 SAMD51J20A Main Clock (MCLK) */ 106 OSCCTRL_0_IRQn = 2, /**< 2 SAMD51J20A Oscillators Control (OSCCTRL) IRQ 0 */ 107 OSCCTRL_1_IRQn = 3, /**< 3 SAMD51J20A Oscillators Control (OSCCTRL) IRQ 1 */ 108 OSCCTRL_2_IRQn = 4, /**< 4 SAMD51J20A Oscillators Control (OSCCTRL) IRQ 2 */ 109 OSCCTRL_3_IRQn = 5, /**< 5 SAMD51J20A Oscillators Control (OSCCTRL) IRQ 3 */ 110 OSCCTRL_4_IRQn = 6, /**< 6 SAMD51J20A Oscillators Control (OSCCTRL) IRQ 4 */ 111 OSC32KCTRL_IRQn = 7, /**< 7 SAMD51J20A 32kHz Oscillators Control (OSC32KCTRL) */ 112 SUPC_0_IRQn = 8, /**< 8 SAMD51J20A Supply Controller (SUPC) IRQ 0 */ 113 SUPC_1_IRQn = 9, /**< 9 SAMD51J20A Supply Controller (SUPC) IRQ 1 */ 114 WDT_IRQn = 10, /**< 10 SAMD51J20A Watchdog Timer (WDT) */ 115 RTC_IRQn = 11, /**< 11 SAMD51J20A Real-Time Counter (RTC) */ 116 EIC_0_IRQn = 12, /**< 12 SAMD51J20A External Interrupt Controller (EIC) IRQ 0 */ 117 EIC_1_IRQn = 13, /**< 13 SAMD51J20A External Interrupt Controller (EIC) IRQ 1 */ 118 EIC_2_IRQn = 14, /**< 14 SAMD51J20A External Interrupt Controller (EIC) IRQ 2 */ 119 EIC_3_IRQn = 15, /**< 15 SAMD51J20A External Interrupt Controller (EIC) IRQ 3 */ 120 EIC_4_IRQn = 16, /**< 16 SAMD51J20A External Interrupt Controller (EIC) IRQ 4 */ 121 EIC_5_IRQn = 17, /**< 17 SAMD51J20A External Interrupt Controller (EIC) IRQ 5 */ 122 EIC_6_IRQn = 18, /**< 18 SAMD51J20A External Interrupt Controller (EIC) IRQ 6 */ 123 EIC_7_IRQn = 19, /**< 19 SAMD51J20A External Interrupt Controller (EIC) IRQ 7 */ 124 EIC_8_IRQn = 20, /**< 20 SAMD51J20A External Interrupt Controller (EIC) IRQ 8 */ 125 EIC_9_IRQn = 21, /**< 21 SAMD51J20A External Interrupt Controller (EIC) IRQ 9 */ 126 EIC_10_IRQn = 22, /**< 22 SAMD51J20A External Interrupt Controller (EIC) IRQ 10 */ 127 EIC_11_IRQn = 23, /**< 23 SAMD51J20A External Interrupt Controller (EIC) IRQ 11 */ 128 EIC_12_IRQn = 24, /**< 24 SAMD51J20A External Interrupt Controller (EIC) IRQ 12 */ 129 EIC_13_IRQn = 25, /**< 25 SAMD51J20A External Interrupt Controller (EIC) IRQ 13 */ 130 EIC_14_IRQn = 26, /**< 26 SAMD51J20A External Interrupt Controller (EIC) IRQ 14 */ 131 EIC_15_IRQn = 27, /**< 27 SAMD51J20A External Interrupt Controller (EIC) IRQ 15 */ 132 FREQM_IRQn = 28, /**< 28 SAMD51J20A Frequency Meter (FREQM) */ 133 NVMCTRL_0_IRQn = 29, /**< 29 SAMD51J20A Non-Volatile Memory Controller (NVMCTRL) IRQ 0 */ 134 NVMCTRL_1_IRQn = 30, /**< 30 SAMD51J20A Non-Volatile Memory Controller (NVMCTRL) IRQ 1 */ 135 DMAC_0_IRQn = 31, /**< 31 SAMD51J20A Direct Memory Access Controller (DMAC) IRQ 0 */ 136 DMAC_1_IRQn = 32, /**< 32 SAMD51J20A Direct Memory Access Controller (DMAC) IRQ 1 */ 137 DMAC_2_IRQn = 33, /**< 33 SAMD51J20A Direct Memory Access Controller (DMAC) IRQ 2 */ 138 DMAC_3_IRQn = 34, /**< 34 SAMD51J20A Direct Memory Access Controller (DMAC) IRQ 3 */ 139 DMAC_4_IRQn = 35, /**< 35 SAMD51J20A Direct Memory Access Controller (DMAC) IRQ 4 */ 140 EVSYS_0_IRQn = 36, /**< 36 SAMD51J20A Event System Interface (EVSYS) IRQ 0 */ 141 EVSYS_1_IRQn = 37, /**< 37 SAMD51J20A Event System Interface (EVSYS) IRQ 1 */ 142 EVSYS_2_IRQn = 38, /**< 38 SAMD51J20A Event System Interface (EVSYS) IRQ 2 */ 143 EVSYS_3_IRQn = 39, /**< 39 SAMD51J20A Event System Interface (EVSYS) IRQ 3 */ 144 EVSYS_4_IRQn = 40, /**< 40 SAMD51J20A Event System Interface (EVSYS) IRQ 4 */ 145 PAC_IRQn = 41, /**< 41 SAMD51J20A Peripheral Access Controller (PAC) */ 146 RAMECC_IRQn = 45, /**< 45 SAMD51J20A RAM ECC (RAMECC) */ 147 SERCOM0_0_IRQn = 46, /**< 46 SAMD51J20A Serial Communication Interface 0 (SERCOM0) IRQ 0 */ 148 SERCOM0_1_IRQn = 47, /**< 47 SAMD51J20A Serial Communication Interface 0 (SERCOM0) IRQ 1 */ 149 SERCOM0_2_IRQn = 48, /**< 48 SAMD51J20A Serial Communication Interface 0 (SERCOM0) IRQ 2 */ 150 SERCOM0_3_IRQn = 49, /**< 49 SAMD51J20A Serial Communication Interface 0 (SERCOM0) IRQ 3 */ 151 SERCOM1_0_IRQn = 50, /**< 50 SAMD51J20A Serial Communication Interface 1 (SERCOM1) IRQ 0 */ 152 SERCOM1_1_IRQn = 51, /**< 51 SAMD51J20A Serial Communication Interface 1 (SERCOM1) IRQ 1 */ 153 SERCOM1_2_IRQn = 52, /**< 52 SAMD51J20A Serial Communication Interface 1 (SERCOM1) IRQ 2 */ 154 SERCOM1_3_IRQn = 53, /**< 53 SAMD51J20A Serial Communication Interface 1 (SERCOM1) IRQ 3 */ 155 SERCOM2_0_IRQn = 54, /**< 54 SAMD51J20A Serial Communication Interface 2 (SERCOM2) IRQ 0 */ 156 SERCOM2_1_IRQn = 55, /**< 55 SAMD51J20A Serial Communication Interface 2 (SERCOM2) IRQ 1 */ 157 SERCOM2_2_IRQn = 56, /**< 56 SAMD51J20A Serial Communication Interface 2 (SERCOM2) IRQ 2 */ 158 SERCOM2_3_IRQn = 57, /**< 57 SAMD51J20A Serial Communication Interface 2 (SERCOM2) IRQ 3 */ 159 SERCOM3_0_IRQn = 58, /**< 58 SAMD51J20A Serial Communication Interface 3 (SERCOM3) IRQ 0 */ 160 SERCOM3_1_IRQn = 59, /**< 59 SAMD51J20A Serial Communication Interface 3 (SERCOM3) IRQ 1 */ 161 SERCOM3_2_IRQn = 60, /**< 60 SAMD51J20A Serial Communication Interface 3 (SERCOM3) IRQ 2 */ 162 SERCOM3_3_IRQn = 61, /**< 61 SAMD51J20A Serial Communication Interface 3 (SERCOM3) IRQ 3 */ 163 SERCOM4_0_IRQn = 62, /**< 62 SAMD51J20A Serial Communication Interface 4 (SERCOM4) IRQ 0 */ 164 SERCOM4_1_IRQn = 63, /**< 63 SAMD51J20A Serial Communication Interface 4 (SERCOM4) IRQ 1 */ 165 SERCOM4_2_IRQn = 64, /**< 64 SAMD51J20A Serial Communication Interface 4 (SERCOM4) IRQ 2 */ 166 SERCOM4_3_IRQn = 65, /**< 65 SAMD51J20A Serial Communication Interface 4 (SERCOM4) IRQ 3 */ 167 SERCOM5_0_IRQn = 66, /**< 66 SAMD51J20A Serial Communication Interface 5 (SERCOM5) IRQ 0 */ 168 SERCOM5_1_IRQn = 67, /**< 67 SAMD51J20A Serial Communication Interface 5 (SERCOM5) IRQ 1 */ 169 SERCOM5_2_IRQn = 68, /**< 68 SAMD51J20A Serial Communication Interface 5 (SERCOM5) IRQ 2 */ 170 SERCOM5_3_IRQn = 69, /**< 69 SAMD51J20A Serial Communication Interface 5 (SERCOM5) IRQ 3 */ 171 USB_0_IRQn = 80, /**< 80 SAMD51J20A Universal Serial Bus (USB) IRQ 0 */ 172 USB_1_IRQn = 81, /**< 81 SAMD51J20A Universal Serial Bus (USB) IRQ 1 */ 173 USB_2_IRQn = 82, /**< 82 SAMD51J20A Universal Serial Bus (USB) IRQ 2 */ 174 USB_3_IRQn = 83, /**< 83 SAMD51J20A Universal Serial Bus (USB) IRQ 3 */ 175 TCC0_0_IRQn = 85, /**< 85 SAMD51J20A Timer Counter Control 0 (TCC0) IRQ 0 */ 176 TCC0_1_IRQn = 86, /**< 86 SAMD51J20A Timer Counter Control 0 (TCC0) IRQ 1 */ 177 TCC0_2_IRQn = 87, /**< 87 SAMD51J20A Timer Counter Control 0 (TCC0) IRQ 2 */ 178 TCC0_3_IRQn = 88, /**< 88 SAMD51J20A Timer Counter Control 0 (TCC0) IRQ 3 */ 179 TCC0_4_IRQn = 89, /**< 89 SAMD51J20A Timer Counter Control 0 (TCC0) IRQ 4 */ 180 TCC0_5_IRQn = 90, /**< 90 SAMD51J20A Timer Counter Control 0 (TCC0) IRQ 5 */ 181 TCC0_6_IRQn = 91, /**< 91 SAMD51J20A Timer Counter Control 0 (TCC0) IRQ 6 */ 182 TCC1_0_IRQn = 92, /**< 92 SAMD51J20A Timer Counter Control 1 (TCC1) IRQ 0 */ 183 TCC1_1_IRQn = 93, /**< 93 SAMD51J20A Timer Counter Control 1 (TCC1) IRQ 1 */ 184 TCC1_2_IRQn = 94, /**< 94 SAMD51J20A Timer Counter Control 1 (TCC1) IRQ 2 */ 185 TCC1_3_IRQn = 95, /**< 95 SAMD51J20A Timer Counter Control 1 (TCC1) IRQ 3 */ 186 TCC1_4_IRQn = 96, /**< 96 SAMD51J20A Timer Counter Control 1 (TCC1) IRQ 4 */ 187 TCC2_0_IRQn = 97, /**< 97 SAMD51J20A Timer Counter Control 2 (TCC2) IRQ 0 */ 188 TCC2_1_IRQn = 98, /**< 98 SAMD51J20A Timer Counter Control 2 (TCC2) IRQ 1 */ 189 TCC2_2_IRQn = 99, /**< 99 SAMD51J20A Timer Counter Control 2 (TCC2) IRQ 2 */ 190 TCC2_3_IRQn = 100, /**< 100 SAMD51J20A Timer Counter Control 2 (TCC2) IRQ 3 */ 191 TCC3_0_IRQn = 101, /**< 101 SAMD51J20A Timer Counter Control 3 (TCC3) IRQ 0 */ 192 TCC3_1_IRQn = 102, /**< 102 SAMD51J20A Timer Counter Control 3 (TCC3) IRQ 1 */ 193 TCC3_2_IRQn = 103, /**< 103 SAMD51J20A Timer Counter Control 3 (TCC3) IRQ 2 */ 194 TCC4_0_IRQn = 104, /**< 104 SAMD51J20A Timer Counter Control 4 (TCC4) IRQ 0 */ 195 TCC4_1_IRQn = 105, /**< 105 SAMD51J20A Timer Counter Control 4 (TCC4) IRQ 1 */ 196 TCC4_2_IRQn = 106, /**< 106 SAMD51J20A Timer Counter Control 4 (TCC4) IRQ 2 */ 197 TC0_IRQn = 107, /**< 107 SAMD51J20A Basic Timer Counter 0 (TC0) */ 198 TC1_IRQn = 108, /**< 108 SAMD51J20A Basic Timer Counter 1 (TC1) */ 199 TC2_IRQn = 109, /**< 109 SAMD51J20A Basic Timer Counter 2 (TC2) */ 200 TC3_IRQn = 110, /**< 110 SAMD51J20A Basic Timer Counter 3 (TC3) */ 201 TC4_IRQn = 111, /**< 111 SAMD51J20A Basic Timer Counter 4 (TC4) */ 202 TC5_IRQn = 112, /**< 112 SAMD51J20A Basic Timer Counter 5 (TC5) */ 203 PDEC_0_IRQn = 115, /**< 115 SAMD51J20A Quadrature Decodeur (PDEC) IRQ 0 */ 204 PDEC_1_IRQn = 116, /**< 116 SAMD51J20A Quadrature Decodeur (PDEC) IRQ 1 */ 205 PDEC_2_IRQn = 117, /**< 117 SAMD51J20A Quadrature Decodeur (PDEC) IRQ 2 */ 206 ADC0_0_IRQn = 118, /**< 118 SAMD51J20A Analog Digital Converter 0 (ADC0) IRQ 0 */ 207 ADC0_1_IRQn = 119, /**< 119 SAMD51J20A Analog Digital Converter 0 (ADC0) IRQ 1 */ 208 ADC1_0_IRQn = 120, /**< 120 SAMD51J20A Analog Digital Converter 1 (ADC1) IRQ 0 */ 209 ADC1_1_IRQn = 121, /**< 121 SAMD51J20A Analog Digital Converter 1 (ADC1) IRQ 1 */ 210 AC_IRQn = 122, /**< 122 SAMD51J20A Analog Comparators (AC) */ 211 DAC_0_IRQn = 123, /**< 123 SAMD51J20A Digital-to-Analog Converter (DAC) IRQ 0 */ 212 DAC_1_IRQn = 124, /**< 124 SAMD51J20A Digital-to-Analog Converter (DAC) IRQ 1 */ 213 DAC_2_IRQn = 125, /**< 125 SAMD51J20A Digital-to-Analog Converter (DAC) IRQ 2 */ 214 DAC_3_IRQn = 126, /**< 126 SAMD51J20A Digital-to-Analog Converter (DAC) IRQ 3 */ 215 DAC_4_IRQn = 127, /**< 127 SAMD51J20A Digital-to-Analog Converter (DAC) IRQ 4 */ 216 I2S_IRQn = 128, /**< 128 SAMD51J20A Inter-IC Sound Interface (I2S) */ 217 PCC_IRQn = 129, /**< 129 SAMD51J20A Parallel Capture Controller (PCC) */ 218 AES_IRQn = 130, /**< 130 SAMD51J20A Advanced Encryption Standard (AES) */ 219 TRNG_IRQn = 131, /**< 131 SAMD51J20A True Random Generator (TRNG) */ 220 ICM_IRQn = 132, /**< 132 SAMD51J20A Integrity Check Monitor (ICM) */ 221 PUKCC_IRQn = 133, /**< 133 SAMD51J20A PUblic-Key Cryptography Controller (PUKCC) */ 222 QSPI_IRQn = 134, /**< 134 SAMD51J20A Quad SPI interface (QSPI) */ 223 SDHC0_IRQn = 135, /**< 135 SAMD51J20A SD/MMC Host Controller 0 (SDHC0) */ 224 225 PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ 226 } IRQn_Type; 227 228 typedef struct _DeviceVectors 229 { 230 /* Stack pointer */ 231 void* pvStack; 232 233 /* Cortex-M handlers */ 234 void* pfnReset_Handler; 235 void* pfnNonMaskableInt_Handler; 236 void* pfnHardFault_Handler; 237 void* pfnMemManagement_Handler; 238 void* pfnBusFault_Handler; 239 void* pfnUsageFault_Handler; 240 void* pvReservedM9; 241 void* pvReservedM8; 242 void* pvReservedM7; 243 void* pvReservedM6; 244 void* pfnSVCall_Handler; 245 void* pfnDebugMonitor_Handler; 246 void* pvReservedM3; 247 void* pfnPendSV_Handler; 248 void* pfnSysTick_Handler; 249 250 /* Peripheral handlers */ 251 void* pfnPM_Handler; /* 0 Power Manager */ 252 void* pfnMCLK_Handler; /* 1 Main Clock */ 253 void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ 254 void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ 255 void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ 256 void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ 257 void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ 258 void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ 259 void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ 260 void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ 261 void* pfnWDT_Handler; /* 10 Watchdog Timer */ 262 void* pfnRTC_Handler; /* 11 Real-Time Counter */ 263 void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ 264 void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ 265 void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ 266 void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ 267 void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ 268 void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ 269 void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ 270 void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ 271 void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ 272 void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ 273 void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ 274 void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ 275 void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ 276 void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ 277 void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ 278 void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ 279 void* pfnFREQM_Handler; /* 28 Frequency Meter */ 280 void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ 281 void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ 282 void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ 283 void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ 284 void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ 285 void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ 286 void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ 287 void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ 288 void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ 289 void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ 290 void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ 291 void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ 292 void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ 293 void* pvReserved42; 294 void* pvReserved43; 295 void* pvReserved44; 296 void* pfnRAMECC_Handler; /* 45 RAM ECC */ 297 void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ 298 void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ 299 void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ 300 void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ 301 void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ 302 void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ 303 void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ 304 void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ 305 void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ 306 void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ 307 void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ 308 void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ 309 void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ 310 void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ 311 void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ 312 void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ 313 void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ 314 void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ 315 void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ 316 void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ 317 void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ 318 void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ 319 void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ 320 void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ 321 void* pvReserved70; 322 void* pvReserved71; 323 void* pvReserved72; 324 void* pvReserved73; 325 void* pvReserved74; 326 void* pvReserved75; 327 void* pvReserved76; 328 void* pvReserved77; 329 void* pvReserved78; 330 void* pvReserved79; 331 void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ 332 void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ 333 void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ 334 void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ 335 void* pvReserved84; 336 void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ 337 void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ 338 void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ 339 void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ 340 void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ 341 void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ 342 void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ 343 void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ 344 void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ 345 void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ 346 void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ 347 void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ 348 void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ 349 void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ 350 void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ 351 void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ 352 void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ 353 void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ 354 void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ 355 void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ 356 void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ 357 void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ 358 void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ 359 void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ 360 void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ 361 void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ 362 void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ 363 void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ 364 void* pvReserved113; 365 void* pvReserved114; 366 void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ 367 void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ 368 void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ 369 void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ 370 void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ 371 void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ 372 void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ 373 void* pfnAC_Handler; /* 122 Analog Comparators */ 374 void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ 375 void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ 376 void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ 377 void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ 378 void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ 379 void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ 380 void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ 381 void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ 382 void* pfnTRNG_Handler; /* 131 True Random Generator */ 383 void* pfnICM_Handler; /* 132 Integrity Check Monitor */ 384 void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ 385 void* pfnQSPI_Handler; /* 134 Quad SPI interface */ 386 void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ 387 void* pvReserved136; 388 } DeviceVectors; 389 390 /* Cortex-M4 processor handlers */ 391 void Reset_Handler ( void ); 392 void NonMaskableInt_Handler ( void ); 393 void HardFault_Handler ( void ); 394 void MemManagement_Handler ( void ); 395 void BusFault_Handler ( void ); 396 void UsageFault_Handler ( void ); 397 void SVCall_Handler ( void ); 398 void DebugMonitor_Handler ( void ); 399 void PendSV_Handler ( void ); 400 void SysTick_Handler ( void ); 401 402 /* Peripherals handlers */ 403 void PM_Handler ( void ); 404 void MCLK_Handler ( void ); 405 void OSCCTRL_0_Handler ( void ); 406 void OSCCTRL_1_Handler ( void ); 407 void OSCCTRL_2_Handler ( void ); 408 void OSCCTRL_3_Handler ( void ); 409 void OSCCTRL_4_Handler ( void ); 410 void OSC32KCTRL_Handler ( void ); 411 void SUPC_0_Handler ( void ); 412 void SUPC_1_Handler ( void ); 413 void WDT_Handler ( void ); 414 void RTC_Handler ( void ); 415 void EIC_0_Handler ( void ); 416 void EIC_1_Handler ( void ); 417 void EIC_2_Handler ( void ); 418 void EIC_3_Handler ( void ); 419 void EIC_4_Handler ( void ); 420 void EIC_5_Handler ( void ); 421 void EIC_6_Handler ( void ); 422 void EIC_7_Handler ( void ); 423 void EIC_8_Handler ( void ); 424 void EIC_9_Handler ( void ); 425 void EIC_10_Handler ( void ); 426 void EIC_11_Handler ( void ); 427 void EIC_12_Handler ( void ); 428 void EIC_13_Handler ( void ); 429 void EIC_14_Handler ( void ); 430 void EIC_15_Handler ( void ); 431 void FREQM_Handler ( void ); 432 void NVMCTRL_0_Handler ( void ); 433 void NVMCTRL_1_Handler ( void ); 434 void DMAC_0_Handler ( void ); 435 void DMAC_1_Handler ( void ); 436 void DMAC_2_Handler ( void ); 437 void DMAC_3_Handler ( void ); 438 void DMAC_4_Handler ( void ); 439 void EVSYS_0_Handler ( void ); 440 void EVSYS_1_Handler ( void ); 441 void EVSYS_2_Handler ( void ); 442 void EVSYS_3_Handler ( void ); 443 void EVSYS_4_Handler ( void ); 444 void PAC_Handler ( void ); 445 void RAMECC_Handler ( void ); 446 void SERCOM0_0_Handler ( void ); 447 void SERCOM0_1_Handler ( void ); 448 void SERCOM0_2_Handler ( void ); 449 void SERCOM0_3_Handler ( void ); 450 void SERCOM1_0_Handler ( void ); 451 void SERCOM1_1_Handler ( void ); 452 void SERCOM1_2_Handler ( void ); 453 void SERCOM1_3_Handler ( void ); 454 void SERCOM2_0_Handler ( void ); 455 void SERCOM2_1_Handler ( void ); 456 void SERCOM2_2_Handler ( void ); 457 void SERCOM2_3_Handler ( void ); 458 void SERCOM3_0_Handler ( void ); 459 void SERCOM3_1_Handler ( void ); 460 void SERCOM3_2_Handler ( void ); 461 void SERCOM3_3_Handler ( void ); 462 void SERCOM4_0_Handler ( void ); 463 void SERCOM4_1_Handler ( void ); 464 void SERCOM4_2_Handler ( void ); 465 void SERCOM4_3_Handler ( void ); 466 void SERCOM5_0_Handler ( void ); 467 void SERCOM5_1_Handler ( void ); 468 void SERCOM5_2_Handler ( void ); 469 void SERCOM5_3_Handler ( void ); 470 void USB_0_Handler ( void ); 471 void USB_1_Handler ( void ); 472 void USB_2_Handler ( void ); 473 void USB_3_Handler ( void ); 474 void TCC0_0_Handler ( void ); 475 void TCC0_1_Handler ( void ); 476 void TCC0_2_Handler ( void ); 477 void TCC0_3_Handler ( void ); 478 void TCC0_4_Handler ( void ); 479 void TCC0_5_Handler ( void ); 480 void TCC0_6_Handler ( void ); 481 void TCC1_0_Handler ( void ); 482 void TCC1_1_Handler ( void ); 483 void TCC1_2_Handler ( void ); 484 void TCC1_3_Handler ( void ); 485 void TCC1_4_Handler ( void ); 486 void TCC2_0_Handler ( void ); 487 void TCC2_1_Handler ( void ); 488 void TCC2_2_Handler ( void ); 489 void TCC2_3_Handler ( void ); 490 void TCC3_0_Handler ( void ); 491 void TCC3_1_Handler ( void ); 492 void TCC3_2_Handler ( void ); 493 void TCC4_0_Handler ( void ); 494 void TCC4_1_Handler ( void ); 495 void TCC4_2_Handler ( void ); 496 void TC0_Handler ( void ); 497 void TC1_Handler ( void ); 498 void TC2_Handler ( void ); 499 void TC3_Handler ( void ); 500 void TC4_Handler ( void ); 501 void TC5_Handler ( void ); 502 void PDEC_0_Handler ( void ); 503 void PDEC_1_Handler ( void ); 504 void PDEC_2_Handler ( void ); 505 void ADC0_0_Handler ( void ); 506 void ADC0_1_Handler ( void ); 507 void ADC1_0_Handler ( void ); 508 void ADC1_1_Handler ( void ); 509 void AC_Handler ( void ); 510 void DAC_0_Handler ( void ); 511 void DAC_1_Handler ( void ); 512 void DAC_2_Handler ( void ); 513 void DAC_3_Handler ( void ); 514 void DAC_4_Handler ( void ); 515 void I2S_Handler ( void ); 516 void PCC_Handler ( void ); 517 void AES_Handler ( void ); 518 void TRNG_Handler ( void ); 519 void ICM_Handler ( void ); 520 void PUKCC_Handler ( void ); 521 void QSPI_Handler ( void ); 522 void SDHC0_Handler ( void ); 523 524 /* 525 * \brief Configuration of the Cortex-M4 Processor and Core Peripherals 526 */ 527 528 #define __CM4_REV 1 /*!< Core revision r0p1 */ 529 #define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ 530 #define __FPU_PRESENT 1 /*!< FPU present or not */ 531 #define __MPU_PRESENT 1 /*!< MPU present or not */ 532 #define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ 533 #define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ 534 #define __VTOR_PRESENT 1 /*!< VTOR present or not */ 535 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 536 537 /** 538 * \brief CMSIS includes 539 */ 540 541 #include <core_cm4.h> 542 #if !defined DONT_USE_CMSIS_INIT 543 #include "system_samd51.h" 544 #endif /* DONT_USE_CMSIS_INIT */ 545 546 /*@}*/ 547 548 /* ************************************************************************** */ 549 /** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51J20A */ 550 /* ************************************************************************** */ 551 /** \defgroup SAMD51J20A_api Peripheral Software API */ 552 /*@{*/ 553 554 #include "component/ac.h" 555 #include "component/adc.h" 556 #include "component/aes.h" 557 #include "component/ccl.h" 558 #include "component/cmcc.h" 559 #include "component/dac.h" 560 #include "component/dmac.h" 561 #include "component/dsu.h" 562 #include "component/eic.h" 563 #include "component/evsys.h" 564 #include "component/freqm.h" 565 #include "component/gclk.h" 566 #include "component/hmatrixb.h" 567 #include "component/icm.h" 568 #include "component/i2s.h" 569 #include "component/mclk.h" 570 #include "component/nvmctrl.h" 571 #include "component/oscctrl.h" 572 #include "component/osc32kctrl.h" 573 #include "component/pac.h" 574 #include "component/pcc.h" 575 #include "component/pdec.h" 576 #include "component/pm.h" 577 #include "component/port.h" 578 #include "component/qspi.h" 579 #include "component/ramecc.h" 580 #include "component/rstc.h" 581 #include "component/rtc.h" 582 #include "component/sdhc.h" 583 #include "component/sercom.h" 584 #include "component/supc.h" 585 #include "component/tc.h" 586 #include "component/tcc.h" 587 #include "component/trng.h" 588 #include "component/usb.h" 589 #include "component/wdt.h" 590 /*@}*/ 591 592 /* ************************************************************************** */ 593 /** REGISTERS ACCESS DEFINITIONS FOR SAMD51J20A */ 594 /* ************************************************************************** */ 595 /** \defgroup SAMD51J20A_reg Registers Access Definitions */ 596 /*@{*/ 597 598 #include "instance/ac.h" 599 #include "instance/adc0.h" 600 #include "instance/adc1.h" 601 #include "instance/aes.h" 602 #include "instance/ccl.h" 603 #include "instance/cmcc.h" 604 #include "instance/dac.h" 605 #include "instance/dmac.h" 606 #include "instance/dsu.h" 607 #include "instance/eic.h" 608 #include "instance/evsys.h" 609 #include "instance/freqm.h" 610 #include "instance/gclk.h" 611 #include "instance/hmatrix.h" 612 #include "instance/icm.h" 613 #include "instance/i2s.h" 614 #include "instance/mclk.h" 615 #include "instance/nvmctrl.h" 616 #include "instance/oscctrl.h" 617 #include "instance/osc32kctrl.h" 618 #include "instance/pac.h" 619 #include "instance/pcc.h" 620 #include "instance/pdec.h" 621 #include "instance/pm.h" 622 #include "instance/port.h" 623 #include "instance/pukcc.h" 624 #include "instance/qspi.h" 625 #include "instance/ramecc.h" 626 #include "instance/rstc.h" 627 #include "instance/rtc.h" 628 #include "instance/sdhc0.h" 629 #include "instance/sercom0.h" 630 #include "instance/sercom1.h" 631 #include "instance/sercom2.h" 632 #include "instance/sercom3.h" 633 #include "instance/sercom4.h" 634 #include "instance/sercom5.h" 635 #include "instance/supc.h" 636 #include "instance/tc0.h" 637 #include "instance/tc1.h" 638 #include "instance/tc2.h" 639 #include "instance/tc3.h" 640 #include "instance/tc4.h" 641 #include "instance/tc5.h" 642 #include "instance/tcc0.h" 643 #include "instance/tcc1.h" 644 #include "instance/tcc2.h" 645 #include "instance/tcc3.h" 646 #include "instance/tcc4.h" 647 #include "instance/trng.h" 648 #include "instance/usb.h" 649 #include "instance/wdt.h" 650 /*@}*/ 651 652 /* ************************************************************************** */ 653 /** PERIPHERAL ID DEFINITIONS FOR SAMD51J20A */ 654 /* ************************************************************************** */ 655 /** \defgroup SAMD51J20A_id Peripheral Ids Definitions */ 656 /*@{*/ 657 658 // Peripheral instances on HPB0 bridge 659 #define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ 660 #define ID_PM 1 /**< \brief Power Manager (PM) */ 661 #define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ 662 #define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ 663 #define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ 664 #define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ 665 #define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ 666 #define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ 667 #define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ 668 #define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ 669 #define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ 670 #define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ 671 #define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ 672 #define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ 673 #define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ 674 #define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ 675 676 // Peripheral instances on HPB1 bridge 677 #define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ 678 #define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ 679 #define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ 680 #define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ 681 #define ID_PORT 36 /**< \brief Port Module (PORT) */ 682 #define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ 683 #define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ 684 #define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ 685 #define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ 686 #define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ 687 #define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ 688 #define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ 689 #define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ 690 #define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ 691 #define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ 692 693 // Peripheral instances on HPB2 bridge 694 #define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ 695 #define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ 696 #define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ 697 #define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ 698 #define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ 699 #define ID_AC 72 /**< \brief Analog Comparators (AC) */ 700 #define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ 701 #define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ 702 #define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ 703 #define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ 704 #define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ 705 #define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ 706 707 // Peripheral instances on HPB3 bridge 708 #define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ 709 #define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ 710 #define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ 711 #define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ 712 #define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ 713 #define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ 714 #define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ 715 #define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ 716 717 // Peripheral instances on AHB (as if on bridge 4) 718 #define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ 719 720 #define ID_PERIPH_COUNT 129 /**< \brief Max number of peripheral IDs */ 721 /*@}*/ 722 723 /* ************************************************************************** */ 724 /** BASE ADDRESS DEFINITIONS FOR SAMD51J20A */ 725 /* ************************************************************************** */ 726 /** \defgroup SAMD51J20A_base Peripheral Base Address Definitions */ 727 /*@{*/ 728 729 #if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) 730 #define AC (0x42002000) /**< \brief (AC) APB Base Address */ 731 #define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ 732 #define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ 733 #define AES (0x42002400) /**< \brief (AES) APB Base Address */ 734 #define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ 735 #define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ 736 #define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ 737 #define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ 738 #define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ 739 #define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ 740 #define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ 741 #define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ 742 #define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ 743 #define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ 744 #define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ 745 #define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ 746 #define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ 747 #define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ 748 #define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ 749 #define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ 750 #define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ 751 #define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ 752 #define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ 753 #define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ 754 #define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ 755 #define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ 756 #define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ 757 #define PM (0x40000400) /**< \brief (PM) APB Base Address */ 758 #define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ 759 #define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ 760 #define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ 761 #define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ 762 #define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ 763 #define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ 764 #define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ 765 #define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ 766 #define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ 767 #define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ 768 #define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ 769 #define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ 770 #define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ 771 #define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ 772 #define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ 773 #define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ 774 #define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ 775 #define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ 776 #define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ 777 #define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ 778 #define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ 779 #define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ 780 #define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ 781 #define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ 782 #define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ 783 #define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ 784 #define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ 785 #define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ 786 #define USB (0x41000000) /**< \brief (USB) APB Base Address */ 787 #define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ 788 #else 789 #define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ 790 #define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ 791 #define AC_INSTS { AC } /**< \brief (AC) Instances List */ 792 793 #define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ 794 #define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ 795 #define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ 796 #define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ 797 798 #define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ 799 #define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ 800 #define AES_INSTS { AES } /**< \brief (AES) Instances List */ 801 802 #define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ 803 #define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ 804 #define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ 805 806 #define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ 807 #define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ 808 #define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ 809 #define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ 810 811 #define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ 812 #define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ 813 #define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ 814 815 #define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ 816 #define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ 817 #define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ 818 819 #define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ 820 #define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ 821 #define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ 822 823 #define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ 824 #define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ 825 #define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ 826 827 #define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ 828 #define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ 829 #define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ 830 831 #define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ 832 #define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ 833 #define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ 834 835 #define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ 836 #define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ 837 #define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ 838 839 #define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ 840 #define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ 841 #define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ 842 843 #define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ 844 #define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ 845 #define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ 846 847 #define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ 848 #define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ 849 #define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ 850 851 #define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ 852 #define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ 853 #define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ 854 855 #define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ 856 #define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ 857 #define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ 858 #define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ 859 #define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ 860 #define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ 861 862 #define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ 863 #define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ 864 #define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ 865 866 #define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ 867 #define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ 868 #define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ 869 870 #define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ 871 #define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ 872 #define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ 873 874 #define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ 875 #define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ 876 #define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ 877 878 #define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ 879 #define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ 880 #define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ 881 882 #define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ 883 #define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ 884 #define PM_INSTS { PM } /**< \brief (PM) Instances List */ 885 886 #define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ 887 #define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ 888 #define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ 889 890 #define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ 891 #define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ 892 #define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ 893 #define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ 894 895 #define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ 896 #define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ 897 #define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ 898 #define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ 899 900 #define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ 901 #define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ 902 #define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ 903 904 #define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ 905 #define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ 906 #define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ 907 908 #define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ 909 #define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ 910 #define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ 911 912 #define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ 913 #define SDHC_INST_NUM 1 /**< \brief (SDHC) Number of instances */ 914 #define SDHC_INSTS { SDHC0 } /**< \brief (SDHC) Instances List */ 915 916 #define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ 917 #define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ 918 #define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ 919 #define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ 920 #define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ 921 #define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ 922 #define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ 923 #define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ 924 925 #define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ 926 #define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ 927 #define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ 928 929 #define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ 930 #define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ 931 #define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ 932 #define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ 933 #define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ 934 #define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ 935 #define TC_INST_NUM 6 /**< \brief (TC) Number of instances */ 936 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */ 937 938 #define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ 939 #define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ 940 #define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ 941 #define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ 942 #define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ 943 #define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ 944 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ 945 946 #define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ 947 #define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ 948 #define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ 949 950 #define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ 951 #define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ 952 #define USB_INSTS { USB } /**< \brief (USB) Instances List */ 953 954 #define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ 955 #define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ 956 #define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ 957 958 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 959 /*@}*/ 960 961 /* ************************************************************************** */ 962 /** PORT DEFINITIONS FOR SAMD51J20A */ 963 /* ************************************************************************** */ 964 /** \defgroup SAMD51J20A_port PORT Definitions */ 965 /*@{*/ 966 967 #include "pio/samd51j20a.h" 968 /*@}*/ 969 970 /* ************************************************************************** */ 971 /** MEMORY MAPPING DEFINITIONS FOR SAMD51J20A */ 972 /* ************************************************************************** */ 973 974 #define HSRAM_SIZE _UL_(0x00040000) /* 256 kB */ 975 #define FLASH_SIZE _UL_(0x00100000) /* 1024 kB */ 976 #define FLASH_PAGE_SIZE 512 977 #define FLASH_NB_OF_PAGES 2048 978 #define FLASH_USER_PAGE_SIZE 512 979 #define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ 980 #define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ 981 982 #define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ 983 #define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ 984 #define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ 985 #define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ 986 #define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ 987 #define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ 988 #define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ 989 #define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ 990 #define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ 991 #define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ 992 #define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ 993 #define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ 994 #define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ 995 #define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ 996 #define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ 997 #define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ 998 #define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ 999 #define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ 1000 #define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ 1001 1002 #define DSU_DID_RESETVALUE _UL_(0x60060304) 1003 #define ADC0_TOUCH_LINES_NUM 32 1004 #define PORT_GROUPS 2 1005 1006 /* ************************************************************************** */ 1007 /** ELECTRICAL DEFINITIONS FOR SAMD51J20A */ 1008 /* ************************************************************************** */ 1009 1010 1011 #ifdef __cplusplus 1012 } 1013 #endif 1014 1015 /*@}*/ 1016 1017 #endif /* SAMD51J20A_H */ 1018
