| /Zephyr-latest/subsys/usb/device_next/class/ |
| D | usbd_uac2_macros.h | 237 #define SPATIAL_LOCATIONS_ARRAY(cluster) \ argument
238 DT_PROP(cluster, front_left), \
239 DT_PROP(cluster, front_right), \
240 DT_PROP(cluster, front_center), \
241 DT_PROP(cluster, low_frequency_effects), \
242 DT_PROP(cluster, back_left), \
243 DT_PROP(cluster, back_right), \
244 DT_PROP(cluster, front_left_of_center), \
245 DT_PROP(cluster, front_right_of_center), \
246 DT_PROP(cluster, back_center), \
[all …]
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| /Zephyr-latest/doc/hardware/peripherals/ |
| D | mbox.rst | 11 is providing one or more channels, each one targeting one other CPU cluster
12 (multiple channels can target the same cluster).
|
| /Zephyr-latest/doc/connectivity/bluetooth/api/audio/ |
| D | bluetooth-le-audio-arch.rst | 61 cluster=true;
69 cluster=true;
75 cluster=true;
81 cluster=true;
87 cluster=true;
91 cluster=true;
96 cluster=true;
103 cluster=true;
111 cluster=true;
116 cluster=true;
[all …]
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| /Zephyr-latest/doc/hardware/porting/ |
| D | soc_porting.rst | 21 - CPU Cluster: a cluster of one or more CPU cores.
195 one CPU cluster can be very different from another CPU cluster, therefore each
196 CPU cluster will often have its own :file:`.dtsi` file.
198 CPU cluster :file:`.dtsi` files should follow the naming scheme
199 :file:`<soc>_<cluster>.dtsi`. A :file:`<soc>_<cluster>.dtsi` file will look
294 SoC's When a SoC defines CPU cluster
|
| D | board_porting.rst | 76 Each SoC has one or more :term:`CPU cluster`, each containing one or more :term:`CPU core` of a par…
140 :term:`CPU cluster` and :term:`variant`: ``nrf5340/cpuapp/ns``
147 :samp:`{board name}[@{revision}][/{SoC}[/{CPU cluster}][/{variant}]]`.
164 - ``cpuapp``: The CPU cluster ``cpuapp``, which consists of a single Cortex-M33
165 CPU core. The number of cores in a CPU cluster cannot be determined from the
190 If you need to add a SoC, CPU cluster, or even architecture support, this is the
|
| /Zephyr-latest/soc/sensry/ganymed/sy1xx/ |
| D | Kconfig.defconfig | 25 # default cluster id 0x3e, core 0 (FC) => 0x3e0 == 992
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| /Zephyr-latest/doc/ |
| D | glossary.rst | 66 :term:`SoC`, :term:`CPU cluster` and :term:`variant`.
83 CPU cluster
87 cluster. Multiple CPU clusters (each of one or more cores) can coexist in
92 instructions sequentially. CPU cores are part of a :term:`CPU cluster`,
132 least one :term:`CPU cluster` (in turn with at least one :term:`CPU core`),
154 and :term:`CPU cluster`. Common uses of the variant concept include
|
| /Zephyr-latest/soc/snps/nsim/arc_classic/ |
| D | linker.ld | 30 /* SRAM - memory available for all cores in cluster. Can be used for both instructions and data */
|
| /Zephyr-latest/boards/phytec/phyboard_lyra/doc/ |
| D | phyboard_lyra_am62xx_a53.rst | 10 processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M4 core.
|
| D | phyboard_lyra_am62xx_m4.rst | 29 quad Cortex-A53 cluster and a single Cortex-M4 core in the MCU domain. Zephyr
|
| /Zephyr-latest/soc/nordic/nrf54h/bicr/ |
| D | bicrgen.py | 49 cluster = regs.find(f".//registers/cluster[name='{cluster_name}']")
50 self._offset = int(cluster.find("addressOffset").text, 0)
52 self._reg = cluster.find(f".//register[name='{reg_name}']")
|
| /Zephyr-latest/dts/arm/nxp/ |
| D | nxp_ke1xz.dtsi | 240 compatible = "nxp,gpio-cluster";
285 compatible = "nxp,gpio-cluster";
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| /Zephyr-latest/boards/toradex/verdin_imx8mp/doc/ |
| D | index.rst | 34 Regarding the Cortex-A53 cluster, it employs the ARMv8-A architecture as a mid-range and
35 energy-efficient processor. With four cores in this cluster, each core is equipped with its own L1
36 memory system. Moreover, the cluster incorporates a unified L2 cache that offers supplementary
|
| /Zephyr-latest/boards/nxp/imx8mn_evk/doc/ |
| D | index.rst | 7 processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M7 core.
|
| /Zephyr-latest/boards/intel/socfpga_std/cyclonev_socdk/doc/ |
| D | index.rst | 254 Info : fpgasoc.cpu.0: MPIDR level2 0, cluster 0, core 0, multi core, no SMT
290 Info : fpgasoc.cpu.0: MPIDR level2 0, cluster 0, core 0, multi core, no SMT
317 Info : fpgasoc.cpu.0: MPIDR level2 0, cluster 0, core 0, multi core, no SMT
|
| /Zephyr-latest/boards/ti/sk_am62/doc/ |
| D | index.rst | 20 cluster and a single Cortex-M4 core in the MCU domain. Zephyr is ported to run on
|
| /Zephyr-latest/boards/phytec/phyboard_electra/doc/ |
| D | index.rst | 29 dual Cortex-A53 cluster and two dual Cortex-R5F cores in the MAIN domain as
|
| /Zephyr-latest/boards/phytec/phyboard_nash/doc/ |
| D | index.rst | 15 i.MX93 MPU is composed of one cluster of 2x Cortex-A55 cores and a single
|
| /Zephyr-latest/boards/ |
| D | Kconfig | 27 Contains the board target (full string including name, revision, soc, cluster and
|
| /Zephyr-latest/boards/nxp/imx8mq_evk/doc/ |
| D | index.rst | 7 processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M4 core.
|
| /Zephyr-latest/boards/nxp/imx8mm_evk/doc/ |
| D | index.rst | 7 processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M4 core.
|
| /Zephyr-latest/boards/toradex/verdin_imx8mm/doc/ |
| D | index.rst | 10 processor cluster. The cores provide complete 64-bit Armv8-A support while maintaining seamless
|
| /Zephyr-latest/arch/arm64/core/ |
| D | Kconfig | 73 This option signifies the use of a Cortex-A76 and A55 big little CPU cluster
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| /Zephyr-latest/boards/nxp/imx8mp_evk/doc/ |
| D | index.rst | 7 processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M7 core.
|
| /Zephyr-latest/boards/nxp/imx93_evk/doc/ |
| D | index.rst | 12 i.MX93 MPU is composed of one cluster of 2x Cortex-A55 cores and a single
|
