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Searched refs:clock_control_subsys_t (Results 1 – 25 of 354) sorted by relevance

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/Zephyr-latest/include/zephyr/drivers/
Dclock_control.h58 typedef void *clock_control_subsys_t; typedef
75 clock_control_subsys_t subsys,
79 clock_control_subsys_t sys);
82 clock_control_subsys_t sys,
86 clock_control_subsys_t sys,
92 clock_control_subsys_t sys);
95 clock_control_subsys_t sys,
99 clock_control_subsys_t sys,
126 clock_control_subsys_t sys) in clock_control_on()
149 clock_control_subsys_t sys) in clock_control_off()
[all …]
/Zephyr-latest/samples/drivers/clock_control_litex/src/
Dmain.c69 clock_control_subsys_t sub_system = (clock_control_subsys_t)&setup; in litex_clk_test_getters()
99 clock_control_subsys_t sub_system1 = (clock_control_subsys_t)&setup1; in litex_clk_test_single()
100 clock_control_subsys_t sub_system2 = (clock_control_subsys_t)&setup2; in litex_clk_test_single()
124 clock_control_subsys_t sub_system = (clock_control_subsys_t)&setup; in litex_clk_test_freq()
134 sub_system = (clock_control_subsys_t)&setup; in litex_clk_test_freq()
162 sub_system = (clock_control_subsys_t)&setup; in litex_clk_test_freq()
192 clock_control_subsys_t sub_system1 = (clock_control_subsys_t)&setup1; in litex_clk_test_phase()
193 clock_control_subsys_t sub_system2 = (clock_control_subsys_t)&setup2; in litex_clk_test_phase()
208 sub_system2 = (clock_control_subsys_t)&setup2; in litex_clk_test_phase()
235 clock_control_subsys_t sub_system1 = (clock_control_subsys_t)&setup1; in litex_clk_test_duty()
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/src/
Dtest_stm32_clock_configuration_i2c.c35 (clock_control_subsys_t) clk, in i2c_set_clock()
57 (clock_control_subsys_t)clk); in i2c_set_clock()
62 (clock_control_subsys_t) clk, in i2c_set_clock()
83 (clock_control_subsys_t)&pclken[0]); in ZTEST()
89 (clock_control_subsys_t) &pclken[0]); in ZTEST()
95 (clock_control_subsys_t)&pclken[0]); in ZTEST()
114 (clock_control_subsys_t) &pclken[0], in ZTEST()
128 (clock_control_subsys_t) &pclken[0]); in ZTEST()
Dtest_stm32_clock_configuration_adc.c67 (clock_control_subsys_t)&pclken[0]); in ZTEST()
73 (clock_control_subsys_t) &pclken[0]); in ZTEST()
79 (clock_control_subsys_t)&pclken[0]); in ZTEST()
87 (clock_control_subsys_t) &pclken[1], in ZTEST()
115 (clock_control_subsys_t)&pclken[1]); in ZTEST()
120 (clock_control_subsys_t) &pclken[1], in ZTEST()
140 (clock_control_subsys_t) &pclken[0]); in ZTEST()
Dtest_stm32_clock_configuration_lptim.c34 (clock_control_subsys_t) &pclken[0]); in ZTEST()
43 (clock_control_subsys_t) &pclken[1], in ZTEST()
65 (clock_control_subsys_t) &pclken[1], in ZTEST()
81 (clock_control_subsys_t) &pclken[0], in ZTEST()
95 (clock_control_subsys_t) &pclken[0]); in ZTEST()
Dtest_stm32_clock_configuration_i2s.c29 (clock_control_subsys_t) &pclken[0]); in ZTEST()
39 (clock_control_subsys_t) &pclken[1], in ZTEST()
57 (clock_control_subsys_t) &pclken[1], in ZTEST()
70 (clock_control_subsys_t) &pclken[0]); in ZTEST()
Dtest_stm32_clock_configuration_sdmmc.c39 (clock_control_subsys_t) &pclken[0]); in ZTEST()
54 (clock_control_subsys_t) &pclken[1], in ZTEST()
113 (clock_control_subsys_t) &pclken[1], in ZTEST()
124 (clock_control_subsys_t) &pclken[0]); in ZTEST()
/Zephyr-latest/tests/boards/espressif/rtc_clk/src/
Drtc_clk_test.c32 (clock_control_subsys_t)ESP32_CLOCK_CONTROL_SUBSYS_CPU, &rate); in rtc_clk_setup()
37 clk_dev, (clock_control_subsys_t)ESP32_CLOCK_CONTROL_SUBSYS_RTC_FAST, &rate); in rtc_clk_setup()
42 clk_dev, (clock_control_subsys_t)ESP32_CLOCK_CONTROL_SUBSYS_RTC_SLOW, &rate); in rtc_clk_setup()
64 clk_dev, (clock_control_subsys_t)ESP32_CLOCK_CONTROL_SUBSYS_CPU, &clk_cfg); in ZTEST()
68 clk_dev, (clock_control_subsys_t)ESP32_CLOCK_CONTROL_SUBSYS_CPU, &cpu_rate); in ZTEST()
104 clk_dev, (clock_control_subsys_t)ESP32_CLOCK_CONTROL_SUBSYS_CPU, &clk_cfg); in ZTEST()
108 clk_dev, (clock_control_subsys_t)ESP32_CLOCK_CONTROL_SUBSYS_CPU, &cpu_rate); in ZTEST()
147 clk_dev, (clock_control_subsys_t)ESP32_CLOCK_CONTROL_SUBSYS_RTC_FAST, in ZTEST()
152 clk_dev, (clock_control_subsys_t)ESP32_CLOCK_CONTROL_SUBSYS_RTC_FAST, in ZTEST()
199 clk_dev, (clock_control_subsys_t)ESP32_CLOCK_CONTROL_SUBSYS_RTC_SLOW, in ZTEST()
[all …]
/Zephyr-latest/tests/drivers/clock_control/clock_control_api/src/
Dtest_clock_control.c22 clock_control_subsys_t subsys,
26 clock_control_subsys_t subsys);
28 static void setup_instance(const struct device *dev, clock_control_subsys_t subsys) in setup_instance()
52 clock_control_subsys_t subsys) in tear_down_instance()
80 clock_control_subsys_t subsys, in test_with_single_instance()
116 clock_control_subsys_t subsys, in test_on_off_status_instance()
147 clock_control_subsys_t subsys, in async_capable_callback()
154 static bool async_capable(const struct device *dev, clock_control_subsys_t subsys) in async_capable()
184 clock_control_subsys_t subsys, in clock_on_callback()
193 clock_control_subsys_t subsys, in test_async_on_instance()
[all …]
/Zephyr-latest/drivers/clock_control/
Dclock_control_fixed_rate.c17 clock_control_subsys_t sys) in fixed_rate_clk_on()
26 clock_control_subsys_t sys) in fixed_rate_clk_off()
35 clock_control_subsys_t sys) in fixed_rate_clk_get_status()
41 clock_control_subsys_t sys, in fixed_rate_clk_get_rate()
Dclock_control_rv32m1_pcc.c25 clock_control_subsys_t sub_system) in clock_ip()
33 clock_control_subsys_t sub_system) in rv32m1_pcc_on()
40 clock_control_subsys_t sub_system) in rv32m1_pcc_off()
47 clock_control_subsys_t sub_system, in rv32m1_pcc_get_rate()
Dclock_control_silabs_series.c22 clock_control_subsys_t sys);
24 static int silabs_clock_control_on(const struct device *dev, clock_control_subsys_t sys) in silabs_clock_control_on()
41 static int silabs_clock_control_off(const struct device *dev, clock_control_subsys_t sys) in silabs_clock_control_off()
54 static int silabs_clock_control_get_rate(const struct device *dev, clock_control_subsys_t sys, in silabs_clock_control_get_rate()
69 clock_control_subsys_t sys) in silabs_clock_control_get_status()
Dclock_control_mcux_mcg.c22 clock_control_subsys_t sub_system) in mcux_mcg_on()
28 clock_control_subsys_t sub_system) in mcux_mcg_off()
34 clock_control_subsys_t sub_system, in mcux_mcg_get_rate()
Dclock_control_silabs_siwx91x.c29 static int siwx91x_clock_on(const struct device *dev, clock_control_subsys_t sys) in siwx91x_clock_on()
88 static int siwx91x_clock_off(const struct device *dev, clock_control_subsys_t sys) in siwx91x_clock_off()
122 static int siwx91x_clock_get_rate(const struct device *dev, clock_control_subsys_t sys, in siwx91x_clock_get_rate()
151 clock_control_subsys_t sys) in siwx91x_clock_get_status()
179 siwx91x_clock_on(dev, (clock_control_subsys_t)SIWX91X_CLK_ULP_I2C); in siwx91x_clock_init()
183 siwx91x_clock_on(dev, (clock_control_subsys_t)SIWX91X_CLK_I2C0); in siwx91x_clock_init()
187 siwx91x_clock_on(dev, (clock_control_subsys_t)SIWX91X_CLK_I2C1); in siwx91x_clock_init()
Dclock_control_mcux_scg_k4.c24 static int mcux_scg_k4_on(const struct device *dev, clock_control_subsys_t sub_system) in mcux_scg_k4_on()
29 static int mcux_scg_k4_off(const struct device *dev, clock_control_subsys_t sub_system) in mcux_scg_k4_off()
34 static int mcux_scg_k4_get_rate(const struct device *dev, clock_control_subsys_t sub_system, in mcux_scg_k4_get_rate()
Dclock_control_arm_scmi.c20 clock_control_subsys_t clk, bool on) in scmi_clock_on_off()
43 static int scmi_clock_on(const struct device *dev, clock_control_subsys_t clk) in scmi_clock_on()
48 static int scmi_clock_off(const struct device *dev, clock_control_subsys_t clk) in scmi_clock_off()
54 clock_control_subsys_t clk, uint32_t *rate) in scmi_clock_get_rate()
Dclock_control_nxp_s32.c19 clock_control_subsys_t sub_system) in nxp_s32_clock_on()
33 clock_control_subsys_t sub_system) in nxp_s32_clock_off()
47 clock_control_subsys_t sub_system, in nxp_s32_clock_get_rate()
Dclock_control_sam_pmc.c22 clock_control_subsys_t sys) in atmel_sam_clock_control_on()
48 clock_control_subsys_t sys) in atmel_sam_clock_control_off()
74 clock_control_subsys_t sys, in atmel_sam_clock_control_get_rate()
104 clock_control_subsys_t sys) in atmel_sam_clock_control_get_status()
Dclock_control_si32_apb.c23 static int clock_control_si32_apb_on(const struct device *dev, clock_control_subsys_t sys) in clock_control_si32_apb_on()
28 static int clock_control_si32_apb_off(const struct device *dev, clock_control_subsys_t sys) in clock_control_si32_apb_off()
34 static int clock_control_si32_apb_get_rate(const struct device *dev, clock_control_subsys_t sys, in clock_control_si32_apb_get_rate()
Dclock_control_mcux_pcc.c33 clock_control_subsys_t sub_system, in get_clock_encoding()
58 clock_control_subsys_t sub_system) in mcux_pcc_on()
74 clock_control_subsys_t sub_system) in mcux_pcc_off()
90 clock_control_subsys_t sub_system, in mcux_pcc_get_rate()
Dclock_control_ambiq.c24 static int ambiq_clock_on(const struct device *dev, clock_control_subsys_t sub_system) in ambiq_clock_on()
56 static int ambiq_clock_off(const struct device *dev, clock_control_subsys_t sub_system) in ambiq_clock_off()
89 static inline int ambiq_clock_get_rate(const struct device *dev, clock_control_subsys_t sub_system, in ambiq_clock_get_rate()
100 static inline int ambiq_clock_configure(const struct device *dev, clock_control_subsys_t sub_system, in ambiq_clock_configure()
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/src/
Dtest_stm32_clock_configuration.c46 (clock_control_subsys_t) &pclken[0]); in ZTEST()
55 (clock_control_subsys_t) &pclken[1], in ZTEST()
77 (clock_control_subsys_t) &pclken[1], in ZTEST()
90 (clock_control_subsys_t) &pclken[0], in ZTEST()
102 (clock_control_subsys_t) &pclken[0]); in ZTEST()
/Zephyr-latest/include/zephyr/drivers/clock_control/
Dnrf_clock_control.h43 ((clock_control_subsys_t)CLOCK_CONTROL_NRF_TYPE_HFCLK)
45 ((clock_control_subsys_t)CLOCK_CONTROL_NRF_TYPE_LFCLK)
47 ((clock_control_subsys_t)CLOCK_CONTROL_NRF_TYPE_HFCLK192M)
49 ((clock_control_subsys_t)CLOCK_CONTROL_NRF_TYPE_HFCLKAUDIO)
133 struct onoff_manager *z_nrf_clock_control_get_onoff(clock_control_subsys_t sys);
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/src/
Dtest_stm32_clock_configuration.c47 (clock_control_subsys_t) &spi1_reg_clk_cfg); in ZTEST()
58 (clock_control_subsys_t) &spi1_domain_clk_cfg, in ZTEST()
113 (clock_control_subsys_t) &spi1_domain_clk_cfg, in ZTEST()
126 (clock_control_subsys_t) &spi1_reg_clk_cfg, in ZTEST()
140 (clock_control_subsys_t) &spi1_reg_clk_cfg); in ZTEST()
/Zephyr-latest/boards/arduino/nicla_vision/
Dcamera_ext_clock.c25 ret = clock_control_on(cam_ext_clk_dev, (clock_control_subsys_t)0); in camera_ext_clock_enable()
31 ret = clock_control_get_rate(cam_ext_clk_dev, (clock_control_subsys_t)0, &rate); in camera_ext_clock_enable()

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