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Searched refs:MCO2_SEL (Results 1 – 10 of 10) sorted by relevance

/Zephyr-latest/samples/boards/st/mco/boards/
Dnucleo_f429zi.overlay27 clocks = <&rcc STM32_SRC_HSE MCO2_SEL(MCO_SEL_HSE)>;
Dstm32f746g_disco.overlay30 clocks = <&rcc STM32_SRC_HSE MCO2_SEL(MCO2_SEL_HSE)>;
Dnucleo_f411re.overlay25 clocks = <&rcc STM32_SRC_PLLI2S_R MCO2_SEL(1)>;
Dnucleo_f446ze.overlay25 clocks = <&rcc STM32_SRC_PLLI2S_R MCO2_SEL(1)>;
/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dstm32f4_clock.h84 #define MCO2_SEL(val) STM32_MCO_CFGR(val, 0x3, 30, CFGR_REG) macro
Dstm32c0_clock.h81 #define MCO2_SEL(val) STM32_MCO_CFGR(val, 0x7, 16, CFGR1_REG) macro
Dstm32f7_clock.h83 #define MCO2_SEL(val) STM32_MCO_CFGR(val, 0x3, 30, CFGR_REG) macro
Dstm32h7rs_clock.h137 #define MCO2_SEL(val) STM32_MCO_CFGR(val, 0x7, 29, CFGR_REG) macro
Dstm32h7_clock.h141 #define MCO2_SEL(val) STM32_MCO_CFGR(val, 0xF, 29, CFGR_REG) macro
Dstm32h5_clock.h156 #define MCO2_SEL(val) STM32_MCO_CFGR(val, 0x7, 25, CFGR1_REG) macro