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Searched refs:DT_INST_PARENT (Results 1 – 25 of 119) sorted by relevance

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/Zephyr-latest/drivers/pwm/
Dpwm_max32.c130 .regs = (mxc_tmr_regs_t *)DT_REG_ADDR(DT_INST_PARENT(_num)), \
132 .clock = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_INST_PARENT(_num))), \
133 .perclk.bus = DT_CLOCKS_CELL(DT_INST_PARENT(_num), offset), \
134 .perclk.bit = DT_CLOCKS_CELL(DT_INST_PARENT(_num), bit), \
135 .perclk.clk_src = DT_PROP(DT_INST_PARENT(_num), clock_source), \
136 .prescaler = DT_PROP(DT_INST_PARENT(_num), prescaler), \
Dpwm_gd32.c195 .reg = DT_REG_ADDR(DT_INST_PARENT(i)), \
196 .clkid = DT_CLOCKS_CELL(DT_INST_PARENT(i), id), \
197 .reset = RESET_DT_SPEC_GET(DT_INST_PARENT(i)), \
198 .prescaler = DT_PROP(DT_INST_PARENT(i), prescaler), \
199 .channels = DT_PROP(DT_INST_PARENT(i), channels), \
200 .is_32bit = DT_PROP(DT_INST_PARENT(i), is_32bit), \
201 .is_advanced = DT_PROP(DT_INST_PARENT(i), is_advanced), \
Dpwm_nxp_flexio.c321 .flexio_dev = DEVICE_DT_GET(DT_INST_PARENT(n)), \
322 .flexio_base = (FLEXIO_Type *)DT_REG_ADDR(DT_INST_PARENT(n)), \
324 .clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_INST_PARENT(n))), \
325 .clock_subsys = (clock_control_subsys_t)DT_CLOCKS_CELL(DT_INST_PARENT(n), name),\
Dpwm_ite_it8801.c161 .mfd = DEVICE_DT_GET(DT_INST_PARENT(inst)), \
162 .i2c_dev = I2C_DT_SPEC_GET(DT_INST_PARENT(inst)), \
/Zephyr-latest/drivers/serial/
Duart_renesas_ra_sci.c1084 DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, irq)}, \
1111 DT_IRQ_BY_NAME(DT_INST_PARENT(index), txi, irq)}, \
1139 R_ICU->IELSR[DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, irq)] = \
1141 R_ICU->IELSR[DT_IRQ_BY_NAME(DT_INST_PARENT(index), txi, irq)] = \
1143 R_ICU->IELSR[DT_IRQ_BY_NAME(DT_INST_PARENT(index), tei, irq)] = \
1145 R_ICU->IELSR[DT_IRQ_BY_NAME(DT_INST_PARENT(index), eri, irq)] = \
1148 IRQ_CONNECT(DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, irq), \
1149 DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, priority), \
1151 IRQ_CONNECT(DT_IRQ_BY_NAME(DT_INST_PARENT(index), txi, irq), \
1152 DT_IRQ_BY_NAME(DT_INST_PARENT(index), txi, priority), \
[all …]
Duart_renesas_ra8_sci_b.c1012 R_ICU->IELSR[DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, irq)] = \
1014 R_ICU->IELSR[DT_IRQ_BY_NAME(DT_INST_PARENT(index), txi, irq)] = \
1016 R_ICU->IELSR[DT_IRQ_BY_NAME(DT_INST_PARENT(index), tei, irq)] = \
1018 R_ICU->IELSR[DT_IRQ_BY_NAME(DT_INST_PARENT(index), eri, irq)] = \
1021 IRQ_CONNECT(DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, irq), \
1022 DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, priority), \
1024 IRQ_CONNECT(DT_IRQ_BY_NAME(DT_INST_PARENT(index), txi, irq), \
1025 DT_IRQ_BY_NAME(DT_INST_PARENT(index), txi, priority), \
1027 IRQ_CONNECT(DT_IRQ_BY_NAME(DT_INST_PARENT(index), tei, irq), \
1028 DT_IRQ_BY_NAME(DT_INST_PARENT(index), tei, priority), \
[all …]
Duart_renesas_ra.c659 PINCTRL_DT_DEFINE(DT_INST_PARENT(n)); \
661 .regs = DT_REG_ADDR(DT_INST_PARENT(n)), \
662 .clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_INST_PARENT(n))), \
665 .mstp = DT_CLOCKS_CELL_BY_IDX(DT_INST_PARENT(n), 0, mstp), \
666 .stop_bit = DT_CLOCKS_CELL_BY_IDX(DT_INST_PARENT(n), 0, stop_bit), \
668 .pcfg = PINCTRL_DT_DEV_CONFIG_GET(DT_INST_PARENT(n)), \
675 ra_icu_irq_connect_dynamic(DT_IRQ_BY_NAME(DT_INST_PARENT(n), name, irq), \
676 DT_IRQ_BY_NAME(DT_INST_PARENT(n), name, priority), isr, dev, \
677 DT_IRQ_BY_NAME(DT_INST_PARENT(n), name, flags));
/Zephyr-latest/drivers/usb/udc/
Dudc_renesas_ra.c674 #define USB_MODULE_NUMBER(n) ((DT_REG_ADDR(DT_INST_PARENT(n))) == R_USB_HS0_BASE ? 1 : 0)
681 data->udc_cfg.hs_irq = DT_IRQ_BY_NAME(DT_INST_PARENT(n), usbhs_ir, irq); \
682 data->udc_cfg.hsirq_d0 = DT_IRQ_BY_NAME(DT_INST_PARENT(n), usbhs_d0, irq); \
683 data->udc_cfg.hsirq_d1 = DT_IRQ_BY_NAME(DT_INST_PARENT(n), usbhs_d1, irq); \
684 data->udc_cfg.hsipl = DT_IRQ_BY_NAME(DT_INST_PARENT(n), usbhs_ir, priority); \
685 data->udc_cfg.hsipl_d0 = DT_IRQ_BY_NAME(DT_INST_PARENT(n), usbhs_d0, priority); \
686 data->udc_cfg.hsipl_d1 = DT_IRQ_BY_NAME(DT_INST_PARENT(n), usbhs_d1, priority); \
697 PINCTRL_DT_DEFINE(DT_INST_PARENT(n)); \
718 static struct udc_ep_config ep_cfg_in##n[DT_PROP(DT_INST_PARENT(n), num_bidir_endpoints)]; \
720 ep_cfg_out##n[DT_PROP(DT_INST_PARENT(n), num_bidir_endpoints)]; \
[all …]
/Zephyr-latest/drivers/mipi_dbi/
Dmipi_dbi_stm32_fmc.c182 UTIL_INC(DT_REG_ADDR_RAW(DT_INST_PARENT(n))))
193 .fmc_address_setup_time = DT_PROP_BY_IDX(DT_INST_PARENT(n), st_timing, 0), \
194 .fmc_data_setup_time = DT_PROP_BY_IDX(DT_INST_PARENT(n), st_timing, 2), \
195 .fmc_memory_width = DT_PROP_BY_IDX(DT_INST_PARENT(n), st_control, 2), \
/Zephyr-latest/drivers/sensor/st/qdec_stm32/
Dqdec_stm32.c151 .timer_inst = ((TIM_TypeDef *)DT_REG_ADDR(DT_INST_PARENT(n))), \
152 .pclken = {.bus = DT_CLOCKS_CELL(DT_INST_PARENT(n), bus), \
153 .enr = DT_CLOCKS_CELL(DT_INST_PARENT(n), bits)}, \
/Zephyr-latest/drivers/gpio/
Dgpio_emul_sdl.c80 BUILD_ASSERT(DT_NODE_HAS_COMPAT_STATUS(DT_INST_PARENT(inst), \
90 .emul = DEVICE_DT_GET(DT_INST_PARENT(inst)), \
/Zephyr-latest/drivers/kscan/
Dkscan_input.c104 INPUT_CALLBACK_DEFINE_NAMED(DEVICE_DT_GET(DT_INST_PARENT(index)), \
109 .input_dev = DEVICE_DT_GET(DT_INST_PARENT(index)), \
/Zephyr-latest/drivers/counter/
Dcounter_mcux_lpc_rtc.c429 IRQ_CONNECT(DT_IRQN(DT_INST_PARENT(n)), \
430 DT_IRQ(DT_INST_PARENT(n), priority), \
433 irq_enable(DT_IRQN(DT_INST_PARENT(n))); \
435 EnableDeepSleepIRQ(DT_IRQN(DT_INST_PARENT(n))); \
442 .base = (RTC_Type *)DT_REG_ADDR(DT_INST_PARENT(id)), \
443 .rtc_dev = DEVICE_DT_GET_OR_NULL(DT_INST_PARENT(id)), \
/Zephyr-latest/drivers/sensor/qdec_sam/
Dqdec_sam.c128 .regs = (Tc *)DT_REG_ADDR(DT_INST_PARENT(n)), \
130 .clock_cfg = SAM_DT_CLOCKS_PMC_CFG(DT_INST_PARENT(n)), \
/Zephyr-latest/drivers/watchdog/
Dwdt_npm2100.c139 .mfd = DEVICE_DT_GET(DT_INST_PARENT(n)), \
140 .i2c = I2C_DT_SPEC_GET(DT_INST_PARENT(n)), \
/Zephyr-latest/drivers/mdio/
Dmdio_nxp_enet.c249 .module_dev = DEVICE_DT_GET(DT_INST_PARENT(inst)), \
251 .clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_INST_PARENT(inst))), \
253 DT_INST_PARENT(inst), 0, name), \
/Zephyr-latest/subsys/input/
Dinput_keymap.c102 INPUT_CALLBACK_DEFINE_NAMED(DEVICE_DT_GET(DT_INST_PARENT(inst)), keymap_cb, \
112 .input_dev = DEVICE_DT_GET(DT_INST_PARENT(inst)), \
/Zephyr-latest/drivers/bbram/
Dbbram_stm32.c117 .parent = DEVICE_DT_GET(DT_INST_PARENT(inst)), \
118 .base_addr = DT_REG_ADDR(DT_INST_PARENT(inst)) + STM32_BKP_REG_OFFSET, \
/Zephyr-latest/drivers/pinctrl/
Dpinctrl_sifive.c16 #define MAX_PIN_NUM DT_PROP(DT_INST_PARENT(0), ngpios)
/Zephyr-latest/drivers/w1/
Dw1_ds2482-800_channel.c165 .parent = DEVICE_DT_GET(DT_INST_PARENT(inst)), \
166 .i2c_spec = I2C_DT_SPEC_GET(DT_INST_PARENT(inst)), \
/Zephyr-latest/drivers/reset/
Dreset_lpc_syscon.c63 (void *)(DT_REG_ADDR(DT_INST_PARENT(0)) + 0x100),
Dreset_gd32.c70 .base = DT_REG_ADDR(DT_INST_PARENT(0)),
/Zephyr-latest/drivers/i2c/
Di2c_sc18im704.c335 .bus = DEVICE_DT_GET(DT_BUS(DT_INST_PARENT(n))), \
336 .bus_speed = DT_PROP_OR(DT_INST_PARENT(n), target_speed, 9600), \
337 .reset_gpios = GPIO_DT_SPEC_GET_OR(DT_INST_PARENT(n), reset_gpios, {0}), \
/Zephyr-latest/drivers/memc/
Dmemc_stm32_nor_psram.c168 .nor_psram = (FMC_NORSRAM_TypeDef *)(DT_REG_ADDR(DT_INST_PARENT(0)) + SRAM_OFFSET),
169 .extended = (FMC_NORSRAM_EXTENDED_TypeDef *)(DT_REG_ADDR(DT_INST_PARENT(0))
/Zephyr-latest/drivers/sensor/maxim/max31790/
Dmax31790_fan_fault.c71 .i2c = I2C_DT_SPEC_GET(DT_INST_PARENT(inst)), \

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